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Process for fabricating a semiconductor electrostatic discharge (ESD) protective device

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US5585299A
US5585299A US08617600 US61760096A US5585299A US 5585299 A US5585299 A US 5585299A US 08617600 US08617600 US 08617600 US 61760096 A US61760096 A US 61760096A US 5585299 A US5585299 A US 5585299A
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region
layer
esd
protective
functional
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US08617600
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Chen-Chung Hsu
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United Microelectronics Corp
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United Microelectronics Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823443MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements

Abstract

Disclosed is a process for fabricating a semiconductor device having both a functional region and an electrostatic discharge (ESD) protective region formed on the same substrate. A gate oxide layer is formed on both the functional region and the ESD protective region and a polysilicon layer is formed on the gate oxide layer. A mask is used to etch the polysilicon layer and the gate oxide layer to form gate electrode and also expose part of the silicon substrate. Ions are implanted to form a lightly doped source/drain electrode. An ESD mask is used to selectively remove part of the oxide layer on the functional region, thus forming an isolator on lateral sides of the gate electrode in the functional region. Ions are then implanted to form a heavily doped region and lightly doped source/drain electrode. After that, a metallization layer is formed by sputtering deposition and then rapid thermal annealing and etching are performed to form self-aligning TiSi2 layer on the gate electrode and on exposed surface of the source/drain electrode. Then the ESD mask is used again to selectively remove part of the oxide layer on the ESD protective region. Finally, ions are implanted to form a heavily doped region. Using the same ESD mask to construct both the ESD protective region and the functional region provides considerable cost savings.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to semiconductor fabrication. More particularly, the invention relates to a process for fabricating a protective device for protecting semiconductor devices and circuits against electrostatic discharge (ESD).

2. Description of Related Art

Electrostatic discharge (ESD) protection can be provided for semiconductor devices using a dual diffusion source/drain (DDD) field effect transistor and a lightly doped source/drain (LDD) field effect transistor. The DDD field effect transistor provides better protection than the LDD field effect transistor. To enhance the ESD protection capability of the LDD field effect transistor, additional masking and ion implanting steps are required to raise the concentration of impurities in the LDD region.

FIGS. 1A-1C (Prior Art) are sectional diagrams of a semiconductor device depicting the steps of a conventional process for fabricating an ESD protective device. In each of these diagrams, the left half part shows the structure for the semiconductor device (hereinafter referred to as "functional region") intended to be protected by the conventional ESD protective device, and the right half part shows the structure for the conventional ESD protective device (hereinafter referred to as "ESD protective region").

Referring to FIG. 1A, in the first step a silicon substrate is 10 prepared and on which a gate electrode 12 is formed. Ions are implanted to form a lightly doped source/drain region 14.

Referring to FIG. 1B (Prior Art), subsequently an isolator 16 is formed on lateral sides of the gate electrode 12. Prior to forming the ESD protective device in the wafer, the isolator 16 must be removed by using a mask. In the subsequent step, another ion implantation is carried out with a high concentration of dopants, whereby the functional region is formed with an LDD structure and the ESD protective region is formed into a structure as shown in the right part of FIG. 1C (Prior Art). In this structure, the heavily doped region 18 in the source/drain electrode includes the originally formed lightly doped region 14, so that a better ESD protective effect is provided.

It is a drawback of the conventional process that, in order to provide the ESD protective region with high ESD capability and retain the LDD structure in the functional region, an additional mask must be used to remove the isolator 16 in the ESD protective region while retaining the isolator in the functional region. Moreover, in the step of forming metal silicide in the functional region by using self-aligning silicide process, another mask must be used to etch the metal silicide or to retard its growth.

Since the ESD is below 2000 V both for the LDD structure and the self-aligning silicide, the process is not suitable for use to form the ESD protective device. However, since the functional region must have such a structure, the use of two masks, one in the ESD protective region for etching the isolator and the other in the self-aligning silicide process for etching the metal silicide used for pattern definition, is quite costly for the overall fabrication process of the semiconductor device.

SUMMARY OF THE INVENTION

It is therefore a primary objective of the present invention to provide a process for fabricating an ESD protective device on a semiconductor device, by which only one mask is needed to form both the ESD protective region and the functional region of the semiconductor device.

In accordance with the foregoing and other objectives of the present invention, there is provided a new and improved method for fabricating an ESD protective device. It is an important aspect of the present invention that an ESD mask is used to form both an ESD protective region and a functional region. The functional region includes a lightly doped source/drain electrode and a self-aligning silicide structure while the ESD protective region includes no self-aligning silicide structure but retains a lightly doped source/drain structure.

A process according to the present invention comprises the steps of:

defining a functional region and an ESD protective region on the silicon substrate and forming a field oxide layer therebetween;

forming a gate oxide layer on both the functional region and the ESD protective region;

forming a polysilicon layer on the gate oxide layer;

using a mask of predefined pattern to etch the polysilicon layer and the gate oxide layer so as to form a gate electrode and expose part of the silicon substrate,

ion implanting to the exposed part of the silicon substrate to form a lightly doped source/drain electrode;

forming an oxide layer on both the functional region and the ESD protective region;

coating a first photoresist layer on the oxide layer on the ESD protective region and then using an ESD mask for pattern definition so as to selectively remove part of the oxide layer on the functional region, thus forming an isolator on lateral side of the gate electrode in the functional region;

ion implanting using the gate electrode and the isolator in the functional region as a mask to form a heavily doped region to thereby form a lightly doped source/drain electrode,

removing the first photoresist layer on the oxide layer in the ESD protective region;

forming by sputtering deposition a metallization layer of titanium to thereby perform a rapid thermal annealing process and an etching process to form a self-aligning TiSi2 layer on the gate electrode and exposed surface of the source/drain electrode;

coating a second photoresist layer on the functional region and then using the ESD mask to selectively remove part of the oxide layer on the ESD protective region;

ion implanting using the electrode gate in the ESD protective region as mask to form heavily doped region, and

removing the second photoresist layer on the functional region.

Another process provided by the present invention for fabricating an electrostatic discharge (ESD) protective device on a silicon substrate, comprises the steps of:

defining a functional region and an ESD protective region on the silicon substrate and forming a field oxide layer therebetween;

forming a gate electrode on the silicon substrate and exposing surfaces of the silicon substrate where the functional region and a source/drain electrode in the silicon substrate are to be formed, then performing an ion implantation process to the exposed surfaces so as to form a lightly doped region;

forming an oxide layer on both the functional region and the ESD protective region;

coating a first photoresist layer on the oxide layer on the ESD protective region and then using an ESD mask for pattern definition so as to form a lightly doped source/drain electrode on the functional region, then removing the first photoresist layer on the oxide layer in the ESD protective region;

performing a self-aligning silicide process to apply a layer of metal on the lightly doped source/drain electrode in the functional region so as to form self-aligning metal silicide layers respectively on the gate electrode and the exposed surfaces of the drain/source electrode;

coating a second photoresist layer on the functional region and then using the ESD mask to selectively remove part of the oxide layer on the ESD protective region; and

ion implanting using the electrode gate in the ESD protective region as mask to form heavily doped region, then removing the second photoresist layer on the functional region.

BRIEF DESCRIPTION OF DRAWINGS

The present invention can be more fully understood by reading the subsequent detailed description of the preferred embodiments thereof with references made to the accompanying drawings, wherein:

FIGS. 1A-1C (Prior Art) are sectional views showing the steps involved in a conventional process for fabricating an ESD protective device; and

FIGS. 2A-2E are schematic sectional diagrams depicting the steps of a process according to the present invention for fabricating an ESD protective device.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

FIGS. 2A-2E, are sectional views of a semiconductor device showing various stages of a fabrication process according to the present invention for fabricating an ESD protective device. In each of these diagrams, the left half part shows the structure for the semiconductor device (hereinafter referred to as "functional region") intended to be protected by the ESD protective device according to the present invention, and the right half part shows the structure for the ESD protective device according to the present invention (hereinafter referred to as "ESD protective region").

Referring to FIG. 2A, a silicon substrate 30 is prepared and on which a gate electrode 34 is formed. Ions are then implanted to form lightly doped source/drain regions 40, 42.

On the silicon substrate 30, field oxide 31 is used separate the functional region from the ESD protective region. Next, oxidation is performed to form gate oxide layer 32 on the silicon substrate 30. Subsequently, a first polysilicon layer 34 with a thickness of between 800 Å to 1500 Å is deposited on the gate oxide layer 32. A mask is then used to define photoresist pattern to etch the first polysilicon layer 34 and the gate oxide layer 32 so as to expose part of the silicon substrate where the source/drain regions 40, 42 in the functional region and the ESD protective region are located. After the photoresist is removed, the structure is as that shown in FIG. 2A, in which the first polysilicon layer 34 that serves as gate electrode has a length of 1.2-1.5 μm.

Subsequently, ions are implanted using a source of first type impurities such as N-type phosphor ions with an energy of 50 KeV and a concentration of 3×1013 atoms/cm2, whereby lightly doped source/drain regions 40, 42 are formed.

Referring to FIG. 2B, in the next step an oxidation process is performed, in which the low-pressure chemical-vapor deposition (LPCVD) method is used to deposit a layer of silicon dioxide 36 to a thickness of 1000-3000 Å.

Referring next to FIGS. 2C and 2D, there are shown steps to construct the functional region. As shown in FIG. 2C, a first photoresist layer 50 is coated on the oxide layer 36 in the ESD protective region. Next, a mask for pattern definition on the ESD protective region is used and etching is performed to remove the oxide layer 36 in the functional region. An isolator 38, which can be silicon dioxide, is formed on the lateral side of the gate electrode in the functional region. N-type ions such as arsenic ions are implanted with an energy of 50-100 KeV and a concentration of 1×1015 to 1×1016 atoms/cm2, whereby a heavily doped N+ -type region is formed. This allows the functional region to be formed with a lightly doped drain (LDD) structure.

Referring to FIG. 2D, subsequently a self-aligning silicide process is carried out in which sputtering deposition is used to deposit a layer of metal as titanium, cobalt, or platinum. In preferred embodiment, a layer of titanium is deposited on the functional region to a thickness of 300 Å to 800 Å. Next, a rapid thermal annealing process is performed at a temperature of 600° C. to 700° C. In this process, N2 or NH3 is used so as to allow the partly deposited titanium film to react with the silicon on the source/drain electrode and the polysilicon on the gate electrode, thereby forming a layer of TiSi2 45. The remaining titanium which was not involved in the reaction and other remnants can be selectively removed by wet etching using, for instance, a solvent containing NH4 OH/H2 O2 /H2 O with a ratio 1:1:5-10. Finally, the rapid thermal annealing process is performed again at a temperature of 800° C. to 900° C. The self-aligning silicide structure is thus formed.

Referring to FIG. 2E, there is shown the step to construct the ESD protective region. A second photoresist layer 52 is coated on the functional region for ESD pattern definition of the ESD protective region. Then the oxide layer (silicon dioxide) 36 is removed by etching. N-type ions such as arsenic ions are implanted with an energy of 50 KeV to 100 KeV and a concentration of 1×1015 to 1×1016 atoms/cm2, into the ESD protective region. The photoresist layer 52 is then removed by using suitable solvents.

Since in the steps shown in FIG. 2C to FIG. 2E, the same ESD photoresist layer is used, the first photoresist layer 50 and the second photoresist layer 52 are made complementary in optical characteristics, i.e., one is positive photoresist and the other negative photoresist.

It is an important aspect of the present invention that the functional region is formed with the LDD and self-aligning silicide structure and the ESD protective device according to the present invention is formed as the ESD protective region in the right part of the semiconductor device shown in FIG. 2E. Moreover, the heavily doped N+ -type region 42 in the source/drain electrode includes the originally formed lightly doped N- -type region. As a result, the ESD protective effect is much more improved. The semiconductor device made with the protective device according to the present invention shown in FIG. 2E has the conventional heavily doped N+ -type region 42 so as to enhance the ESD capability. Since the protective device according to the present invention (the aforementioned ESD protective region) is included along with the functional structure (the aforementioned functional region) in the semiconductor device intended to be protected by the protective device according to the present invention, only one mask is needed in the fabriess. Thus, fabrication cost is significantly reduced.

The present invention has been described hitherto with exemplary preferred embodiments directed to the utilization of N-type source/drain electrode. However, it is to be understood that the scope of the present invention need not be limited to the disclosed preferred embodiments. Materials, conductive characteristics, parameters, and conditions set for the processes are all subject to other modifications and still within the spirit and scope of the present invention. Therefore, the claims are intended to cover various modifications and similar arrangements. The scope of the claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (17)

What is claimed is:
1. A process for fabricating an electrostatic discharge (ESD) protective device on a silicon substrate, comprising the steps of:
(1) defining a functional region and an ESD protective region on the silicon substrate and forming a field oxide layer therebetween;
(2) forming a gate oxide layer on both the functional region and the ESD protective region;
(3) forming a polysilicon layer on the gate oxide layer;
(4) forming, using a mask of predefined pattern to etch the polysilicon layer and the gate oxide layer, a gate electrode and exposing part of the silicon substrate, then performing an ion implantation process to the exposed part of the silicon substrate to form a lightly doped source/drain electrode;
(5) forming an oxide layer on both the functional region and the ESD protective region;
(6) coating a first photoresist layer on the oxide layer on the ESD protective region and then using an ESD mask for pattern definition so as to selectively remove part of the oxide layer on the functional region, thus forming an isolator on lateral side of the gate electrode in the functional region;
(7) ion implanting using the gate electrode and the isolator in the functional region as a mask to form a heavily doped region to thereby form a lightly doped source/drain electrode, then removing the first photoresist layer on the oxide layer in the ESD protective region;
(8) forming by sputtering deposition a metallization layer of titanium to thereby perform a rapid thermal annealing process and an etching process to form a self-aligning TiSi2 layer on the gate electrode and exposed surface of the source/drain electrode;
(9) coating a second photoresist layer on the functional region and then using the ESD mask to selectively remove part of the oxide layer on the ESD protective region; and
(10) ion implanting using the gate electrode in the ESD protective region as mask to form heavily doped region, then removing the second photoresist layer on the functional region.
2. A process as claimed in claim 1, wherein in Step (3) the polysilicon layer on the gate dioxide layer has a thickness of between 800 Å to 1500 Å.
3. A process as claimed in claim 1, wherein in Step (4) the polysilicon layer serving as gate electrode has a length of 1.2 μm to 1.5 μm.
4. A process as claimed in claim 1, wherein in Step (4) the ion implantation process uses a source of N-type phosphor ions with an energy of about 50 KeV and a concentration of about 3×1013 atoms/cm2.
5. A process as claimed in claim 1, wherein in Step (5) the oxide layer is formed through a low-pressure chemical-vapor deposition (LPCVD) method to a thickness of 1000 Å to 3000 Å.
6. A process as claimed in claim 1, wherein in Step (7) the ion implantation process uses a source of N-type arsenic ions with an energy of 50 KeV to 100 KeV and a concentration of 1×1015 to 1×1016 atoms/cm2.
7. A process as claimed in claim 1, wherein in Step (8) the sputtering deposition process deposits the titanium layer to a thickness of 300 Å to 800 Å.
8. A process as claimed in claim 1, wherein in Step (8) the etching process is a wet etching process using a solvent containing NH4 OH/H2 O2 /H2 O with a ratio 1:1:5-10.
9. A process as claimed in claim 1, wherein in Step (9) the heavily doped region in the ESD protective region includes originally formed lightly doped region.
10. A process for fabricating an electrostatic discharge (ESD) protective device on a silicon substrate, comprising the following steps of:
(1) defining a functional region and an ESD protective region on the silicon substrate and forming a field oxide layer therebetween;
(2) forming a gate electrode on the silicon substrate and exposing surfaces of the silicon substrate where the functional region and a source/drain electrode in the silicon substrate are to be formed, then performing an ion implantation process to the exposed surfaces so as to form a lightly doped region;
(3) forming an oxide layer on both the functional region and the ESD protective region;
(4) coating a first photoresist layer on the oxide layer on the ESD protective region and then using an ESD mask for pattern definition so as to form a lightly doped source/drain electrode on the functional region, then removing the first photoresist layer on the oxide layer in the ESD protective region;
(5) performing a self-aligning silicide process to apply a layer of metal on the lightly doped source/drain electrode in the functional region so as to form self-aligning metal silicide layers respectively on the gate electrode and the exposed surfaces of the drain/source electrode;
(6) coating a second photoresist layer on the functional region and then using the ESD mask to selectively remove part of the oxide layer on the ESD protective region; and
(7) ion implanting using the gate electrode in the ESD protective region as mask to form heavily doped region, then removing the second photoresist layer on the functional region.
11. A process as claimed in claim 10, wherein in Step (2) the ion implantation process uses a source of N-type phosphor ions with an energy of about 50 KeV and a concentration of 3×1013 atoms/cm2.
12. A process as claimed in claim 10, wherein in Step (3) the oxide layer is formed through a low-pressure chemical-vapor deposition (LPCVD) method to a thickness of 1000 Å to 3000 Å.
13. A process as claimed in claim 10, wherein in Step (5) the metal is selected from the group consisting of titanium, cobalt, and platinum.
14. A process as claimed in claim 10, wherein in Step (7) the ion implantation process uses a source of N-type arsenic ions with an energy of about 50 KeV and a concentration of 1×1015 and 1×1016 atoms/cm2.
15. A process as claimed in claim 10, wherein the heavily doped region in the ESD protective region includes originally formed lightly doped region.
16. A process as claimed in claims 1 through 15, wherein the first photoresist layer and the second photoresist layer are complementary in optical characteristics.
17. A process as claimed in claim 16, wherein the first photoresist layer is positive photoresist and the second photoresist layer is negative.
US08617600 1996-03-19 1996-03-19 Process for fabricating a semiconductor electrostatic discharge (ESD) protective device Expired - Fee Related US5585299A (en)

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Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5650341A (en) * 1996-10-03 1997-07-22 Mosel Vitelic Inc. Process for fabricating CMOS Device
FR2767603A1 (en) * 1997-08-22 1999-02-26 Mitsubishi Electric Corp Method of manufacturing a semiconductor device on a semiconductor substrate
US5946573A (en) * 1997-01-24 1999-08-31 United Microelectronics Corp. Self-aligned silicide (salicide) process for electrostatic discharge (ESD) protection
US5960288A (en) * 1997-08-12 1999-09-28 United Semiconductor Corp. Method of fabricating electrostatic discharge protection device
US5985722A (en) * 1996-08-26 1999-11-16 Nec Corporation Method of fabricating electrostatic discharge device
US5994176A (en) * 1998-02-19 1999-11-30 Texas Instruments - Acer Incorporated Method for forming self-aligned silicided MOS transistors with asymmetric ESD protecting transistors
US6020240A (en) * 1998-04-07 2000-02-01 Texas Instruments-Acer Incorporated Method to simultaneously fabricate the self-aligned silicided devices and ESD protection devices
US6022794A (en) * 1998-05-25 2000-02-08 United Microeletronics Corp. Method of manufacturing a buried contact in a static random access memory
US6037625A (en) * 1997-12-08 2000-03-14 Nec Corporation Semiconductor device with salicide structure and fabrication method thereof
US6100127A (en) * 1997-12-12 2000-08-08 Texas Instruments - Acer Incorporated Self-aligned silicided MOS transistor with a lightly doped drain ballast resistor for ESD protection
US6121090A (en) * 1998-04-20 2000-09-19 Texas Instruments - Acer Incorporated Self-aligned silicided MOS devices with an extended S/D junction and an ESD protection circuit
US6180462B1 (en) * 1999-06-07 2001-01-30 United Microelectronics Corp. Method of fabricating an analog integrated circuit with ESD protection
US6218226B1 (en) * 2000-01-21 2001-04-17 Vanguard International Semiconductor Corporation Method of forming an ESD protection device
US6359314B1 (en) * 1999-09-02 2002-03-19 Lsi Logic Corporation Swapped drain structures for electrostatic discharge protection
US6368922B1 (en) * 1996-04-02 2002-04-09 Winbond Electronics Corporation Internal ESD protection structure with contact diffusion
US6399431B1 (en) 2000-03-21 2002-06-04 Chartered Semiconductor Manufacturing Ltd. ESD protection device for SOI technology
US6429079B1 (en) 1997-10-22 2002-08-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US6444404B1 (en) 2000-08-09 2002-09-03 Taiwan Semiconductor Manufacturing Company Method of fabricating ESD protection device by using the same photolithographic mask for both the ESD implantation and the silicide blocking regions
US6514839B1 (en) 2001-10-05 2003-02-04 Taiwan Semiconductor Manufacturing Company ESD implantation method in deep-submicron CMOS technology for high-voltage-tolerant applications with light-doping concentrations
US6566717B2 (en) 2001-03-30 2003-05-20 Hynix Semiconductor Inc. Integrated circuit with silicided ESD protection transistors
US20050048724A1 (en) * 2003-09-01 2005-03-03 Jung-Cheng Kao Deep submicron manufacturing method for electrostatic discharge protection devices
US20050214654A1 (en) * 2004-03-26 2005-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. ESD-resistant photomask and method of preventing mask ESD damage
US20070141772A1 (en) * 2002-05-14 2007-06-21 Sony Corporation Semiconductor device, its manufacturing method and electronic apparatus thereof
US20070236843A1 (en) * 2005-07-26 2007-10-11 Demirlioglu Esin K Floating gate structure with high electrostatic discharge performance
US20120258576A1 (en) * 2011-04-05 2012-10-11 Renesas Electronics Corporation Manufacturing method of semiconductor device
US9431550B2 (en) 2005-12-28 2016-08-30 Vishay-Siliconix Trench polysilicon diode

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4345366A (en) * 1980-10-20 1982-08-24 Ncr Corporation Self-aligned all-n+ polysilicon CMOS process
US4528744A (en) * 1982-04-08 1985-07-16 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a semiconductor device
US4753898A (en) * 1987-07-09 1988-06-28 Motorola, Inc. LDD CMOS process
US4891326A (en) * 1984-05-16 1990-01-02 Hitachi, Ltd. Semiconductor device and a process for manufacturing the same
US5023190A (en) * 1990-08-03 1991-06-11 Micron Technology, Inc. CMOS processes
US5141890A (en) * 1982-02-01 1992-08-25 Texas Instruments Incorporated CMOS sidewall oxide-lightly doped drain process
US5166087A (en) * 1991-01-16 1992-11-24 Sharp Kabushiki Kaisha Method of fabricating semiconductor element having lightly doped drain (ldd) without using sidewalls
US5246872A (en) * 1991-01-30 1993-09-21 National Semiconductor Corporation Electrostatic discharge protection device and a method for simultaneously forming MOS devices with both lightly doped and non lightly doped source and drain regions
US5399513A (en) * 1989-06-27 1995-03-21 National Semiconductor Corporation Salicide compatible CMOS process with a differential oxide implant mask
US5516717A (en) * 1995-04-19 1996-05-14 United Microelectronics Corporation Method for manufacturing electrostatic discharge devices

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4345366A (en) * 1980-10-20 1982-08-24 Ncr Corporation Self-aligned all-n+ polysilicon CMOS process
US5141890A (en) * 1982-02-01 1992-08-25 Texas Instruments Incorporated CMOS sidewall oxide-lightly doped drain process
US4528744A (en) * 1982-04-08 1985-07-16 Tokyo Shibaura Denki Kabushiki Kaisha Method of manufacturing a semiconductor device
US4891326A (en) * 1984-05-16 1990-01-02 Hitachi, Ltd. Semiconductor device and a process for manufacturing the same
US4753898A (en) * 1987-07-09 1988-06-28 Motorola, Inc. LDD CMOS process
US5399513A (en) * 1989-06-27 1995-03-21 National Semiconductor Corporation Salicide compatible CMOS process with a differential oxide implant mask
US5023190A (en) * 1990-08-03 1991-06-11 Micron Technology, Inc. CMOS processes
US5166087A (en) * 1991-01-16 1992-11-24 Sharp Kabushiki Kaisha Method of fabricating semiconductor element having lightly doped drain (ldd) without using sidewalls
US5246872A (en) * 1991-01-30 1993-09-21 National Semiconductor Corporation Electrostatic discharge protection device and a method for simultaneously forming MOS devices with both lightly doped and non lightly doped source and drain regions
US5516717A (en) * 1995-04-19 1996-05-14 United Microelectronics Corporation Method for manufacturing electrostatic discharge devices

Cited By (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6368922B1 (en) * 1996-04-02 2002-04-09 Winbond Electronics Corporation Internal ESD protection structure with contact diffusion
US5985722A (en) * 1996-08-26 1999-11-16 Nec Corporation Method of fabricating electrostatic discharge device
US5650341A (en) * 1996-10-03 1997-07-22 Mosel Vitelic Inc. Process for fabricating CMOS Device
US5946573A (en) * 1997-01-24 1999-08-31 United Microelectronics Corp. Self-aligned silicide (salicide) process for electrostatic discharge (ESD) protection
US5960288A (en) * 1997-08-12 1999-09-28 United Semiconductor Corp. Method of fabricating electrostatic discharge protection device
US6008077A (en) * 1997-08-22 1999-12-28 Mitsubishi Denki Kabushiki Kaisha Method for fabricating semiconductor device
FR2767603A1 (en) * 1997-08-22 1999-02-26 Mitsubishi Electric Corp Method of manufacturing a semiconductor device on a semiconductor substrate
DE19819438C2 (en) * 1997-08-22 2002-01-24 Mitsubishi Electric Corp A method of manufacturing a semiconductor device having a silicide protective layer
US6429079B1 (en) 1997-10-22 2002-08-06 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
US6037625A (en) * 1997-12-08 2000-03-14 Nec Corporation Semiconductor device with salicide structure and fabrication method thereof
US6100127A (en) * 1997-12-12 2000-08-08 Texas Instruments - Acer Incorporated Self-aligned silicided MOS transistor with a lightly doped drain ballast resistor for ESD protection
US5994176A (en) * 1998-02-19 1999-11-30 Texas Instruments - Acer Incorporated Method for forming self-aligned silicided MOS transistors with asymmetric ESD protecting transistors
US6020240A (en) * 1998-04-07 2000-02-01 Texas Instruments-Acer Incorporated Method to simultaneously fabricate the self-aligned silicided devices and ESD protection devices
US6121090A (en) * 1998-04-20 2000-09-19 Texas Instruments - Acer Incorporated Self-aligned silicided MOS devices with an extended S/D junction and an ESD protection circuit
US6022794A (en) * 1998-05-25 2000-02-08 United Microeletronics Corp. Method of manufacturing a buried contact in a static random access memory
US6180462B1 (en) * 1999-06-07 2001-01-30 United Microelectronics Corp. Method of fabricating an analog integrated circuit with ESD protection
US6359314B1 (en) * 1999-09-02 2002-03-19 Lsi Logic Corporation Swapped drain structures for electrostatic discharge protection
US6587322B2 (en) 1999-09-02 2003-07-01 Lsi Logic Corporation Swapped drain structures for electrostatic discharge protection
US6218226B1 (en) * 2000-01-21 2001-04-17 Vanguard International Semiconductor Corporation Method of forming an ESD protection device
US6399431B1 (en) 2000-03-21 2002-06-04 Chartered Semiconductor Manufacturing Ltd. ESD protection device for SOI technology
US6444404B1 (en) 2000-08-09 2002-09-03 Taiwan Semiconductor Manufacturing Company Method of fabricating ESD protection device by using the same photolithographic mask for both the ESD implantation and the silicide blocking regions
US6566717B2 (en) 2001-03-30 2003-05-20 Hynix Semiconductor Inc. Integrated circuit with silicided ESD protection transistors
US6514839B1 (en) 2001-10-05 2003-02-04 Taiwan Semiconductor Manufacturing Company ESD implantation method in deep-submicron CMOS technology for high-voltage-tolerant applications with light-doping concentrations
US20030089951A1 (en) * 2001-10-05 2003-05-15 Taiwan Semiconductor Manufacturing Company ESD implantation in deep-submicron CMOS technology for high-voltage-tolerant applications
US6838734B2 (en) * 2001-10-05 2005-01-04 Taiwan Semiconductor Manufacturing Co., Ltd. ESD implantation in deep-submicron CMOS technology for high-voltage-tolerant applications
US20070141772A1 (en) * 2002-05-14 2007-06-21 Sony Corporation Semiconductor device, its manufacturing method and electronic apparatus thereof
US9748289B2 (en) * 2002-05-14 2017-08-29 Sony Semiconductor Solutions Corporation Semiconductor device, its manufacturing method and electronic apparatus thereof
US20050048724A1 (en) * 2003-09-01 2005-03-03 Jung-Cheng Kao Deep submicron manufacturing method for electrostatic discharge protection devices
US20050214654A1 (en) * 2004-03-26 2005-09-29 Taiwan Semiconductor Manufacturing Co., Ltd. ESD-resistant photomask and method of preventing mask ESD damage
US7252911B2 (en) * 2004-03-26 2007-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. ESD-resistant photomask and method of preventing mask ESD damage
US20070236843A1 (en) * 2005-07-26 2007-10-11 Demirlioglu Esin K Floating gate structure with high electrostatic discharge performance
US9111754B2 (en) 2005-07-26 2015-08-18 Vishay-Siliconix Floating gate structure with high electrostatic discharge performance
US9431550B2 (en) 2005-12-28 2016-08-30 Vishay-Siliconix Trench polysilicon diode
US20120258576A1 (en) * 2011-04-05 2012-10-11 Renesas Electronics Corporation Manufacturing method of semiconductor device
US8569136B2 (en) * 2011-04-05 2013-10-29 Renesas Electronic Corporation Manufacturing method of semiconductor device

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