US5479033A - Complementary junction heterostructure field-effect transistor - Google Patents
Complementary junction heterostructure field-effect transistor Download PDFInfo
- Publication number
- US5479033A US5479033A US08/250,088 US25008894A US5479033A US 5479033 A US5479033 A US 5479033A US 25008894 A US25008894 A US 25008894A US 5479033 A US5479033 A US 5479033A
- Authority
- US
- United States
- Prior art keywords
- channel
- layer
- gate
- integrated circuit
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000005669 field effect Effects 0.000 title claims abstract description 28
- 230000000295 complement effect Effects 0.000 title description 2
- 239000004065 semiconductor Substances 0.000 claims abstract description 38
- 150000001875 compounds Chemical class 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 9
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical group [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 27
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 21
- 230000004888 barrier function Effects 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 16
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 5
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical group [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 15
- 238000005468 ion implantation Methods 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 11
- 238000011161 development Methods 0.000 abstract description 5
- 230000008569 process Effects 0.000 abstract description 5
- 239000007943 implant Substances 0.000 description 22
- 238000005516 engineering process Methods 0.000 description 20
- 230000008901 benefit Effects 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 230000037230 mobility Effects 0.000 description 13
- 238000013461 design Methods 0.000 description 12
- 238000013459 approach Methods 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000002513 implantation Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 238000001465 metallisation Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 238000000407 epitaxy Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 3
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 238000001534 heteroepitaxy Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000003877 atomic layer epitaxy Methods 0.000 description 2
- 230000001934 delay Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 2
- 229910021342 tungsten silicide Inorganic materials 0.000 description 2
- 229910017115 AlSb Inorganic materials 0.000 description 1
- 241000282836 Camelus dromedarius Species 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 229910003944 H3 PO4 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000370 acceptor Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- LVQULNGDVIKLPK-UHFFFAOYSA-N aluminium antimonide Chemical compound [Sb]#[Al] LVQULNGDVIKLPK-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000004047 hole gas Substances 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910001425 magnesium ion Inorganic materials 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/802—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors
Definitions
- the present invention relates to complimentary junction heterostructure field-effect transistors (C-JHFETs) formed from III-V compound semiconductors and to a method for their manufacture.
- C-JHFETs complimentary junction heterostructure field-effect transistors
- the present invention may also be applied to the formation of high-speed integrated circuits (ICs) comprising a plurality of C-JHFET devices.
- CMOS Complimentary metal-oxide semiconductor
- Si ECL silicon emitter-coupled logic
- CMOS complementary metal-oxide semiconductor
- GaAs and other III-V complimentary ICs have a potential advantage over silicon CMOS ICs; but this advantage can be improved significantly by the development of a high-mobility p-channel FET.
- a viable complimentary III-V IC technology is needed to allow the fabrication of n- and p-channel FETs on a single substrate in a straightforward manner.
- Such a complimentary III-V IC technology will result in an extremely low static power consumption; and it will allow the use of many circuit design tricks developed for silicon CMOS ICs that minimize the number of transistors required to obtain a given level of functionality.
- the realization of a high level of integration with a compound semiconductor IC technology can only be realized if the transistor gate and subthreshold currents are reduced to a sufficiently low level.
- the p-channel transconductance is limited by the bulk hole mobility, as in the case of a conventional p-channel JFET.
- the p-channel drive current is therefore about twenty times less and the gate turn-on voltage is lower than for a complimentary n-channel GaAs MESFET.
- C-HFET complimentary heterostructure FET
- C-HFETs are Schottky-gate FETs in which the conducting path is a two-dimensional hole (or electron) gas at the heterointerface between a highly doped wide-bandgap material (AlGaAs) and an undoped smaller-bandgap material (GaAs).
- AlGaAs highly doped wide-bandgap material
- GaAs undoped smaller-bandgap material
- the prior art p-channel HFETs show improved performance, particularly at low temperatures (77 K.); but the room-temperature (i.e. 300 K.) performance has been disappointing.
- the greatest limitation of present C-HFETs is excessively high leakage current at room temperature. A high leakage current increases the static power dissipation and reduces the number of devices that can be incorporated into an IC.
- the progress in the development of C-HFETs to date has been slow; and these devices have yet to meet acceptable design constraints with regard to threshold voltages and gate leakage currents.
- C-HFET termed a semiconductor-insulator-semiconductor FET (SISFET) or a heterostructure insulated gate FET (HIGFET) is potentially less sensitive to process variations than conventional C-HFETs because the transistor threshold is largely independent of the distance between the electrons and the gate.
- SIGFET semiconductor-insulator-semiconductor FET
- HIGFET heterostructure insulated gate FET
- C-HIGFET technology offers high performance p- and n-channel devices that use the same InGaAs channel for device design and fabrication simplicity.
- the use of a common epitaxy for both the p- and n-channel devices results in trade-offs and conflicting design and processing requirements.
- insulated-gate approaches also termed metal insulator semiconductor (MIS) devices
- MIS metal insulator semiconductor
- the present invention uses a complimentary JFET technology that uses a different epitaxial layer structure in the p- and n-channel transistors, thereby allowing each device to be independently optimized for high performance and ease of manufacture.
- U.S. Pat. No. 5,122,851 discloses a trench gate JFET transistor in silicon suitable for use in interfacing large numbers of photodetectors with associated circuitry as in an infrared array image detector.
- the gate in this invention is recessed in a trench formed in the substrate between a drain and source region.
- the trench is preferably of sufficiently depth to mitigate the generation of 1/f noise in the transistor.
- Devices of opposite conductivities may be combined in a complimentary manner on the same substrate.
- U.S. Pat. No. 5,010,025 discloses a method for forming the above trench-gate JFET device.
- the gates of the present invention are not recessed in a trench as in the above patents (although the entire n-channel transistor of the present invention is formed in a trench for reasons of ease of manufacture rather than to reduce 1/f noise).
- U.S. Pat. No. 4,117,587 discloses a negative resistance semiconductor device formed by interconnecting in series two complimentary JFETs with the gate of each device connected to the drain of the other device of the opposite conductivity type. The result is a two-terminal circuit device that exhibits a current-versus-voltage characteristic having a negative resistance region.
- the present invention comprises more than two terminals and does not show a negative resistance characteristic.
- U.S. Pat. No. 5,130,770 discloses a JFET formed by a silicon-on-insulator technology.
- the drain and source of the JFET are formed on a semiconducting island supported by an electrically insulating layer that is preferably SiO 2 .
- Semiconductor oxides are not used in the formation of compound semiconductor devices as in the present invention.
- U.S. Pat. No. 5,031,007 discloses complimentary FETs formed from a compound semiconductor strained-layer superlattice comprising a plurality of alternating layers of two different semiconductor materials, one forming quantum-well layers and the other forming barrier layers.
- the strained layer superlattice increases the hole mobility by splitting the degeneracy of the valence band over that of the material in bulk form.
- the p-channel transistor in the present invention uses at least one strained quantum-well layer to increase the hole mobility by splitting the valence band degeneracy; and no strained layers or quantum wells are present in the complimentary n-channel transistor in the present invention.
- U.S. Pat. No. 5,142,349 discloses a C-HFET device that attempts to solve a problem with conventional HFETs due to a mismatch in the p- and n-channel threshold voltage and operating characteristics.
- This invention uses multiple electrically isolated vertically aligned channels to form a plurality of vertically stacked FETs with the channel regions controlled by a single gate electrode.
- aluminum antimonide (A1Sb) and gallium antimonide (GaSb) am preferably used for the p-channel devices and indium arsenide (InAs) and AlSb or the complimentary n-channel devices.
- U.S. Pat. No. 5,243,206 discloses a heterostructure field-effect transistor structure having vertically stacked complimentary n- and p-channel devices.
- the n- and p-channel transistors share a common gate electrode with the n and p channels positioned parallel to each other and vertically spaced by a predetermined separator thickness.
- this vertically stacked design is intended to dramatically reduce the chip size of compound semiconductors and increase the device packing density, it does so at the expense of a more complicated epitaxy and an increased manufacturing difficulty.
- the n- and p-channel transistors are not capable of independent operation due to the common gate electrode.
- a positive voltage on the gate turns the n-channel transistor on while simultaneously turning the p-channel off. This mode of operation may be advantageous for certain applications; but it is more restrictive than one in which the n- and p-channel transistors are completely independent as in the present invention.
- U.S. Pat. No. 5,060,031 discloses a complimentary heterojunction field-effect transistor with an anisotype n + gate for p-channel devices.
- the heavily n-doped anisotype layer underneath the gate electrode forms a semiconductor junction that replaces or augments a Schottky-barrier junction for the purpose of increasing the p-channel turn-on voltage to nearly 1.7 volts.
- a common channel preferably InGaAs
- p-channel transistors is used for both n-channel and p-channel transistors.
- the use of a common epitaxy for both n- and p-channel transistors results in some layers that are common to both transistors, and limits the ability to independently optimize each transistor's characteristics.
- a primary concern in the design of compound semiconductor complimentary field-effect transistors is the structure of the channel region underneath the gate electrode since the channel region performance largely determines the overall performance of the transistor. This is especially true of p-channel transistors.
- C-JHFET complimentary junction heterostructure field-effect transistor
- Another advantage of the C-JHFET of the present invention is that once the design of the p-channel device is optimized, a complimentary n-channel device may be formed in a compatible manner.
- Another object of the present invention to provide a III-V integrated circuit wherein the p-channel transistor is optimized to provide current drive for a unit of device width and device size approaching that of an n-channel device.
- Another object of the invention is to provide a III-V integrated circuit wherein bandgap engineering by means of heteroepitaxy improves the mobility of the p-channel transistor.
- An additional object of the invention is to provide a III-V integrated circuit wherein crystal lattice strain is used to split the degeneracy of the light and heavy hole bands to improve the transport in the light hole band.
- Still another object of the invention is to provide a III-V integrated circuit wherein the strained quantum-well layer is thermodynamically stable and compatible with high temperature processing requirements.
- Another object of the invention is to form an n-channel FET by ion implantation and a complimentary p-channel FET by heteroepitaxy, to obtain a high level of performance in both devices.
- Still another object of the invention is to form a p-channel FET with enhanced mobility, and to form a complimentary n-channel FET by a compatible process.
- a pair of complimentary junction heterostructure field-effect transistors is provided on a common III-V semiconductor substrate, and a method for their manufacture is described.
- FIG. 1 is a cross-sectional view of an integrated circuit 10 comprising a complimentary n- and p-channel junction heterostructure field transistors according to the present invention.
- FIGS. 2-10 are cross-sectional views illustrating the construction of an integrated circuit 10 of complmentary n- and p-channel junction heterostructure field-effect transistors according to the present invention.
- FIG. 11 shows the drain-to-source current-versus-voltage characteristics for a self-aligned 0.8 ⁇ 50 micron gate n-channel junction heterostructure field-effect transistor 16 as a function of the gate-to-drain voltage at 300 K.
- FIG. 12 shows the 300 K. behavior of the drain-to-source current and the transconductance as functions of the gate-to-source voltage for the device of FIG. 11.
- FIG. 13 shows the drain-to-source current-versus-voltage characteristics for a self-aligned 1.0 ⁇ 50 micron gate p-channel junction heterostructure field-effect transistor 16 as a function of the gate-to-drain voltage at 300 K.
- FIG. 14 shows the 300 K. behavior of the drain-to-source current and the transductance as, functions of the gate-to-source voltage for the device of FIG. 13.
- FIG. 15 shows an embodiment of the present invention in which an inverter circuit 60 is formed from the complimentary n- and p-channel junction heterostructure field-effect transistors.
- FIG. 16 shows the voltage transfer curves of the inverter circuit of FIG. 15.
- FIG. 17 shows frequency response curves illustrating the maximum frequency of oscillation as a function of power dissipation for a 0.9 ⁇ 100 micron gate n-channel junction heterostructure field-effect transistor 14 according to the present invention.
- the thickness of the semiconductor substrate is chosen on the basis of convenience for manufacture, and is not significant in the operation of the transistors other than as a thermal heat sink and mechanical support.
- the size of the transistors is determined by the semiconductor processing capabilities and the required operating characteristics.
- FIG. 1 illustrates a highly simplified cross-section through channel regions above a complimentary junction field-effect transistor integrated circuit in accordance with the present invention.
- All material layers in FIG. 1 are substantially single crystal epitaxially grown layers. This requires that each epitaxial layer comprise a material that is crystallographically compatible with an underlying substrate.
- the epitaxial layers of the present invention may be grew by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), atomic layer epitaxy (ALE), or the like.
- the integrated circuit 10 of the present invention shown schematically in FIG. 1, comprises: a semiconductor substrate 12, at least one n-channel junction heterostructure field-effect transistor (JHFET) 14 formed on the substrate, at least one p-channel JHFET 16 formed on the substrate, and at least one isolation region 18.
- JHFET junction heterostructure field-effect transistor
- the substrate 12 is a III-V compound semiconductor, preferably semi-insulating gallium arsenide (GaAs). Since the limiting factor in forming a complimentary compound semiconductor IC 10 is the performance of the p-channel transistor 16, a series of epitaxial layers are grown on the substrate for use in the formation of a high-performance p-channel transistor. The n-channel transistor 14 is then made in a manner that is compatible with and that does not degrade the performance of the p-channel transistor 16.
- GaAs gallium arsenide
- a strained quantum-well channel represents the best known method for improving the transport of the p-channel transistor 16. This is especially so because modulation doping has not been widely studied for p-channel field-effect transistors; and it may be difficult to obtain the optimum charge modulation required for a successful p-channel MODFET.
- FIGS. 2-10 A process sequence for forming the complimentary n- and p-channel JHFET transistors of the present invention is described with reference to FIGS. 2-10.
- a device region is formed by growing a plurality of epitaxial layers on the substrate as shown in FIG. 2, beginning with a buffer layer 20.
- the buffer layer 20 may be, for example, a semi-insulating (i.e. not intentionally doped) GaAs layer about 1 micron thick.
- the buffer layer 20 preferably includes a leakage barrier 22 to reduce carrier leakage from the p-channel transistor.
- the leakage barrier 22 may be in the form of a semiconductor p-n junction, or it may be a higher-bandgap material.
- a p-n junction leakage barrier 22 may be formed, for example, by growing about 75 nm of n-doped (about 5 ⁇ 10 17 cm -3 Si) GaAs upon the semi-insulating GaAs, followed by the growth of about 15 nm of p-doped (about 1.5 ⁇ 10 18 cm -3 Be) GaAs and about 10 nm of semi-insulating GaAs.
- a p-n junction leakage barrier 22 may also be used in forming the gate and channel regions of the n-channel transistor 14.
- the leakage barrier 22 may also be designed to improve the modulation doping efficiency by doping the strained quantum-well channel 24 from both the front (i.e. top) and back (i.e. bottom) sides.
- a higher-bandgap leakage barrier 22 may be formed, for example, by growing a layer of a material having an energy bandgap higher than that of the strained quantum-well channel 24.
- the higher-bandgap leakage barrier 22 may also become a part of the n-channel transistor to improve the p-n junction forward turn-on voltage.
- the leakage barrier 22 may be designed as a fully depleted n + layer to form a junction camel diode.
- the leakage barrier 22 may be doped to form a modulation-doping layer to provide backside modulation doping of the channel, thereby allowing the use of a smaller gate to channel spacing and increasing the maximum transistor drain-to-source current that may be controlled.
- At least one strained quantum-well layer 24 is epitaxially grown above the leakage barrier 22 in FIG. 2.
- the strained quantum-well layer used in forming the first conducting channel 24 is preferably indium gallium arsenide.
- the thickness and indium content of the strained quantum-well layer 24 are chosen to provide sufficient crystal lattice strain to split the degeneracy of the valence band to enhance the transport characteristics of the p-channel transistor 16; but of a value low enough to be thermally stable at the high temperatures (about 800° C. for about 15 seconds) used for rapid thermal annealing to activate the ion implants; or of a value low enough for the strain to be compensated by an overlying strain-compensation layer.
- the strained quantum-well layer 24 may be undoped with an indium composition of about 15% and a thickness of about 10 nm.
- the strained quantum-well layer 24 forms the first conducting channel 24 of the p-channel transistor 16 in FIG. 1.
- Al x Ga 1-x As aluminum gallium arsenide
- a portion of the higher-bandgap layer 26 grown in direct contact with the strained quantum-well layer 24 may be semi-insulating (for example, the first 5 nm) to better separate the ionized acceptors from the holes in the channel.
- the thickness of the semi-insulating portion of the higher-bandgap layer 26 is chosen to efficiently modulate the first conducting channel 24.
- the higher-bandgap layer 26 may also include a strain compensation region (i.e. a layer of a material having strain characteristics in the opposite sense to that of the first channel 24) to balance the strain of the first conducting channel 24, and to allow the use of a higher local strain in the first conducting channel 24.
- a strain compensation region i.e. a layer of a material having strain characteristics in the opposite sense to that of the first channel 24
- An advantage of using a strain-compensation higher-bandgap layer 26 is that it allows the use of a thicker strained quantum-well channel (i.e. the first conducting channel 24) to satisfy the thermal stability requirements of high temperature IC processing.
- Other compound semiconductor p-channel FET designs in the prior art have either sacrificed performance or thermal stability; and none of the prior art p-channel FET designs have optimized both thermal stability and performance.
- the higher-bandgap layer 26 acts in combination with the first conducting channel 24 to generate a two-dimensional hole gas in the first channel to enhance the mobility of the p-channel JHFET 16.
- first gate layer 28 In FIG. 2, above the higher-bandgap layer 26 is grown a first gate layer 28.
- the first gate 28 forms the junction gate on the p-channel FET 16.
- the first gate layer 28 may be, for example, n-doped GaAs (allout 5 ⁇ 10 18 cm -3 Si) with a thickness of about 50 nm.
- At least one mesa region (i.e. a p-mesa) is formed on the substrate 12 to fabricate at least one p-channel transistor 16 after the epitaxial growth step in FIG. 2.
- This p-mesa etch step may be performed with conventional semiconductor processing.
- a patterned photoresist mask may be formed on the substrate 12, and material in the mask openings etched down to the buffer layer 20 (or to the leakage barrier 22 if suitably designed to provide a p-n junction for the n-channel JHFET) with a 1:4:45 solution of H 3 PO 4 :H 2 O 2 :H 2 O.
- the etched wells or trenches formed in this manner adjacent to the p-mesas may be designed so as to provide selected locations for the formation of the complimentary n-channel JHFETs 14 in the buffer layer 20.
- This single mask and etching step allows the production of both enhancement and depletion mode n-channel JHFETs 14 on the same IC 10 as the p-channel JHFETs 16.
- the n-channel JHFET 14 is preferably fabricated by ion implantation in the epitaxial buffer layer 20.
- the n-channel transistor is called a JHFET, it should be more properly termed a JFET when the region of the buffer layer 20 in which the n-channel transistor is formed does not include a semiconductor heterostructure.
- the ion implantation approach is an advantage of the present invention since it allows the full flexibility of the epitaxy to improve the p-channel device, which is the weak link in compound semiconductor materials.
- the fully ion implanted n-channel JHFET 14 preferably uses a junction gate in order to achieve a reasonably high gate turn-on voltage of about 1 volt.
- junction field-effect transistors are used in the n-channel JHFET of IC 10 since they represent a fully ion implanted approach that meets all of the circuit requirements of complimentary logic.
- the n-channel JHFET 14 is fully compatible with a thermally stable, high-performance p-JHFET device 16.
- FIG. 4 shows a first ion implantation step performed after the p-mesa etch step in FIG. 3.
- This first ion implantation step is used for the formation of at least one complimentary n-channel JHFET 14.
- This step proceeds with an initial n-channel implant and a subsequent lower-energy p + implant.
- the n-channel implanted ion is preferably Si at an energy of about 70 keV and a dosage of about 1.5 ⁇ 10 13 cm -2 .
- the subsequent p + implanted ion is preferably Zn at an energy of about 45 keV and a dosage of about 3 ⁇ 10 14 cm -2 .
- the p + implant forms the second gate 30 and the n + implant forms the second conducting channel 32 of the n-channel transistor 14.
- the n-channel JHFET may include other ion implantation steps as known to the art for compound semiconductors, including those used in prior-art MESFETs. These implantation steps may be used to improve the backside confinement, and may include, for example, a deep Mg ion implant at an energy of 210 keV and a dosage of about 1.5 ⁇ 10 12 cm -2 . These additional implantation steps may also include co-implantation of a group V material coincident with the profile of the shallow p + implant to reduce interdiffusion of the p + and n layers. This co-implantation may be, for example, P 2 co-implanted at 45 keV at a dosage of about 3 ⁇ 10 14 cm -2 .
- FIG. 5 shows an isolation step performed after the first ion implantation step in FIG. 4.
- This isolation step preferably performed by ion implantation, forms at least one isolation region 18 in the substrate 12 around a transistor to electrically isolate that transistor from adjacent transistors.
- the isolation step may be performed, for example, by ion implanting oxygen at 40 and 120 keV at a dosage of 1 ⁇ 10 14 cm -2 for each implant.
- Oxygen implantation is a well-known isolation technique used in compound semiconductors; it is thermally stable in the embodiments of the present invention at high temperatures; and it is capable of reducing the parasitic capacitances under the gate contacts outside the active areas.
- Oxygen implantation is used to isolate other regions of the IC 10 where desired.
- Oxygen implantation may also be performed at an earlier step with the same benefits in terms of reducing parasitic capacitances of the gate electrodes, or at a later step in the fabrication sequence in which case the parasitic capacitance under the gate electrodes is unchanged.
- FIG. 6 shows a refractory gate electrode formation and drain/source etch step performed after the isolation step in FIG. 5.
- the refractory gate electrode material is deposited (for example, by sputter deposition) over the substrate 12 and patterned by reactive ion etching (for example, in a plasma of SF 6 , CHF 3 , and O 2 ) to form the first gate electrode 34 on the p-channel transistor 16 and the second gate electrode 36 on the n-channel transistor 14.
- the gate electrode material may be, for example, tungsten or tungsten silicide.
- the electrode metal thickness is preferably about 300 nm for a tungsten gate electrode material, and about 400 nm for tungsten silicide.
- the electrical gates of the transistors are the p-n junctions with the refractory gate electrodes serving as a self-aligned etch and implant mask.
- a wet etch for example, a 5:1 solution of citric acid and 30% hydrogen peroxide
- the wet etching serves multiple purposes: it undercuts the gates 28 and 30 slightly to reduce the gate capacitance, it forms a T-shaped gate profile that spaces the p-n junction gate away from the source and drain implants, and it simplifies the formation of the heavily doped self-aligned source and drain regions.
- the gate length for both the n- and p-channel gates is about 1 micron.
- the drain and source regions of the n-channel transistor are formed by ion implantation as shown in FIG. 7.
- the second drain 38 and second source 40 of the n-channel transistor 14 are formed after protecting the p-channel transistor 16 with a patterned photoresist mask.
- This n + implant step may be performed for example by implanting Si at energies of 40 and 80 keV with a dosage of 2 ⁇ 10 13 cm -2 for each implant, and using the self-aligned second gate electrode 36 as an implant mask.
- the drain and source regions of the p-channel transistor are formed by ion implantation as shown in FIG. 8 and the implants annealed.
- This step forms the first drain 42 and the first source 44 of the p-channel transistor 16.
- the n-channel transistor 14 is protected by a patterned photoresist mask, and the selfaligned first gate electrode 34 is used as the implant mask for the drain and source regions.
- This p + implant step may be performed for example by implanting Zn at energies of 40 and 80 keV with a dosage of 1 ⁇ 10 14 cm -2 for each implant.
- the n + and p + implants are activated by rapid thermal annealing at about 800° C. for about 15 seconds. Separate implant activation steps may also be performed for n + and p + activation, respectively.
- the order of the n + and p + implants may be reversed from that outlined herein.
- the next step in fabricating the C-JHFET IC 10 is a p-ohmic deposition step to deposit ohmic contacts on the drain and source of the p-channel transistor 16 as shown in FIG. 9.
- the p-metallization is preferably Be/Au with a thickness of about 300 nm, with patterning by lift-off. After alloying the contact metallization at about 410° C. for about 15 seconds, this step forms the first drain electrode 46 and the first source electrode 48 to the p-channel transistor 16.
- the ohmic contacts to the n-channel transistor are similarly formed in FIG. 10 in an n-ohmic deposition step.
- This step deposits an n-type contact metallization consisting of, for example, Ge:Au:Ni:Au with layer thicknesses of 26 nm, 54 nm, 15 nm, and 200 nm, respectively.
- the n-metals am patterned by lift-off, and subsequently alloyed at about 370° C. for about 15 seconds.
- This step forms the second drain electrode 50 and the second source electrode 52 on the n-channel transistor 14.
- Interconnection of the completed n- and p-channel transistors to form logic gates is performed with a two level metallization.
- Ti/Pt/Au is preferably used as the electrical interconnection metal with silicon nitride used as the insulating material above the transistors and between the metallization levels.
- the complimentary JHFET transistors of the present invention are designed with low subthreshold currents; and the device threshold voltage, V th (defined herein as the gate-to-source voltage, V GS , at 5 mA/mm of drain current, I DS ), is designed to be sufficiently large so that the device in the off-state is biased well into the sub-threshold regime.
- the gate turn-on voltage, V to (defined herein as V GS at 1 mA/mm of gate current), is designed to be higher than the circuit power supply voltage. For compound semiconductors, this may be done by designing the C-JHFETs with a turn-on voltage that is substantially larger than the Schottky barrier height of about 0.5 /volts.
- junction gates are used to achieve high gate turn-on voltages of about -1.1 volts for the p-channel transistor 16 and about 1.0 volts for the n-channel transistor 14.
- the thickness of the conducting channel is controlled by the voltage on the gate electrode which fixes the depth of the depletion region under the gate.
- a positive voltage on the second gate electrode 36 enhances the second conducting channel 32 turning the n-channel JHFET 14 on.
- a negative voltage on the first gate electrode 34 enhances the first conducting channel 24 turning the p-channel JHFET 16 on. It should be understood that the threshold voltage of the devices as well as enhancement/depletion mode operation can be chosen by the designer to meet specific circuit needs.
- the threshold voltage, V th of the complimentary JHFETs in the IC 10 may be adjusted in manufacture to obtain symmetrical transistors by controlling the doping profile in the gate channel region by direct ion implantation for the n-channel JHFET 14, or by changing the doping, thickness, or composition of the epitaxial layers 22, 24, and 26 of the p-channel JHFET.
- FIGS. 11-14 show operating characteristics of complimentary JHFET enhancement-mode transistors in the IC 10 of the present invention.
- FIG. 11 shows the drain-to-source current-versus-voltage characteristics for a self-aligned 0.8 ⁇ 50 micron gate n-channel junction heterostructure field-effect transistor 14 as a function of the gate-to-drain voltage at room temperature (300 K.).
- HG. 12 shows the 300 K. behavior of the n-channel drain-to-source current and the transconductance as functions of the gate-to-source voltage for the device of FIG. 11.
- V to for the n-channel transistor is 1.0 volts.
- the n-channel transistor device-on/leakage current ratios i.e. the ratios of the on- to off-current flow and the on-current to the gate current in the transistor) are greater than or equal to 90.
- FIG. 13 shows the drain-to-source current-versus-voltage characteristics for a self-aligned 1.0 ⁇ 50 micron gate p-channel junction heterostructure field-effect transistor 16 as a function of the gate-to-drain voltage at 300 K.
- the IC 10 is preferably operated at a power supply voltages of about ⁇ 1.0 volt to about ⁇ 1.25 volts.
- FIG. 14 shows the 300 K. behavior of the p-channel drain-to-source current and the transconductance as functions of the gate-to-source voltage for the device of FIG. 13.
- the value of V to for this p-channel transistor is 1.1 volts.
- P-channel transistors fabricated according to the present invention can hold 1.15 volts on the gate with a gate leakage current of 1 microampere/micron; and n-channel JHFETs can hold 0.95 volts on the gate at the same gate leakage current.
- the gate leakage represents the largest dc power dissipation for the complimentary IC 10.
- the important parameters of FET characteristics for digital ICs are the transconductance and the maximum frequency of operation. To minimize the total propagation delay in an IC, the supply voltages should be reduced to the a minimum value, which ultimately depends on the noise margins and basic delays. High-speed operation at low supply voltages requires a high mobility in the channel to maintain a constant drift velocity.
- the self-aligned refractory gate process of the present invention avoids the excess gate capacitance associated with conventional JFETs.
- the junction gates 28 and 30 are made coincident with or slightly undercut from the refractory metal gate electrodes 34 and 36 in contrast to conventional JFETs which have both metal overhang capacitance and extension of the gate region beyond the edge of the gate metal electrode.
- the self-aligned n-channel JHFET 14 of the present invention shows no rf speed penalty over prior art MESFETs, but has the advantage of a higher gate turn-on voltage.
- FIG. 15 shows a dc inverter circuit 60 which is a specialized type of IC 10 that may be formed from the complimentary n- and p-channel junction heterostructure field-effect transistors of the present invention.
- the inverter circuit 60 comprises a p-channel JHFET 16 and an n-channel JHFET 14 that are directly connected together as shown in FIG. 15.
- a power supply connection 62 and a ground connection 64 are made to the transistor pair.
- the inverter input 66 is common to the two gate electrodes 34 and 36 that are connected together, and the inverter output 68 is taken from the common drain/source interconnection of the two JHFETs.
- An advantage of the use of the complementary technology of the present invention is that the inverter circuit 60 is simple, having only two direct-coupled transistors; and no level translation is required.
- FIG. 16 shows the operation of the inverter circuit 60 at power supply voltages of 1.0 and 1.25 volts. Noise margins of greater than 200 mV are obtained for the inverter with a power supply voltage of 1.0 volts.
- FIG. 17 shows frequency response curves illustrating the maximum frequency of oscillation for a 0.9 ⁇ 100 micron gate n-channel junction heterostructure field-effect transistor 14 as a function of the dissipated dc power.
- this JHFET operates at a maximum frequency of 20 GHz.
- the maximum frequency of oscillation may be increased to over 35 GHz.
- 31-stage ring oscillators loaded with a 200 micron interconnection wire between each stage may also be fabricated according to the present invention.
- These ring oscillators show gate delays as low as 179 picoseconds for a power supply voltage of 1.2 volts, and have a power-delay product of about 28 femtoJoules.
- Power-delay products as low as 8.9 femtoJoules am obtained at a speed of 320 picoseconds/stage and a power supply voltage of 0.8 volts.
- n- and p-channel JHFETs are basic building blocks that may be interconnected to provide any digital logic function using fewer devices and simpler circuitry than is possible with devices of a single FET type.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
Claims (12)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/250,088 US5479033A (en) | 1994-05-27 | 1994-05-27 | Complementary junction heterostructure field-effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/250,088 US5479033A (en) | 1994-05-27 | 1994-05-27 | Complementary junction heterostructure field-effect transistor |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/809,003 Continuation-In-Part US5306311A (en) | 1987-07-20 | 1991-12-17 | Prosthetic articular cartilage |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/457,971 Division US5735903A (en) | 1987-07-20 | 1995-06-01 | Meniscal augmentation device |
Publications (1)
Publication Number | Publication Date |
---|---|
US5479033A true US5479033A (en) | 1995-12-26 |
Family
ID=22946273
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/250,088 Expired - Lifetime US5479033A (en) | 1994-05-27 | 1994-05-27 | Complementary junction heterostructure field-effect transistor |
Country Status (1)
Country | Link |
---|---|
US (1) | US5479033A (en) |
Cited By (132)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5940695A (en) * | 1996-10-11 | 1999-08-17 | Trw Inc. | Gallium antimonide complementary HFET |
US5977560A (en) * | 1994-10-24 | 1999-11-02 | Micron Technology, Inc. | Thin film transistor constructions with polycrystalline silicon-germanium alloy doped with carbon in the channel region |
US6222234B1 (en) * | 1998-04-15 | 2001-04-24 | Nec Corporation | Semiconductor device having partially and fully depleted SOI elements on a common substrate |
WO2002009186A2 (en) * | 2000-07-24 | 2002-01-31 | Motorola, Inc. | Field effect transistor |
US20020017644A1 (en) * | 2000-05-26 | 2002-02-14 | Fitzgerald Eugene A. | Buried channel strained silicon FET using a supply layer created through ion implantation |
US6429103B1 (en) * | 2000-04-13 | 2002-08-06 | Motorola, Inc. | MOCVD-grown emode HIGFET buffer |
US20020197803A1 (en) * | 2001-06-21 | 2002-12-26 | Amberwave Systems Corporation | Enhancement of p-type metal-oxide-semiconductor field effect transistors |
WO2003007787A2 (en) | 2001-07-16 | 2003-01-30 | Depuy Products, Inc. | Cartilage repair and regeneration device and method |
WO2003007839A2 (en) | 2001-07-16 | 2003-01-30 | Depuy Products, Inc. | Devices form naturally occurring biologically derived |
US20030052334A1 (en) * | 2001-06-18 | 2003-03-20 | Lee Minjoo L. | Structure and method for a high-speed semiconductor device |
US20030057439A1 (en) * | 2001-08-09 | 2003-03-27 | Fitzgerald Eugene A. | Dual layer CMOS devices |
US6555946B1 (en) | 2000-07-24 | 2003-04-29 | Motorola, Inc. | Acoustic wave device and process for forming the same |
US6589856B2 (en) | 2001-08-06 | 2003-07-08 | Motorola, Inc. | Method and apparatus for controlling anti-phase domains in semiconductor structures and devices |
US6590236B1 (en) | 2000-07-24 | 2003-07-08 | Motorola, Inc. | Semiconductor structure for use with high-frequency signals |
US20030155592A1 (en) * | 2001-12-28 | 2003-08-21 | Masashi Shima | Semiconductor device and complementary semiconductor device |
US6638838B1 (en) | 2000-10-02 | 2003-10-28 | Motorola, Inc. | Semiconductor structure including a partially annealed layer and method of forming the same |
US6639249B2 (en) | 2001-08-06 | 2003-10-28 | Motorola, Inc. | Structure and method for fabrication for a solid-state lighting device |
US6646293B2 (en) | 2001-07-18 | 2003-11-11 | Motorola, Inc. | Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates |
US6649480B2 (en) | 2000-12-04 | 2003-11-18 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
US6667196B2 (en) | 2001-07-25 | 2003-12-23 | Motorola, Inc. | Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method |
US6673667B2 (en) | 2001-08-15 | 2004-01-06 | Motorola, Inc. | Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials |
US6673646B2 (en) | 2001-02-28 | 2004-01-06 | Motorola, Inc. | Growth of compound semiconductor structures on patterned oxide films and process for fabricating same |
US20040026765A1 (en) * | 2002-06-07 | 2004-02-12 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
US6693298B2 (en) | 2001-07-20 | 2004-02-17 | Motorola, Inc. | Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same |
US6693033B2 (en) | 2000-02-10 | 2004-02-17 | Motorola, Inc. | Method of removing an amorphous oxide from a monocrystalline surface |
US6703144B2 (en) | 2000-01-20 | 2004-03-09 | Amberwave Systems Corporation | Heterointegration of materials using deposition and bonding |
US6703688B1 (en) | 2001-03-02 | 2004-03-09 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6709989B2 (en) | 2001-06-21 | 2004-03-23 | Motorola, Inc. | Method for fabricating a semiconductor structure including a metal oxide interface with silicon |
US6713326B2 (en) | 2000-08-16 | 2004-03-30 | Masachusetts Institute Of Technology | Process for producing semiconductor article using graded epitaxial growth |
US6724008B2 (en) | 2001-03-02 | 2004-04-20 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6723661B2 (en) | 2001-03-02 | 2004-04-20 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US20040164318A1 (en) * | 2001-08-06 | 2004-08-26 | Massachusetts Institute Of Technology | Structures with planar strained layers |
US20040195623A1 (en) * | 2003-04-03 | 2004-10-07 | Chung-Hu Ge | Strained channel on insulator device |
US20040217444A1 (en) * | 2001-10-17 | 2004-11-04 | Motorola, Inc. | Method and apparatus utilizing monocrystalline insulator |
US6821829B1 (en) | 2000-06-12 | 2004-11-23 | Freescale Semiconductor, Inc. | Method of manufacturing a semiconductor component and semiconductor component thereof |
US20050035369A1 (en) * | 2003-08-15 | 2005-02-17 | Chun-Chieh Lin | Structure and method of forming integrated circuits utilizing strained channel transistors |
US20050035470A1 (en) * | 2003-08-12 | 2005-02-17 | Chih-Hsin Ko | Strained channel complementary field-effect transistors and methods of manufacture |
US20050035409A1 (en) * | 2003-08-15 | 2005-02-17 | Chih-Hsin Ko | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
US20050035410A1 (en) * | 2003-08-15 | 2005-02-17 | Yee-Chia Yeo | Semiconductor diode with reduced leakage |
US20050040493A1 (en) * | 2003-08-18 | 2005-02-24 | Yee-Chia Yeo | Resistor with reduced leakage |
US6864115B2 (en) | 2000-01-20 | 2005-03-08 | Amberwave Systems Corporation | Low threading dislocation density relaxed mismatched epilayers without high temperature growth |
US6876010B1 (en) | 1997-06-24 | 2005-04-05 | Massachusetts Institute Of Technology | Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization |
US20050156274A1 (en) * | 2003-04-25 | 2005-07-21 | Yee-Chia Yeo | Strained channel transistor and methods of manufacture |
US6933518B2 (en) | 2001-09-24 | 2005-08-23 | Amberwave Systems Corporation | RF circuits including transistors having strained material layers |
US20050186722A1 (en) * | 2004-02-25 | 2005-08-25 | Kuan-Lun Cheng | Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions |
US6940089B2 (en) | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
US20050208717A1 (en) * | 2003-07-25 | 2005-09-22 | Yee-Chia Yeo | Capacitor with enhanced performance and method of manufacture |
WO2005089411A2 (en) | 2004-03-17 | 2005-09-29 | Revivicor, Inc. | Tissue products from animals lacking functional alpha 1,3 galactosyl transferase |
US20050248906A1 (en) * | 2003-07-25 | 2005-11-10 | Yee-Chia Yeo | Capacitor that includes high permittivity capacitor dielectric |
US20050266632A1 (en) * | 2004-05-26 | 2005-12-01 | Yun-Hsiu Chen | Integrated circuit with strained and non-strained transistors, and method of forming thereof |
US6995430B2 (en) | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US7060632B2 (en) | 2002-03-14 | 2006-06-13 | Amberwave Systems Corporation | Methods for fabricating strained layers on semiconductor substrates |
US7074623B2 (en) | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
US7122449B2 (en) | 2002-06-10 | 2006-10-17 | Amberwave Systems Corporation | Methods of fabricating semiconductor structures having epitaxially grown source and drain elements |
US7160333B2 (en) | 2000-08-04 | 2007-01-09 | Depuy Orthopaedics, Inc. | Reinforced small intestinal submucosa |
US20070010078A1 (en) * | 2005-07-07 | 2007-01-11 | Micron Technology, Inc. | Methods of forming integrated circuitry and methods of forming local interconnects |
US7163563B2 (en) | 2001-07-16 | 2007-01-16 | Depuy Products, Inc. | Unitary surgical device and method |
US7201917B2 (en) | 2001-07-16 | 2007-04-10 | Depuy Products, Inc. | Porous delivery scaffold and method |
US20070090416A1 (en) * | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US7217603B2 (en) | 2002-06-25 | 2007-05-15 | Amberwave Systems Corporation | Methods of forming reacted conductive gate electrodes |
US7227176B2 (en) | 1998-04-10 | 2007-06-05 | Massachusetts Institute Of Technology | Etch stop layer system |
US20070138565A1 (en) * | 2005-12-15 | 2007-06-21 | Intel Corporation | Extreme high mobility CMOS logic |
WO2007076791A1 (en) * | 2005-12-12 | 2007-07-12 | Infineon Technologies Ag | Method for the production of a compound semiconductor field effect transistor comprising a fin structure, and compound semiconductor field effect transistor comprising a fin structure |
US7268024B2 (en) | 2003-04-30 | 2007-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
US7307273B2 (en) | 2002-06-07 | 2007-12-11 | Amberwave Systems Corporation | Control of strain in device layers by selective relaxation |
US20080032478A1 (en) * | 2006-08-02 | 2008-02-07 | Hudait Mantu K | Stacking fault and twin blocking barrier for integrating III-V on Si |
US7332417B2 (en) | 2003-01-27 | 2008-02-19 | Amberwave Systems Corporation | Semiconductor structures with structural homogeneity |
US7335545B2 (en) | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
US20080064174A1 (en) * | 2006-08-31 | 2008-03-13 | Stmicroelectronics S.A. | Method for manufacturing an integrated circuit with fully depleted and partially depleted transistors |
US7354627B2 (en) | 2004-12-22 | 2008-04-08 | Depuy Products, Inc. | Method for organizing the assembly of collagen fibers and compositions formed therefrom |
US7361195B2 (en) | 2001-07-16 | 2008-04-22 | Depuy Products, Inc. | Cartilage repair apparatus and method |
US7368308B2 (en) | 2002-08-23 | 2008-05-06 | Amberwave Systems Corporation | Methods of fabricating semiconductor heterostructures |
US7393733B2 (en) | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
US20080169512A1 (en) * | 2004-08-10 | 2008-07-17 | Doyle Brian S | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US7479421B2 (en) | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US7504704B2 (en) | 2003-03-07 | 2009-03-17 | Amberwave Systems Corporation | Shallow trench isolation process |
US7513866B2 (en) | 2004-10-29 | 2009-04-07 | Depuy Products, Inc. | Intestine processing device and associated method |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7569233B2 (en) | 2004-05-04 | 2009-08-04 | Depuy Products, Inc. | Hybrid biologic-synthetic bioabsorbable scaffolds |
US20090218632A1 (en) * | 2008-02-28 | 2009-09-03 | International Business Machines Corporation | Cmos structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication |
US7594967B2 (en) | 2002-08-30 | 2009-09-29 | Amberwave Systems Corporation | Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy |
US7595062B2 (en) | 2005-07-28 | 2009-09-29 | Depuy Products, Inc. | Joint resurfacing orthopaedic implant and associated method |
US20090243031A1 (en) * | 2008-03-26 | 2009-10-01 | International Business Machines Corporation | Structure and method to control oxidation in high-k gate structures |
US7615829B2 (en) | 2002-06-07 | 2009-11-10 | Amberwave Systems Corporation | Elevated source and drain elements for strained-channel heterojuntion field-effect transistors |
US20090283837A1 (en) * | 2008-05-13 | 2009-11-19 | Frank Huebinger | Semiconductor Devices and Methods of Manufacture Thereof |
US20100032773A1 (en) * | 2008-08-08 | 2010-02-11 | Mayank Shrivastava | Semiconductor Devices and Methods for Manufacturing a Semiconductor Device |
US7736956B2 (en) | 2005-08-17 | 2010-06-15 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US7776697B2 (en) | 2001-09-21 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
US7781771B2 (en) | 2004-03-31 | 2010-08-24 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US7808051B2 (en) | 2008-09-29 | 2010-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Standard cell without OD space effect in Y-direction |
US20100264425A1 (en) * | 2007-06-18 | 2010-10-21 | University Of Utah Research Foundation | Transistors for replacing metal-oxide-semiconductor field-effect transistors in nanoelectronics |
US7819918B2 (en) | 2001-07-16 | 2010-10-26 | Depuy Products, Inc. | Implantable tissue repair device |
US7867860B2 (en) | 2003-07-25 | 2011-01-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel transistor formation |
US7871440B2 (en) | 2006-12-11 | 2011-01-18 | Depuy Products, Inc. | Unitary surgical device and method |
US7879675B2 (en) | 2005-03-14 | 2011-02-01 | Intel Corporation | Field effect transistor with metal source/drain regions |
US20110024798A1 (en) * | 2009-08-03 | 2011-02-03 | Sony Corporation | Semiconductor device and method for manufacturing same |
US7888201B2 (en) | 2003-11-04 | 2011-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors |
US7898041B2 (en) | 2005-06-30 | 2011-03-01 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7914808B2 (en) | 2001-07-16 | 2011-03-29 | Depuy Products, Inc. | Hybrid biologic/synthetic porous extracellular matrix scaffolds |
US7943961B2 (en) | 2008-03-13 | 2011-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain bars in stressed layers of MOS devices |
US7989280B2 (en) | 2005-11-30 | 2011-08-02 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
US8025896B2 (en) | 2001-07-16 | 2011-09-27 | Depuy Products, Inc. | Porous extracellular matrix scaffold and method |
US20110260173A1 (en) * | 2010-04-16 | 2011-10-27 | Tsinghua University | Semiconductor structure |
US8053304B2 (en) * | 2009-02-24 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming high-mobility devices including epitaxially growing a semiconductor layer on a dislocation-blocking layer in a recess formed in a semiconductor substrate |
US8067818B2 (en) | 2004-10-25 | 2011-11-29 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US8084818B2 (en) | 2004-06-30 | 2011-12-27 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US8092529B2 (en) | 2001-07-16 | 2012-01-10 | Depuy Products, Inc. | Meniscus regeneration device |
JP2012094774A (en) * | 2010-10-28 | 2012-05-17 | Sony Corp | Semiconductor device |
US8183646B2 (en) | 2005-02-23 | 2012-05-22 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US20120223391A1 (en) * | 2011-03-04 | 2012-09-06 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing semiconductor device |
US8268709B2 (en) | 2004-09-29 | 2012-09-18 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8366787B2 (en) | 2000-08-04 | 2013-02-05 | Depuy Products, Inc. | Hybrid biologic-synthetic bioabsorbable scaffolds |
US8405164B2 (en) | 2003-06-27 | 2013-03-26 | Intel Corporation | Tri-gate transistor device with stress incorporation layer and method of fabrication |
US8558278B2 (en) | 2007-01-16 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained transistor with optimized drive current and method of forming |
US8680576B2 (en) * | 2012-05-16 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS device and method of forming the same |
US8748292B2 (en) | 2002-06-07 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming strained-semiconductor-on-insulator device structures |
US8822282B2 (en) | 2001-03-02 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of fabricating contact regions for FET incorporating SiGe |
US20140264380A1 (en) * | 2013-03-15 | 2014-09-18 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Complementary Field Effect Transistors Using Gallium Polar and Nitrogen Polar III-Nitride Material |
US20150044859A1 (en) * | 2013-08-07 | 2015-02-12 | International Business Machines Corporation | Compound semiconductor integrated circuit and method to fabricate same |
US9059288B2 (en) | 2013-06-21 | 2015-06-16 | International Business Machines Corporation | Overlapped III-V finfet with doped semiconductor extensions |
US9337307B2 (en) | 2005-06-15 | 2016-05-10 | Intel Corporation | Method for fabricating transistor with thinned channel |
US20160240671A1 (en) * | 2013-09-27 | 2016-08-18 | Intel Corporation | Transistor structure with variable clad/core dimension for stress and bandgap |
US20170005091A1 (en) * | 2015-06-30 | 2017-01-05 | Infineon Technologies Austria Ag | Semiconductor Devices and Method for Forming Semiconductor Devices |
US9768313B2 (en) * | 2015-10-05 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices having transition metal dichalcogenide layers with different thicknesses and methods of manufacture |
US20170271333A1 (en) * | 2012-05-16 | 2017-09-21 | Sony Corporation | Semiconductor device and manufacturing method of the same |
US10199477B2 (en) * | 2013-08-12 | 2019-02-05 | Nxp Usa, Inc. | Complementary gallium nitride integrated circuits |
US10381349B2 (en) | 2017-08-29 | 2019-08-13 | International Business Machines Corporation | Stacked complementary junction FETs for analog electronic circuits |
CN114035636A (en) * | 2021-11-12 | 2022-02-11 | 深圳飞骧科技股份有限公司 | Band gap reference starting circuit and radio frequency chip |
CN114265462A (en) * | 2021-12-15 | 2022-04-01 | 成都海光微电子技术有限公司 | Band gap reference, chip, electronic device and electronic equipment |
US11349023B2 (en) * | 2019-10-01 | 2022-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integration of p-channel and n-channel E-FET III-V devices without parasitic channels |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4117587A (en) * | 1973-11-30 | 1978-10-03 | Matsushita Electronics Corporation | Negative-resistance semiconductor device |
US4811075A (en) * | 1987-04-24 | 1989-03-07 | Power Integrations, Inc. | High voltage MOS transistors |
US5010025A (en) * | 1989-04-03 | 1991-04-23 | Grumman Aerospace Corporation | Method of making trench JFET integrated circuit elements |
US5031007A (en) * | 1985-12-23 | 1991-07-09 | Sandia Corporation | SLS complementary logic devices with increase carrier mobility |
US5060030A (en) * | 1990-07-18 | 1991-10-22 | Raytheon Company | Pseudomorphic HEMT having strained compensation layer |
US5060031A (en) * | 1990-09-18 | 1991-10-22 | Motorola, Inc | Complementary heterojunction field effect transistor with an anisotype N+ ga-channel devices |
US5122851A (en) * | 1989-04-03 | 1992-06-16 | Grumman Aerospace Corporation | Trench JFET integrated circuit elements |
US5130770A (en) * | 1990-06-19 | 1992-07-14 | Brevatome | Integrated circuit in silicon on insulator technology comprising a field effect transistor |
US5142349A (en) * | 1991-07-01 | 1992-08-25 | Motorola, Inc. | Self-doped high performance complementary heterojunction field effect transistor |
US5198879A (en) * | 1990-03-19 | 1993-03-30 | Fujitsu Limited | Heterojunction semiconductor device |
US5243206A (en) * | 1991-07-02 | 1993-09-07 | Motorola, Inc. | Logic circuit using vertically stacked heterojunction field effect transistors |
-
1994
- 1994-05-27 US US08/250,088 patent/US5479033A/en not_active Expired - Lifetime
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4117587A (en) * | 1973-11-30 | 1978-10-03 | Matsushita Electronics Corporation | Negative-resistance semiconductor device |
US5031007A (en) * | 1985-12-23 | 1991-07-09 | Sandia Corporation | SLS complementary logic devices with increase carrier mobility |
US4811075A (en) * | 1987-04-24 | 1989-03-07 | Power Integrations, Inc. | High voltage MOS transistors |
US5010025A (en) * | 1989-04-03 | 1991-04-23 | Grumman Aerospace Corporation | Method of making trench JFET integrated circuit elements |
US5122851A (en) * | 1989-04-03 | 1992-06-16 | Grumman Aerospace Corporation | Trench JFET integrated circuit elements |
US5198879A (en) * | 1990-03-19 | 1993-03-30 | Fujitsu Limited | Heterojunction semiconductor device |
US5130770A (en) * | 1990-06-19 | 1992-07-14 | Brevatome | Integrated circuit in silicon on insulator technology comprising a field effect transistor |
US5060030A (en) * | 1990-07-18 | 1991-10-22 | Raytheon Company | Pseudomorphic HEMT having strained compensation layer |
US5060031A (en) * | 1990-09-18 | 1991-10-22 | Motorola, Inc | Complementary heterojunction field effect transistor with an anisotype N+ ga-channel devices |
US5142349A (en) * | 1991-07-01 | 1992-08-25 | Motorola, Inc. | Self-doped high performance complementary heterojunction field effect transistor |
US5243206A (en) * | 1991-07-02 | 1993-09-07 | Motorola, Inc. | Logic circuit using vertically stacked heterojunction field effect transistors |
Non-Patent Citations (30)
Title |
---|
A. G. Baca et al., "Complimentary GaAs Junction-Gated Heterostructure Field Effect Transistor Technology," to be presented at the IEEE GaAs IC Symposium, Philadelphia, Pa., Oct. 16-19, 1994. |
A. G. Baca et al., Complimentary GaAs Junction Gated Heterostructure Field Effect Transistor Technology, to be presented at the IEEE GaAs IC Symposium, Philadelphia, Pa., Oct. 16 19, 1994. * |
Baca et al; "A GaAs Complementary Junction-gated HFET Technology"; Dec. 1-3, 1993; International Semiconductor Device Research Syposium. |
Baca et al; A GaAs Complementary Junction gated HFET Technology ; Dec. 1 3, 1993; International Semiconductor Device Research Syposium. * |
C. P. Lee et al., High Transconductance p Channel InGaAs/AlGaAs Modulation Doped Field Effect Transistors, IEEE Electron Device Letters , vol. EDL 8, pp. 85 87, Mar. 1987. * |
C.-P. Lee et al., "High-Transconductance p-Channel InGaAs/AlGaAs Modulation-Doped Field Effect Transistors," IEEE Electron Device Letters, vol. EDL-8, pp. 85-87, Mar. 1987. |
J. C. Zolper et al., "A Self-Aligned Zn-Gate GaAs JFET by Ion Implantation," presented at the 1993 International Semiconductor Device Research Symposium, Charlottesville, Va., Dec. 1-3, 1993. |
J. C. Zolper et al., A Self Aligned Zn Gate GaAs JFET by Ion Implantation, presented at the 1993 International Semiconductor Device Research Symposium, Charlottesville, Va., Dec. 1 3, 1993. * |
J. K. Abrokwah et al., "Anisotype-Gate Self-Aligned p-Channel Heterostructure Field-Effect Transistors," IEEE Transactions on Electron Devices, vol. 40, pp. 278-283, Feb. 1993. |
J. K. Abrokwah et al., Anisotype Gate Self Aligned p Channel Heterostructure Field Effect Transistors, IEEE Transactions on Electron Devices , vol. 40, pp. 278 283, Feb. 1993. * |
M. Ino et al., "III-V High-Speed ICs" in High-Speed Digital IC Technologies, M. Rocchi, ed. [Artech House, 1990], pp. 181-264. |
M. Ino et al., III V High Speed ICs in High Speed Digital IC Technologies , M. Rocchi, ed. Artech House, 1990 , pp. 181 264. * |
N. C. Cirillo, Jr. et al., "Complimentary Heterostructure Insulated Gate Field Effect Transistors (HIGFETs)," Proceedings of the International Electron Devices Meeting, [IEEE, 1985], pp. 317-320. |
N. C. Cirillo, Jr. et al., "Realization of n-Channel and p-Channel High-Mobility (Al,Ga)As/GaAs Heterostructure Insulating Gate FET's on a Planar Wafer Surface," IEEE Electron Device Letters, vol. EDL-6, pp. 645-647, Dec. 1985. |
N. C. Cirillo, Jr. et al., Complimentary Heterostructure Insulated Gate Field Effect Transistors (HIGFETs), Proceedings of the International Electron Devices Meeting , IEEE, 1985 , pp. 317 320. * |
N. C. Cirillo, Jr. et al., Realization of n Channel and p Channel High Mobility (Al,Ga)As/GaAs Heterostructure Insulating Gate FET s on a Planar Wafer Surface, IEEE Electron Device Letters , vol. EDL 6, pp. 645 647, Dec. 1985. * |
P. P. Ruden et al., "High Performance Complimentary Logic Based on GaAs/InGaAs/AlGaAs HIGFETs," Proceedings of the International Electron Devices Meeting, [IEEE, 1989], pp. 117-120. |
P. P. Ruden et al., "Quantum-Well p-Channel AlGaAs/InGaAs/GaAs Heterostructure Insulated-Gate Field-Effect Transistors," IEEE Transactions on Electron Devices, vol. 36, pp. 2371-2379, Nov. 1989. |
P. P. Ruden et al., High Performance Complimentary Logic Based on GaAs/InGaAs/AlGaAs HIGFETs, Proceedings of the International Electron Devices Meeting , IEEE, 1989 , pp. 117 120. * |
P. P. Ruden et al., Quantum Well p Channel AlGaAs/InGaAs/GaAs Heterostructure Insulated Gate Field Effect Transistors, IEEE Transactions on Electron Devices , vol. 36, pp. 2371 2379, Nov. 1989. * |
R. A. Kiehl et al., "The Potential of Complimentary Heterostructure FET IC's," IEEE Transactions on Electron Devices, vol. ED-34, pp. 2412-2421, Dec. 1987. |
R. A. Kiehl et al., The Potential of Complimentary Heterostructure FET IC s, IEEE Transactions on Electron Devices , vol. ED 34, pp. 2412 2421, Dec. 1987. * |
R. R. Daniels et al., "Complimentary Heterostructure Insulated Gate FET Circuits for High-Speed, Low Power VLSI," Proceedings of the International Electron Devices Meeting, [IEEE, 1986], pp. 448-451. |
R. R. Daniels et al., "Quantum-Well p-Channel AlGaAs/InGaAs/GaAs Heterostructure Insulated-Gate Field Effect Transistors with Very High Transconductance," IEEE Electron Device Letters, vol. 9, pp. 355-357, Jul. 1988. |
R. R. Daniels et al., Complimentary Heterostructure Insulated Gate FET Circuits for High Speed, Low Power VLSI, Proceedings of the International Electron Devices Meeting , IEEE, 1986 , pp. 448 451. * |
R. R. Daniels et al., Quantum Well p Channel AlGaAs/InGaAs/GaAs Heterostructure Insulated Gate Field Effect Transistors with Very High Transconductance, IEEE Electron Device Letters , vol. 9, pp. 355 357, Jul. 1988. * |
T. Mizutani et al., "Complimentary Circuit with AlGaAs/GaAs Heterostructure MISFETs Employing High-Mobility Two-Dimensional Electron and Hole Gases," Electronics Letters, vol. 21, pp. 1116-1117, 7 Nov. 1985. |
T. Mizutani et al., Complimentary Circuit with AlGaAs/GaAs Heterostructure MISFETs Employing High Mobility Two Dimensional Electron and Hole Gases, Electronics Letters , vol. 21, pp. 1116 1117, 7 Nov. 1985. * |
Zuleeq et al; "Double Implanted GaAs Complementary JFET's " IEEE Electron Device Letters, vol. EDL-5, No. 1; Jan. 1, 1984 pp. 21-23. |
Zuleeq et al; Double Implanted GaAs Complementary JFET s IEEE Electron Device Letters, vol. EDL 5, No. 1; Jan. 1, 1984 pp. 21 23. * |
Cited By (274)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5977560A (en) * | 1994-10-24 | 1999-11-02 | Micron Technology, Inc. | Thin film transistor constructions with polycrystalline silicon-germanium alloy doped with carbon in the channel region |
US5985703A (en) * | 1994-10-24 | 1999-11-16 | Banerjee; Sanjay | Method of making thin film transistors |
US6320202B1 (en) | 1994-10-24 | 2001-11-20 | Micron Technology, Inc. | Bottom-gated thin film transistors comprising germanium in a channel region |
US6384432B1 (en) | 1996-10-11 | 2002-05-07 | Trw Inc. | Gallium antimonide complementary HFET |
US6054729A (en) * | 1996-10-11 | 2000-04-25 | Trw Inc. | Gallium antimonide complementary HFET |
US5940695A (en) * | 1996-10-11 | 1999-08-17 | Trw Inc. | Gallium antimonide complementary HFET |
US6876010B1 (en) | 1997-06-24 | 2005-04-05 | Massachusetts Institute Of Technology | Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization |
US7250359B2 (en) | 1997-06-24 | 2007-07-31 | Massachusetts Institute Of Technology | Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization |
US7081410B2 (en) | 1997-06-24 | 2006-07-25 | Massachusetts Institute Of Technology | Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization |
US7227176B2 (en) | 1998-04-10 | 2007-06-05 | Massachusetts Institute Of Technology | Etch stop layer system |
US6222234B1 (en) * | 1998-04-15 | 2001-04-24 | Nec Corporation | Semiconductor device having partially and fully depleted SOI elements on a common substrate |
US6461907B2 (en) | 1998-04-15 | 2002-10-08 | Nec Corporation | Semiconductor device and fabrication method |
US6703144B2 (en) | 2000-01-20 | 2004-03-09 | Amberwave Systems Corporation | Heterointegration of materials using deposition and bonding |
US6864115B2 (en) | 2000-01-20 | 2005-03-08 | Amberwave Systems Corporation | Low threading dislocation density relaxed mismatched epilayers without high temperature growth |
US6693033B2 (en) | 2000-02-10 | 2004-02-17 | Motorola, Inc. | Method of removing an amorphous oxide from a monocrystalline surface |
US6429103B1 (en) * | 2000-04-13 | 2002-08-06 | Motorola, Inc. | MOCVD-grown emode HIGFET buffer |
US20020017644A1 (en) * | 2000-05-26 | 2002-02-14 | Fitzgerald Eugene A. | Buried channel strained silicon FET using a supply layer created through ion implantation |
US20060011983A1 (en) * | 2000-05-26 | 2006-01-19 | Amberwave Systems Corporation | Methods of fabricating strained-channel FET having a dopant supply region |
US6555839B2 (en) * | 2000-05-26 | 2003-04-29 | Amberwave Systems Corporation | Buried channel strained silicon FET using a supply layer created through ion implantation |
US6821829B1 (en) | 2000-06-12 | 2004-11-23 | Freescale Semiconductor, Inc. | Method of manufacturing a semiconductor component and semiconductor component thereof |
WO2002009186A2 (en) * | 2000-07-24 | 2002-01-31 | Motorola, Inc. | Field effect transistor |
US6590236B1 (en) | 2000-07-24 | 2003-07-08 | Motorola, Inc. | Semiconductor structure for use with high-frequency signals |
US6555946B1 (en) | 2000-07-24 | 2003-04-29 | Motorola, Inc. | Acoustic wave device and process for forming the same |
WO2002009186A3 (en) * | 2000-07-24 | 2002-05-02 | Motorola Inc | Field effect transistor |
US7799089B2 (en) | 2000-08-04 | 2010-09-21 | Depuy Orthopaedics, Inc. | Reinforced small intestinal submucosa |
US8366787B2 (en) | 2000-08-04 | 2013-02-05 | Depuy Products, Inc. | Hybrid biologic-synthetic bioabsorbable scaffolds |
US7160333B2 (en) | 2000-08-04 | 2007-01-09 | Depuy Orthopaedics, Inc. | Reinforced small intestinal submucosa |
US6713326B2 (en) | 2000-08-16 | 2004-03-30 | Masachusetts Institute Of Technology | Process for producing semiconductor article using graded epitaxial growth |
US6737670B2 (en) | 2000-08-16 | 2004-05-18 | Massachusetts Institute Of Technology | Semiconductor substrate structure |
US6921914B2 (en) | 2000-08-16 | 2005-07-26 | Massachusetts Institute Of Technology | Process for producing semiconductor article using graded epitaxial growth |
US6638838B1 (en) | 2000-10-02 | 2003-10-28 | Motorola, Inc. | Semiconductor structure including a partially annealed layer and method of forming the same |
US6649480B2 (en) | 2000-12-04 | 2003-11-18 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs |
US6881632B2 (en) | 2000-12-04 | 2005-04-19 | Amberwave Systems Corporation | Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETS |
US6673646B2 (en) | 2001-02-28 | 2004-01-06 | Motorola, Inc. | Growth of compound semiconductor structures on patterned oxide films and process for fabricating same |
US7501351B2 (en) | 2001-03-02 | 2009-03-10 | Amberwave Systems Corporation | Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits |
US8822282B2 (en) | 2001-03-02 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of fabricating contact regions for FET incorporating SiGe |
US7256142B2 (en) | 2001-03-02 | 2007-08-14 | Amberwave Systems Corporation | Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits |
US6724008B2 (en) | 2001-03-02 | 2004-04-20 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6723661B2 (en) | 2001-03-02 | 2004-04-20 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6703688B1 (en) | 2001-03-02 | 2004-03-09 | Amberwave Systems Corporation | Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits |
US6940089B2 (en) | 2001-04-04 | 2005-09-06 | Massachusetts Institute Of Technology | Semiconductor device structure |
US7348259B2 (en) | 2001-04-04 | 2008-03-25 | Massachusetts Institute Of Technology | Method of fabricating a semiconductor structure that includes transferring one or more material layers to a substrate and smoothing an exposed surface of at least one of the material layers |
US8436336B2 (en) | 2001-06-18 | 2013-05-07 | Massachusetts Institute Of Technology | Structure and method for a high-speed semiconductor device having a Ge channel layer |
US20030052334A1 (en) * | 2001-06-18 | 2003-03-20 | Lee Minjoo L. | Structure and method for a high-speed semiconductor device |
US7301180B2 (en) | 2001-06-18 | 2007-11-27 | Massachusetts Institute Of Technology | Structure and method for a high-speed semiconductor device having a Ge channel layer |
US6709989B2 (en) | 2001-06-21 | 2004-03-23 | Motorola, Inc. | Method for fabricating a semiconductor structure including a metal oxide interface with silicon |
US20050151164A1 (en) * | 2001-06-21 | 2005-07-14 | Amberwave Systems Corporation | Enhancement of p-type metal-oxide-semiconductor field effect transistors |
US20020197803A1 (en) * | 2001-06-21 | 2002-12-26 | Amberwave Systems Corporation | Enhancement of p-type metal-oxide-semiconductor field effect transistors |
US7819918B2 (en) | 2001-07-16 | 2010-10-26 | Depuy Products, Inc. | Implantable tissue repair device |
US8012205B2 (en) | 2001-07-16 | 2011-09-06 | Depuy Products, Inc. | Cartilage repair and regeneration device |
US7914808B2 (en) | 2001-07-16 | 2011-03-29 | Depuy Products, Inc. | Hybrid biologic/synthetic porous extracellular matrix scaffolds |
US8337537B2 (en) | 2001-07-16 | 2012-12-25 | Depuy Products, Inc. | Device from naturally occurring biologically derived materials |
WO2003007879A2 (en) | 2001-07-16 | 2003-01-30 | Depuy Products, Inc. | Cartilage repair and regeneration scaffold and method |
US20080167716A1 (en) * | 2001-07-16 | 2008-07-10 | Schwartz Hebert E | Cartilage repair apparatus and method |
US7361195B2 (en) | 2001-07-16 | 2008-04-22 | Depuy Products, Inc. | Cartilage repair apparatus and method |
US7201917B2 (en) | 2001-07-16 | 2007-04-10 | Depuy Products, Inc. | Porous delivery scaffold and method |
WO2003007839A2 (en) | 2001-07-16 | 2003-01-30 | Depuy Products, Inc. | Devices form naturally occurring biologically derived |
US7163563B2 (en) | 2001-07-16 | 2007-01-16 | Depuy Products, Inc. | Unitary surgical device and method |
WO2003007787A2 (en) | 2001-07-16 | 2003-01-30 | Depuy Products, Inc. | Cartilage repair and regeneration device and method |
US8025896B2 (en) | 2001-07-16 | 2011-09-27 | Depuy Products, Inc. | Porous extracellular matrix scaffold and method |
US8092529B2 (en) | 2001-07-16 | 2012-01-10 | Depuy Products, Inc. | Meniscus regeneration device |
US6646293B2 (en) | 2001-07-18 | 2003-11-11 | Motorola, Inc. | Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates |
US6693298B2 (en) | 2001-07-20 | 2004-02-17 | Motorola, Inc. | Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same |
US6667196B2 (en) | 2001-07-25 | 2003-12-23 | Motorola, Inc. | Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method |
US6639249B2 (en) | 2001-08-06 | 2003-10-28 | Motorola, Inc. | Structure and method for fabrication for a solid-state lighting device |
US20040164318A1 (en) * | 2001-08-06 | 2004-08-26 | Massachusetts Institute Of Technology | Structures with planar strained layers |
US6589856B2 (en) | 2001-08-06 | 2003-07-08 | Motorola, Inc. | Method and apparatus for controlling anti-phase domains in semiconductor structures and devices |
US20050221550A1 (en) * | 2001-08-09 | 2005-10-06 | Amberwave Systems Corporation | Dual layer semiconductor devices |
US6974735B2 (en) | 2001-08-09 | 2005-12-13 | Amberwave Systems Corporation | Dual layer Semiconductor Devices |
US7465619B2 (en) | 2001-08-09 | 2008-12-16 | Amberwave Systems Corporation | Methods of fabricating dual layer semiconductor devices |
US20030057439A1 (en) * | 2001-08-09 | 2003-03-27 | Fitzgerald Eugene A. | Dual layer CMOS devices |
US6673667B2 (en) | 2001-08-15 | 2004-01-06 | Motorola, Inc. | Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials |
US7776697B2 (en) | 2001-09-21 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
US7884353B2 (en) | 2001-09-21 | 2011-02-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
US7846802B2 (en) | 2001-09-21 | 2010-12-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same |
US7906776B2 (en) | 2001-09-24 | 2011-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | RF circuits including transistors having strained material layers |
US6933518B2 (en) | 2001-09-24 | 2005-08-23 | Amberwave Systems Corporation | RF circuits including transistors having strained material layers |
US7709828B2 (en) | 2001-09-24 | 2010-05-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | RF circuits including transistors having strained material layers |
US20040217444A1 (en) * | 2001-10-17 | 2004-11-04 | Motorola, Inc. | Method and apparatus utilizing monocrystalline insulator |
US6777728B2 (en) * | 2001-12-28 | 2004-08-17 | Fujitsu Limited | Semiconductor device and complementary semiconductor device |
US20030155592A1 (en) * | 2001-12-28 | 2003-08-21 | Masashi Shima | Semiconductor device and complementary semiconductor device |
US7060632B2 (en) | 2002-03-14 | 2006-06-13 | Amberwave Systems Corporation | Methods for fabricating strained layers on semiconductor substrates |
US7259108B2 (en) | 2002-03-14 | 2007-08-21 | Amberwave Systems Corporation | Methods for fabricating strained layers on semiconductor substrates |
US8748292B2 (en) | 2002-06-07 | 2014-06-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of forming strained-semiconductor-on-insulator device structures |
US7297612B2 (en) | 2002-06-07 | 2007-11-20 | Amberwave Systems Corporation | Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes |
US7138310B2 (en) * | 2002-06-07 | 2006-11-21 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
US7838392B2 (en) | 2002-06-07 | 2010-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for forming III-V semiconductor device structures |
US7566606B2 (en) | 2002-06-07 | 2009-07-28 | Amberwave Systems Corporation | Methods of fabricating semiconductor devices having strained dual channel layers |
US20040026765A1 (en) * | 2002-06-07 | 2004-02-12 | Amberwave Systems Corporation | Semiconductor devices having strained dual channel layers |
US7420201B2 (en) | 2002-06-07 | 2008-09-02 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures with elevated source/drain regions |
US7109516B2 (en) | 2002-06-07 | 2006-09-19 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator finFET device structures |
US7074623B2 (en) | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
US7414259B2 (en) | 2002-06-07 | 2008-08-19 | Amberwave Systems Corporation | Strained germanium-on-insulator device structures |
US7259388B2 (en) | 2002-06-07 | 2007-08-21 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US7588994B2 (en) | 2002-06-07 | 2009-09-15 | Amberwave Systems Corporation | Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain |
US7615829B2 (en) | 2002-06-07 | 2009-11-10 | Amberwave Systems Corporation | Elevated source and drain elements for strained-channel heterojuntion field-effect transistors |
US7335545B2 (en) | 2002-06-07 | 2008-02-26 | Amberwave Systems Corporation | Control of strain in device layers by prevention of relaxation |
US6995430B2 (en) | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US7307273B2 (en) | 2002-06-07 | 2007-12-11 | Amberwave Systems Corporation | Control of strain in device layers by selective relaxation |
US7122449B2 (en) | 2002-06-10 | 2006-10-17 | Amberwave Systems Corporation | Methods of fabricating semiconductor structures having epitaxially grown source and drain elements |
US7439164B2 (en) | 2002-06-10 | 2008-10-21 | Amberwave Systems Corporation | Methods of fabricating semiconductor structures having epitaxially grown source and drain elements |
US8129821B2 (en) | 2002-06-25 | 2012-03-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Reacted conductive gate electrodes |
US7217603B2 (en) | 2002-06-25 | 2007-05-15 | Amberwave Systems Corporation | Methods of forming reacted conductive gate electrodes |
US7375385B2 (en) | 2002-08-23 | 2008-05-20 | Amberwave Systems Corporation | Semiconductor heterostructures having reduced dislocation pile-ups |
US7829442B2 (en) | 2002-08-23 | 2010-11-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor heterostructures having reduced dislocation pile-ups and related methods |
US7368308B2 (en) | 2002-08-23 | 2008-05-06 | Amberwave Systems Corporation | Methods of fabricating semiconductor heterostructures |
US7594967B2 (en) | 2002-08-30 | 2009-09-29 | Amberwave Systems Corporation | Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy |
US7332417B2 (en) | 2003-01-27 | 2008-02-19 | Amberwave Systems Corporation | Semiconductor structures with structural homogeneity |
US7504704B2 (en) | 2003-03-07 | 2009-03-17 | Amberwave Systems Corporation | Shallow trench isolation process |
US20040195623A1 (en) * | 2003-04-03 | 2004-10-07 | Chung-Hu Ge | Strained channel on insulator device |
US6900502B2 (en) | 2003-04-03 | 2005-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel on insulator device |
US7029994B2 (en) | 2003-04-03 | 2006-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel on insulator device |
US20050233552A1 (en) * | 2003-04-03 | 2005-10-20 | Chung-Hu Ke | Strained channel on insulator device |
US7052964B2 (en) | 2003-04-25 | 2006-05-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel transistor and methods of manufacture |
US20050156274A1 (en) * | 2003-04-25 | 2005-07-21 | Yee-Chia Yeo | Strained channel transistor and methods of manufacture |
US7268024B2 (en) | 2003-04-30 | 2007-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
US7820513B2 (en) | 2003-06-27 | 2010-10-26 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US8273626B2 (en) | 2003-06-27 | 2012-09-25 | Intel Corporationn | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US7456476B2 (en) | 2003-06-27 | 2008-11-25 | Intel Corporation | Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication |
US8405164B2 (en) | 2003-06-27 | 2013-03-26 | Intel Corporation | Tri-gate transistor device with stress incorporation layer and method of fabrication |
US7745279B2 (en) | 2003-07-25 | 2010-06-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Capacitor that includes high permittivity capacitor dielectric |
US7037772B2 (en) | 2003-07-25 | 2006-05-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing an integrated circuit including capacitor with high permittivity capacitor dielectric |
US7867860B2 (en) | 2003-07-25 | 2011-01-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel transistor formation |
US7354843B2 (en) | 2003-07-25 | 2008-04-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a capacitor that includes forming a bottom electrode in a strained silicon layer |
US20050208717A1 (en) * | 2003-07-25 | 2005-09-22 | Yee-Chia Yeo | Capacitor with enhanced performance and method of manufacture |
US20050248906A1 (en) * | 2003-07-25 | 2005-11-10 | Yee-Chia Yeo | Capacitor that includes high permittivity capacitor dielectric |
US7442967B2 (en) | 2003-08-12 | 2008-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel complementary field-effect transistors |
US20050035470A1 (en) * | 2003-08-12 | 2005-02-17 | Chih-Hsin Ko | Strained channel complementary field-effect transistors and methods of manufacture |
US7101742B2 (en) | 2003-08-12 | 2006-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel complementary field-effect transistors and methods of manufacture |
US20060189056A1 (en) * | 2003-08-12 | 2006-08-24 | Chih-Hsin Ko | Strained channel complementary field-effect transistors and methods of manufacture |
US20050035409A1 (en) * | 2003-08-15 | 2005-02-17 | Chih-Hsin Ko | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
US20050035369A1 (en) * | 2003-08-15 | 2005-02-17 | Chun-Chieh Lin | Structure and method of forming integrated circuits utilizing strained channel transistors |
US7112495B2 (en) | 2003-08-15 | 2006-09-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
US20050035410A1 (en) * | 2003-08-15 | 2005-02-17 | Yee-Chia Yeo | Semiconductor diode with reduced leakage |
US7646068B2 (en) | 2003-08-15 | 2010-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit |
US20050040493A1 (en) * | 2003-08-18 | 2005-02-24 | Yee-Chia Yeo | Resistor with reduced leakage |
US7071052B2 (en) | 2003-08-18 | 2006-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Resistor with reduced leakage |
US7888201B2 (en) | 2003-11-04 | 2011-02-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors |
US20050186722A1 (en) * | 2004-02-25 | 2005-08-25 | Kuan-Lun Cheng | Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions |
WO2005089411A2 (en) | 2004-03-17 | 2005-09-29 | Revivicor, Inc. | Tissue products from animals lacking functional alpha 1,3 galactosyl transferase |
EP2433492A1 (en) | 2004-03-17 | 2012-03-28 | Revivicor Inc. | Tissue products derived from animals lacking any expression of functional alpha 1,3 galactosyltransferase |
US7781771B2 (en) | 2004-03-31 | 2010-08-24 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US7569233B2 (en) | 2004-05-04 | 2009-08-04 | Depuy Products, Inc. | Hybrid biologic-synthetic bioabsorbable scaffolds |
US20050266632A1 (en) * | 2004-05-26 | 2005-12-01 | Yun-Hsiu Chen | Integrated circuit with strained and non-strained transistors, and method of forming thereof |
US8084818B2 (en) | 2004-06-30 | 2011-12-27 | Intel Corporation | High mobility tri-gate devices and methods of fabrication |
US7960794B2 (en) | 2004-08-10 | 2011-06-14 | Intel Corporation | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US20080169512A1 (en) * | 2004-08-10 | 2008-07-17 | Doyle Brian S | Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow |
US8399922B2 (en) | 2004-09-29 | 2013-03-19 | Intel Corporation | Independently accessed double-gate and tri-gate transistors |
US8268709B2 (en) | 2004-09-29 | 2012-09-18 | Intel Corporation | Independently accessed double-gate and tri-gate transistors in same process flow |
US9190518B2 (en) | 2004-10-25 | 2015-11-17 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US10236356B2 (en) | 2004-10-25 | 2019-03-19 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US8067818B2 (en) | 2004-10-25 | 2011-11-29 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US8502351B2 (en) | 2004-10-25 | 2013-08-06 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US8749026B2 (en) | 2004-10-25 | 2014-06-10 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US9741809B2 (en) | 2004-10-25 | 2017-08-22 | Intel Corporation | Nonplanar device with thinned lower body portion and method of fabrication |
US7513866B2 (en) | 2004-10-29 | 2009-04-07 | Depuy Products, Inc. | Intestine processing device and associated method |
US8183627B2 (en) | 2004-12-01 | 2012-05-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid fin field-effect transistor structures and related methods |
US7393733B2 (en) | 2004-12-01 | 2008-07-01 | Amberwave Systems Corporation | Methods of forming hybrid fin field-effect transistor structures |
US7354627B2 (en) | 2004-12-22 | 2008-04-08 | Depuy Products, Inc. | Method for organizing the assembly of collagen fibers and compositions formed therefrom |
US8368135B2 (en) | 2005-02-23 | 2013-02-05 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US9614083B2 (en) | 2005-02-23 | 2017-04-04 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US9368583B2 (en) | 2005-02-23 | 2016-06-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US9748391B2 (en) | 2005-02-23 | 2017-08-29 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US8816394B2 (en) | 2005-02-23 | 2014-08-26 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US10121897B2 (en) | 2005-02-23 | 2018-11-06 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US9048314B2 (en) | 2005-02-23 | 2015-06-02 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US8664694B2 (en) | 2005-02-23 | 2014-03-04 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US8183646B2 (en) | 2005-02-23 | 2012-05-22 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US7879675B2 (en) | 2005-03-14 | 2011-02-01 | Intel Corporation | Field effect transistor with metal source/drain regions |
US11978799B2 (en) | 2005-06-15 | 2024-05-07 | Tahoe Research, Ltd. | Method for fabricating transistor with thinned channel |
US9806195B2 (en) | 2005-06-15 | 2017-10-31 | Intel Corporation | Method for fabricating transistor with thinned channel |
US9337307B2 (en) | 2005-06-15 | 2016-05-10 | Intel Corporation | Method for fabricating transistor with thinned channel |
US9385180B2 (en) | 2005-06-21 | 2016-07-05 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US8581258B2 (en) | 2005-06-21 | 2013-11-12 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US8933458B2 (en) | 2005-06-21 | 2015-01-13 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US9761724B2 (en) | 2005-06-21 | 2017-09-12 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US8071983B2 (en) | 2005-06-21 | 2011-12-06 | Intel Corporation | Semiconductor device structures and methods of forming semiconductor structures |
US7898041B2 (en) | 2005-06-30 | 2011-03-01 | Intel Corporation | Block contact architectures for nanoscale channel transistors |
US7364997B2 (en) * | 2005-07-07 | 2008-04-29 | Micron Technology, Inc. | Methods of forming integrated circuitry and methods of forming local interconnects |
US20070010078A1 (en) * | 2005-07-07 | 2007-01-11 | Micron Technology, Inc. | Methods of forming integrated circuitry and methods of forming local interconnects |
US7595062B2 (en) | 2005-07-28 | 2009-09-29 | Depuy Products, Inc. | Joint resurfacing orthopaedic implant and associated method |
US7736956B2 (en) | 2005-08-17 | 2010-06-15 | Intel Corporation | Lateral undercut of metal gate in SOI device |
US8193567B2 (en) | 2005-09-28 | 2012-06-05 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US7479421B2 (en) | 2005-09-28 | 2009-01-20 | Intel Corporation | Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby |
US20070090416A1 (en) * | 2005-09-28 | 2007-04-26 | Doyle Brian S | CMOS devices with a single work function gate electrode and method of fabrication |
US7902014B2 (en) | 2005-09-28 | 2011-03-08 | Intel Corporation | CMOS devices with a single work function gate electrode and method of fabrication |
US8294180B2 (en) | 2005-09-28 | 2012-10-23 | Intel Corporation | CMOS devices with a single work function gate electrode and method of fabrication |
US7989280B2 (en) | 2005-11-30 | 2011-08-02 | Intel Corporation | Dielectric interface for group III-V semiconductor device |
WO2007076791A1 (en) * | 2005-12-12 | 2007-07-12 | Infineon Technologies Ag | Method for the production of a compound semiconductor field effect transistor comprising a fin structure, and compound semiconductor field effect transistor comprising a fin structure |
US20080224183A1 (en) * | 2005-12-12 | 2008-09-18 | Muhammad Nawaz | Method for Manufacturing a Compound Semiconductor Field Effect Transistor Having a Fin Structure, and Compound Semiconductor Field Effect Transistor Having a Fin Structure |
US8518768B2 (en) | 2005-12-15 | 2013-08-27 | Intel Corporation | Extreme high mobility CMOS logic |
US8183556B2 (en) | 2005-12-15 | 2012-05-22 | Intel Corporation | Extreme high mobility CMOS logic |
US8802517B2 (en) | 2005-12-15 | 2014-08-12 | Intel Corporation | Extreme high mobility CMOS logic |
US10141437B2 (en) | 2005-12-15 | 2018-11-27 | Intel Corporation | Extreme high mobility CMOS logic |
US20070138565A1 (en) * | 2005-12-15 | 2007-06-21 | Intel Corporation | Extreme high mobility CMOS logic |
US9691856B2 (en) | 2005-12-15 | 2017-06-27 | Intel Corporation | Extreme high mobility CMOS logic |
US9548363B2 (en) | 2005-12-15 | 2017-01-17 | Intel Corporation | Extreme high mobility CMOS logic |
US8617945B2 (en) | 2006-08-02 | 2013-12-31 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US8143646B2 (en) | 2006-08-02 | 2012-03-27 | Intel Corporation | Stacking fault and twin blocking barrier for integrating III-V on Si |
US20080032478A1 (en) * | 2006-08-02 | 2008-02-07 | Hudait Mantu K | Stacking fault and twin blocking barrier for integrating III-V on Si |
US7691727B2 (en) * | 2006-08-31 | 2010-04-06 | Stmicroelectronics S.A. | Method for manufacturing an integrated circuit with fully depleted and partially depleted transistors |
US20080064174A1 (en) * | 2006-08-31 | 2008-03-13 | Stmicroelectronics S.A. | Method for manufacturing an integrated circuit with fully depleted and partially depleted transistors |
US7871440B2 (en) | 2006-12-11 | 2011-01-18 | Depuy Products, Inc. | Unitary surgical device and method |
US8558278B2 (en) | 2007-01-16 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained transistor with optimized drive current and method of forming |
US8253168B2 (en) * | 2007-06-18 | 2012-08-28 | University Of Utah Research Foundation | Transistors for replacing metal-oxide-semiconductor field-effect transistors in nanoelectronics |
US20100264425A1 (en) * | 2007-06-18 | 2010-10-21 | University Of Utah Research Foundation | Transistors for replacing metal-oxide-semiconductor field-effect transistors in nanoelectronics |
US20090218632A1 (en) * | 2008-02-28 | 2009-09-03 | International Business Machines Corporation | Cmos structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication |
US8569159B2 (en) * | 2008-02-28 | 2013-10-29 | International Business Machines Corporation | CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication |
US20120199910A1 (en) * | 2008-02-28 | 2012-08-09 | International Business Machines Corporation | Cmos structure including non-planar hybrid orientation substrate with planar gate electrodes & method for fabrication |
US8211786B2 (en) * | 2008-02-28 | 2012-07-03 | International Business Machines Corporation | CMOS structure including non-planar hybrid orientation substrate with planar gate electrodes and method for fabrication |
US7943961B2 (en) | 2008-03-13 | 2011-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain bars in stressed layers of MOS devices |
US8389316B2 (en) | 2008-03-13 | 2013-03-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strain bars in stressed layers of MOS devices |
US20090243031A1 (en) * | 2008-03-26 | 2009-10-01 | International Business Machines Corporation | Structure and method to control oxidation in high-k gate structures |
US7955926B2 (en) | 2008-03-26 | 2011-06-07 | International Business Machines Corporation | Structure and method to control oxidation in high-k gate structures |
US20100151640A1 (en) * | 2008-05-13 | 2010-06-17 | Frank Huebinger | Semiconductor Devices with Active Regions of Different Heights |
US7687862B2 (en) * | 2008-05-13 | 2010-03-30 | Infineon Technologies Ag | Semiconductor devices with active regions of different heights |
US8003458B2 (en) | 2008-05-13 | 2011-08-23 | Infineon Technologies Ag | Methods of manufacturing a semiconductor device with active regions of different heights |
US20090283837A1 (en) * | 2008-05-13 | 2009-11-19 | Frank Huebinger | Semiconductor Devices and Methods of Manufacture Thereof |
US9806193B2 (en) | 2008-06-23 | 2017-10-31 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8741733B2 (en) | 2008-06-23 | 2014-06-03 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8362566B2 (en) | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US9450092B2 (en) | 2008-06-23 | 2016-09-20 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US9224754B2 (en) | 2008-06-23 | 2015-12-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8097930B2 (en) * | 2008-08-08 | 2012-01-17 | Infineon Technologies Ag | Semiconductor devices with trench isolations |
US20100032773A1 (en) * | 2008-08-08 | 2010-02-11 | Mayank Shrivastava | Semiconductor Devices and Methods for Manufacturing a Semiconductor Device |
US7808051B2 (en) | 2008-09-29 | 2010-10-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Standard cell without OD space effect in Y-direction |
US8053304B2 (en) * | 2009-02-24 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming high-mobility devices including epitaxially growing a semiconductor layer on a dislocation-blocking layer in a recess formed in a semiconductor substrate |
TWI497692B (en) * | 2009-08-03 | 2015-08-21 | Sony Corp | Semiconductor device and method for manufacturing same |
US8378389B2 (en) * | 2009-08-03 | 2013-02-19 | Sony Corporation | Semiconductor device and method for manufacturing same |
US8575658B2 (en) | 2009-08-03 | 2013-11-05 | Sony Corporation | Semiconductor device and method for manufacturing same |
US20110024798A1 (en) * | 2009-08-03 | 2011-02-03 | Sony Corporation | Semiconductor device and method for manufacturing same |
CN101989601B (en) * | 2009-08-03 | 2013-02-27 | 索尼公司 | Semiconductor device and method for manufacturing same |
CN101989601A (en) * | 2009-08-03 | 2011-03-23 | 索尼公司 | Semiconductor device and method for manufacturing same |
US20110260173A1 (en) * | 2010-04-16 | 2011-10-27 | Tsinghua University | Semiconductor structure |
US8455858B2 (en) * | 2010-04-16 | 2013-06-04 | Tsinghua University | Semiconductor structure for reducing band-to-band tunneling (BTBT) leakage |
US20120126291A1 (en) * | 2010-10-28 | 2012-05-24 | Sony Corporation | Semiconductor device |
JP2012094774A (en) * | 2010-10-28 | 2012-05-17 | Sony Corp | Semiconductor device |
US8698202B2 (en) * | 2010-10-28 | 2014-04-15 | Sony Corporation | Semiconductor device |
US20120223391A1 (en) * | 2011-03-04 | 2012-09-06 | Fujitsu Semiconductor Limited | Semiconductor device and method of manufacturing semiconductor device |
US8704311B2 (en) * | 2011-03-04 | 2014-04-22 | Fujitsu Semiconductor Limited | Semiconductor device having epitaxial semiconductor layer above impurity layer |
US8916431B2 (en) | 2011-03-04 | 2014-12-23 | Fujitsu Semiconductor Limited | Semiconductor device having epitaxial semiconductor layer above impurity layer |
US20170271333A1 (en) * | 2012-05-16 | 2017-09-21 | Sony Corporation | Semiconductor device and manufacturing method of the same |
US10629598B2 (en) | 2012-05-16 | 2020-04-21 | Sony Corporation | Semiconductor device and manufacturing method of the same |
US8680576B2 (en) * | 2012-05-16 | 2014-03-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS device and method of forming the same |
US11031399B2 (en) | 2012-05-16 | 2021-06-08 | Sony Corporation | Semiconductor device and manufacturing method of the same |
US8927362B2 (en) | 2012-05-16 | 2015-01-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS device and method of forming the same |
US10109632B2 (en) * | 2012-05-16 | 2018-10-23 | Sony Corporation | Semiconductor device and manufacturing method of the same |
US9105499B1 (en) * | 2013-03-15 | 2015-08-11 | The United States Of America, As Represented By The Secretary Of The Navy | Complementary field effect transistors using gallium polar and nitrogen polar III-nitride material |
US20150221649A1 (en) * | 2013-03-15 | 2015-08-06 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Complementary Field Effect Transistors Using Gallium Polar and Nitrogen Polar III-Nitride Material |
US20150221647A1 (en) * | 2013-03-15 | 2015-08-06 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Complementary Field Effect Transistors Using Gallium Polar and Nitrogen Polar III-Nitride Material |
US9018056B2 (en) * | 2013-03-15 | 2015-04-28 | The United States Of America, As Represented By The Secretary Of The Navy | Complementary field effect transistors using gallium polar and nitrogen polar III-nitride material |
US20140264380A1 (en) * | 2013-03-15 | 2014-09-18 | The Government Of The United States Of America, As Represented By The Secretary Of The Navy | Complementary Field Effect Transistors Using Gallium Polar and Nitrogen Polar III-Nitride Material |
US9111786B1 (en) * | 2013-03-15 | 2015-08-18 | The United States Of America, As Represented By The Secretary Of The Navy | Complementary field effect transistors using gallium polar and nitrogen polar III-nitride material |
US9093532B2 (en) | 2013-06-21 | 2015-07-28 | International Business Machines Corporation | Overlapped III-V finFET with doped semiconductor extensions |
US9059288B2 (en) | 2013-06-21 | 2015-06-16 | International Business Machines Corporation | Overlapped III-V finfet with doped semiconductor extensions |
US9312128B2 (en) * | 2013-08-07 | 2016-04-12 | Globalfoundries Inc. | Compound semiconductor integrated circuit and method to fabricate same |
US20150041856A1 (en) * | 2013-08-07 | 2015-02-12 | International Business Machines Corporation | Compound Semiconductor Integrated Circuit and Method to Fabricate Same |
US20150044859A1 (en) * | 2013-08-07 | 2015-02-12 | International Business Machines Corporation | Compound semiconductor integrated circuit and method to fabricate same |
US9275854B2 (en) * | 2013-08-07 | 2016-03-01 | Globalfoundries Inc. | Compound semiconductor integrated circuit and method to fabricate same |
US10199477B2 (en) * | 2013-08-12 | 2019-02-05 | Nxp Usa, Inc. | Complementary gallium nitride integrated circuits |
US9818870B2 (en) * | 2013-09-27 | 2017-11-14 | Intel Corporation | Transistor structure with variable clad/core dimension for stress and bandgap |
US20160240671A1 (en) * | 2013-09-27 | 2016-08-18 | Intel Corporation | Transistor structure with variable clad/core dimension for stress and bandgap |
US20170005091A1 (en) * | 2015-06-30 | 2017-01-05 | Infineon Technologies Austria Ag | Semiconductor Devices and Method for Forming Semiconductor Devices |
US9768313B2 (en) * | 2015-10-05 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices having transition metal dichalcogenide layers with different thicknesses and methods of manufacture |
US11251185B2 (en) | 2017-08-29 | 2022-02-15 | International Business Machines Corporation | Stacked complementary junction FETs for analog electronic circuits |
US10553586B2 (en) | 2017-08-29 | 2020-02-04 | International Business Machines Corporation | Stacked complementary junction FETs for analog electronic circuits |
US10381349B2 (en) | 2017-08-29 | 2019-08-13 | International Business Machines Corporation | Stacked complementary junction FETs for analog electronic circuits |
US11349023B2 (en) * | 2019-10-01 | 2022-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integration of p-channel and n-channel E-FET III-V devices without parasitic channels |
US11843047B2 (en) | 2019-10-01 | 2023-12-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integration of p-channel and n-channel E-FET III-V devices without parasitic channels |
CN114035636A (en) * | 2021-11-12 | 2022-02-11 | 深圳飞骧科技股份有限公司 | Band gap reference starting circuit and radio frequency chip |
CN114035636B (en) * | 2021-11-12 | 2022-07-08 | 深圳飞骧科技股份有限公司 | Band gap reference starting circuit and radio frequency chip |
CN114265462A (en) * | 2021-12-15 | 2022-04-01 | 成都海光微电子技术有限公司 | Band gap reference, chip, electronic device and electronic equipment |
CN114265462B (en) * | 2021-12-15 | 2024-04-30 | 成都海光微电子技术有限公司 | Band gap reference, chip, electronic device and electronic equipment |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5479033A (en) | Complementary junction heterostructure field-effect transistor | |
JP2581355B2 (en) | Complementary heterojunction field-effect transistor with anisotropic N + gate for P-channel devices | |
JP3135939B2 (en) | HEMT type semiconductor device | |
US5155571A (en) | Complementary field effect transistors having strained superlattice structure | |
US4821090A (en) | Compound semiconductor integrated circuit device | |
US6914273B2 (en) | GaN-type enhancement MOSFET using hetero structure | |
US4583105A (en) | Double heterojunction FET with ohmic semiconductor gate and controllable low threshold voltage | |
US4830980A (en) | Making complementary integrated p-MODFET and n-MODFET | |
US4641161A (en) | Heterojunction device | |
US5161235A (en) | Field-effect compound semiconductive transistor with GaAs gate to increase barrier height and reduce turn-on threshold | |
EP0334006A1 (en) | Stacked channel heterojunction fet | |
EP0130676B1 (en) | Semiconductor device having a hetero junction | |
JPH0661441A (en) | Semiconductor device provided with complementary transistor | |
US5192698A (en) | Making staggered complementary heterostructure FET | |
US6201267B1 (en) | Compact low power complement FETs | |
JP2527775B2 (en) | Field effect transistor and method of manufacturing the same | |
US4791072A (en) | Method for making a complementary device containing MODFET | |
Cirillo et al. | Realization of n-channel and p-channel high-mobility (Al, Ga) As/GaAs heterostructure insulating gate FET's on a planar wafer surface | |
US4866491A (en) | Heterojunction field effect transistor having gate threshold voltage capability | |
EP0283878B1 (en) | Field effect transistor | |
JPH02111073A (en) | Insulated gate fet and integrated circuit device thereof | |
US5355005A (en) | Self-doped complementary field effect transistor | |
Baca et al. | Complementary GaAs junction-gated heterostructure field effect transistor technology | |
JP3006792B2 (en) | Heterostructure field effect transistor | |
JPS62199049A (en) | Semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SANDIA CORPORATION, NEW MEXICO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BACA, ALBERT G.;DRUMMOND, TIMOTHY J.;ROBERSTON, PERRY J.;AND OTHERS;REEL/FRAME:007078/0684;SIGNING DATES FROM 19940527 TO 19940620 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
CC | Certificate of correction | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 19991226 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
ERR | Erratum |
Free format text: IN THE NOTICE OF "PATENTS WHICH EXPIRED ON 19991226 DUE TO FAILURE TO PAY MAINTENANCE FEES" APPEARING IN THE OFFICIAL GAZETTE OF 20000307, ALL REFERENCE TO PATENT NO. 5479033 WHICH ISSUED FROM APPLICATION NO. 08/250088 SHOULD BE DELETED SINCE THE RELEVANT MAINTENANCE FEE WAS TIMELY PAID IN THAT PATENT. |