US5416802A - Receiver circuit for digital and analog modulated signal - Google Patents

Receiver circuit for digital and analog modulated signal Download PDF

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Publication number
US5416802A
US5416802A US08063694 US6369493A US5416802A US 5416802 A US5416802 A US 5416802A US 08063694 US08063694 US 08063694 US 6369493 A US6369493 A US 6369493A US 5416802 A US5416802 A US 5416802A
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Prior art keywords
signal
intermediate frequency
digital
amplifier
frequency signal
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Expired - Fee Related
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US08063694
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Junichi Ishii
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NEC Corp
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NEC Corp
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits
    • H04B1/26Circuits for superheterodyne receivers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/0002Modulated-carrier systems analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M1/00Substation equipment, e.g. for use by subscribers; Analogous equipment at exchanges
    • H04M1/72Substation extension arrangements; Cordless telephones, i.e. devices for establishing wireless links to base stations without route selecting
    • H04M1/725Cordless telephones
    • H04M1/72502Cordless telephones with one base station connected to a single line

Abstract

A receiver circuit for receiving both digital and analog modulated signals has a high frequency amplifier for amplifying digital and analog modulated high frequency signals, a down conversion block for converting an output signal from the high frequency amplifier into an intermediate frequency signal, a root Nyquist bandpass filter for limiting the intermediate frequency signal from the down conversion block to a frequency band based on root Nyquist characteristics, an intermediate frequency signal linear amplifier for linearly amplifying the intermediate frequency signal from the root Nyquist bandpass filter, a limiter amplifier for limiting to a constant amplitude the intermediate frequency signal from the intermediate frequency signal linear amplifier, a received signal intensity detector for detecting received signal intensity information from the intermediate frequency signal from the intermediate frequency signal linear amplifier, a synchronizing clock signal generator for generating a synchronizing clock signal from the received signal intensity information from the received signal intensity detector, a digital demodulator for demodulating a digital modulated intermediate frequency signal from the limiter amplifier based on the synchronizing clock signal, and an analog demodulator for demodulating an analog modulated intermediate frequency signal from the limiter amplifier.

Description

BACKGROUND OF THE INVENTION

1. Filed of the Invention

The present invention relates to a receiver circuit for receiving an analog modulated signal as well as a digital modulated signal.

2. Description of the Related Art

Cellular communication systems that are currently in service as mobile radio communication systems are required to increase system capacity as the number of subscribers increases. To meet this need, a switch from the conventional analog cellular communication systems to digital cellular communication systems is taking place in various countries in North America, Europe, and in Japan. In North America, both analog and digital cellular communication systems employ the same frequency band, and cellular terminals must therefore be dual-mode devices capable of connecting with analog and digital cellular communication systems.

FIG. 1 of the accompanying drawings shows a receiver circuit of a conventional dual-mode device. The receiver circuit comprises a high frequency amplifier 1, a bandpass filter 2, a down conversion block 16, intermediate frequency bandpass filters 8, 10, an intermediate frequency signal linear amplifier 9, a limiter amplifier 11, an analog demodulator 12, an automatic-gain-control amplifier 19, a digital demodulator 14, and a received signal intensity detector 15. The received signal intensity detector 15 outputs received signal intensity information SRSS. The down conversion block 16 comprises mixers 3, 6, local oscillators 4, 7, and a bandpass filter 5.

The receiver circuit shown in FIG. 1 operates as follows:

A digital modulated signal that has been received is amplified by the high frequency amplifier 1 and then limited to a certain received frequency band by the bandpass filter 2. The digital modulated signal is thereafter converted into an intermediate frequency signal by the down conversion block 16. The digital modulated intermediate frequency signal from the down conversion block 16 is passed through the intermediate frequency bandpass filter 8 and applied to the intermediate frequency signal linear amplifier 9, which linearly amplifies the applied signal. The amplified signal from the intermediate frequency signal linear amplifier 9 is again limited to a frequency band by the intermediate frequency bandpass filter 10. The digital modulated intermediate frequency signal from the intermediate frequency bandpass filter 10 is then linearly amplified by the automatic gain control amplifier 19. The digital demodulator 14 produces I and Q signals from the amplified signal from the automatic gain control amplifier 19. The I and Q signals pass through respective root Nyquist filters (not shown), which output orthogonally demodulated signals. An analog modulated signal that has been received is processed into an intermediate frequency signal by the same circuit components as the digital modulated signal up to the intermediate frequency bandpass filter 10. The intermediate frequency signal produced from the analog modulated signal is then limited to a certain amplitude and amplified by the limiter amplifier 11 and demodulated into an analog demodulated signal by the analog demodulator 12.

A conventional receiver circuit capable of receiving both digital and analog modulated signals is composed of many parts and is complex in circuit arrangement because for digital signal demodulation it requires the automatic gain control amplifier for linearly amplifying the intermediate frequency signal and the bandpass filter having characteristics approximating root Nyquist characteristics to limit the frequency bands of the I and Q signals, and for analog signal demodulation, it also requires the limiter amplifier for limiting and amplifying the intermediate frequency signal.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a receiver circuit for receiving both digital and analog modulated signals which is made up of a relatively small number of parts and is of a relatively simple circuit arrangement.

To achieve the above object, in accordance with the present invention, there is provided a receiver circuit for receiving both digital and analog modulated signals that comprises a frequency converter for converting digital and analog modulated high frequency signals into respective intermediate frequency signals, a root Nyquist bandpass filter for limiting an intermediate frequency signal from the frequency converter to a frequency band based on root Nyquist characteristics, an intermediate frequency signal linear amplifier for linearly amplifying the intermediate frequency signal that has passed through the root Nyquist bandpass filter, a limiter amplifier for limiting to a constant amplitude the intermediate frequency signal from the intermediate frequency signal linear amplifier, a digital demodulator connected to the limiter amplifier for demodulating a digital modulated intermediate frequency signal from the limiter amplifier, and an analog demodulator connected to the limiter amplifier parallel to the digital demodulator for demodulating an analog modulated intermediate frequency signal from the limiter amplifier.

The receiver circuit may further comprise a received signal intensity detector for detecting received signal intensity information from the intermediate frequency signal amplified by the intermediate frequency signal linear amplifier.

The receiver circuit may further comprise a first synchronizing clock signal generator for generating a synchronizing clock signal from the received signal intensity information detected by the received signal intensity detector and applying the synchronizing clock signal to the digital demodulator.

The receiver circuit may further comprise a second synchronizing clock signal generator for generating a synchronizing clock signal from the digital modulated intermediate frequency signal from the limiter amplifier and applying the synchronizing clock signal to the digital demodulator.

The receiver circuit may further comprise a high frequency amplifier for amplifying the digital and analog modulated high frequency signals and applying said amplified high frequency signals to said frequency converter.

The receiver circuit may further comprise a bandpass filter connected between said high frequency amplifier and said frequency converter for limiting an output signal from said high frequency amplifier to a predetermined frequency band.

The above and other objects, features, and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional receiver circuit for receiving both digital and analog modulated signals;

FIG. 2 is a block diagram of a receiver circuit for receiving both digital and analog modulated signals according to a first embodiment of the present invention; and

FIG. 3 is a block diagram of a receiver circuit for receiving both digital and analog modulated signals according to a second embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 shows in block form a receiver circuit for receiving both digital and analog modulated signals according to a first embodiment of the present invention. Those parts shown in FIG. 2 which are identical to those of the conventional receiver circuit shown in FIG. 1 are denoted by identical reference numerals.

The receiver circuit shown in FIG. 2 comprises a high frequency amplifier 1, a bandpass filter 2, a down conversion block 16, an intermediate frequency signal linear amplifier 9, a limiter amplifier 11, an analog demodulator 12, a digital demodulator 13, and a received signal intensity detector 15. The received signal intensity detector 15 outputs received signal intensity information SRSS. The down conversion block 16 comprises mixers 3, 6, local oscillators 4, 7, and a bandpass filter 5.

A root Nyquist bandpass filter 20 is connected to an input terminal of the intermediate frequency signal linear amplifier 9. The received signal intensity information SRSS from the received signal intensity detector 15 is supplied to a synchronizing clock signal generator 17 which applies a synchronizing clock signal SSYC to the digital demodulator 13.

A digital modulated signal that has been received is amplified by the high frequency amplifier 1 and then limited to a certain received frequency band by the bandpass filter 2. The digital modulated signal is thereafter converted into an intermediate frequency signal by the down conversion block 16. The digital modulated intermediate frequency signal from the down conversion block 16 is limited to a frequency band by the root Nyquist bandpass filter 20 with root Nyquist characteristics. Since it is impossible for the root Nyquist bandpass filter 20 to have complete root Nyquist characteristics, the root Nyquist bandpass filter 20 has characteristics approximate to root Nyquist characteristics having an attenuation rate of 1/√2 at a frequency which is 1/2 the symbol rate.

An output signal from the root Nyquist bandpass filter 20 is applied to the intermediate frequency signal linear amplifier 9, which linearly amplifies the applied signal. The amplified signal from the intermediate frequency signal linear amplifier 9 is limited to a certain amplitude and amplified by the limiter amplifier 11. For digital signal demodulation, the received signal intensity information SRSS from the received signal intensity detector 15 is supplied to the synchronizing clock signal generator 17. The synchronizing clock signal SSYC from the synchronizing clock signal generator 17 and the output signal from the limiter amplifier 11 are applied to the digital demodulator 13, which produces a digital demodulated signal.

An analog modulated signal that has been received is processed into an intermediate frequency signal by the same circuit components as the digital modulated signal up to the limiter amplifier 11. The output signal from the limiter amplifier 11 is applied to the analog modulator 12, which produces an analog demodulated signal.

FIG. 3 shows in block form a receiver circuit for receiving both digital and analog modulated signals according to a second embodiment of the present invention. The receiver circuit shown in FIG. 3 differs from the receiver circuit shown in FIG. 2 in that the output signal from the limiter amplifier 11 is applied to a synchronizing clock signal generator 18 which generates a synchronizing clock signal SSYC and supplies it to the digital demodulator 13.

A digital modulated signal that has been received is converted into an intermediate frequency signal which is passed through the root Nyquist bandpass filter 20 and then amplified by the intermediate frequency signal linear amplifier 9, as with the first embodiment. The amplified signal from the intermediate frequency signal linear amplifier 9 is limited to a certain amplitude and amplified by the limiter amplifier 11. The amplified signal from the limiter amplifier 11 is supplied to the synchronizing clock signal generator 18, the digital demodulator 13, and the analog demodulator 12. The digital demodulator 13 demodulates the signal from the limiter amplifier 11 into a digital demodulated signal with the synchronizing clock signal SSYC from the synchronizing clock signal generator 18.

The analog demodulator 12 demodulates the signal from the limiter amplifier 11 into an analog demodulated signal.

Although certain preferred embodiments of the present invention have been shown and described in detail, it should be understood that various changes and modifications may be made therein without departing from the scope of the appended claims.

Claims (6)

What is claimed is:
1. A receiver circuit for receiving both digital and analog modulated signals, comprising:
a frequency converter for converting digital and analog modulated high frequency signals into respective intermediate frequency signals;
a root Nyquist bandpass filter for limiting the intermediate frequency signal from said frequency converter to a frequency band based on root Nyquist characteristics;
an intermediate frequency signal linear amplifier for linearly amplifying the intermediate frequency signal that has passed through said root Nyquist bandpass filter;
a limiter amplifier for limiting to a constant amplitude the intermediate frequency signal from said intermediate frequency signal linear amplifier;
a digital demodulator connected to said limiter amplifier for demodulating the digital modulated intermediate frequency signal from said limiter amplifier; and
an analog demodulator connected to said limiter amplifier parallel to said digital demodulator for demodulating the analog modulated intermediate frequency signal from said limiter amplifier.
2. A receiver circuit according to claim 1 that further comprises a received signal intensity detector for detecting received signal intensity information from the intermediate frequency signal amplified by said intermediate frequency signal linear amplifier.
3. A receiver circuit according to claim 2 that further comprises a first synchronizing clock signal generator for generating a synchronizing clock signal from the received signal intensity information detected by said received signal intensity detector and applying said synchronizing clock signal to said digital demodulator.
4. A receiver circuit according to claim 1 or 2 that further comprises a second synchronizing clock signal generator for generating a synchronizing clock signal from the digital modulated intermediate frequency signal from said limiter amplifier and applying said synchronizing clock signal to said digital demodulator.
5. A receiver circuit according to claim 1 that further comprises a high frequency amplifier for amplifying the digital and analog modulated high frequency signals and applying the amplified high frequency signals to said frequency converter.
6. A receiver circuit according to claim 5 that further comprises a bandpass filter connected between said high frequency amplifier and said frequency converter for limiting an output signal from said high frequency amplifier to a predetermined frequency band.
US08063694 1992-05-20 1993-05-20 Receiver circuit for digital and analog modulated signal Expired - Fee Related US5416802A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP15293192A JP2970226B2 (en) 1992-05-20 1992-05-20 Digital receiver circuitry
JP4-152931 1992-05-20

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US5416802A true US5416802A (en) 1995-05-16

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JP (1) JP2970226B2 (en)
CA (1) CA2096476C (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5724388A (en) * 1994-04-22 1998-03-03 Advantest Corp. Digital signal modulation analysis device
US5768696A (en) * 1995-12-18 1998-06-16 Golden Eagle Electronics Manufactory Ltd. Wireless 900 MHz monitor system
US5809065A (en) * 1996-02-20 1998-09-15 Usa Digital Radio Partners, L.P. Method and apparatus for improving the quality of AM compatible digital broadcast system signals in the presence of distortion
US5974098A (en) * 1994-09-12 1999-10-26 Nec Corporation Received signal detector for digital demodulator
US6005640A (en) * 1996-09-27 1999-12-21 Sarnoff Corporation Multiple modulation format television signal receiver system
US6122529A (en) * 1998-03-17 2000-09-19 Transcept, Inc. Simulcast with hierarchical cell structure overlay
US6233443B1 (en) 1995-09-12 2001-05-15 Transcept, Inc. Apparatus and method for reducing co-channel radio interference
US6301240B1 (en) 1998-02-19 2001-10-09 Transcept, Inc. Centrally located equipment for wireless telephone system
EP1160978A1 (en) * 2000-05-29 2001-12-05 Sony International (Europe) GmbH Digital filter
US6374124B1 (en) 1997-12-24 2002-04-16 Transcept, Inc. Dynamic reallocation of transceivers used to interconnect wireless telephones to a broadband network
US6657678B1 (en) * 1994-02-14 2003-12-02 Hitachi, Ltd. Digital broadcasting receiver
US20050201494A1 (en) * 2004-03-15 2005-09-15 Samsung Electronics Co., Ltd. Apparatus and method for digital down-conversion in a multi-mode wireless terminal
US20050201501A1 (en) * 2004-03-15 2005-09-15 Samsung Electronics Co., Ltd. Apparatus and method for digital down-conversion in a multi-mode wireless terminal

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4355401A (en) * 1979-09-28 1982-10-19 Nippon Electric Co., Ltd. Radio transmitter/receiver for digital and analog communications system
US4748685A (en) * 1986-10-10 1988-05-31 Motorola, Inc. Mobile radio communications system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4355401A (en) * 1979-09-28 1982-10-19 Nippon Electric Co., Ltd. Radio transmitter/receiver for digital and analog communications system
US4748685A (en) * 1986-10-10 1988-05-31 Motorola, Inc. Mobile radio communications system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
White Series No. 105, Digital Modulation and Demodulation Technology for Mobile Communication, Published by TRIKEPS, Ltd. Mar. 14, 1990. *

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6657678B1 (en) * 1994-02-14 2003-12-02 Hitachi, Ltd. Digital broadcasting receiver
US5724388A (en) * 1994-04-22 1998-03-03 Advantest Corp. Digital signal modulation analysis device
US5974098A (en) * 1994-09-12 1999-10-26 Nec Corporation Received signal detector for digital demodulator
US6233443B1 (en) 1995-09-12 2001-05-15 Transcept, Inc. Apparatus and method for reducing co-channel radio interference
US5768696A (en) * 1995-12-18 1998-06-16 Golden Eagle Electronics Manufactory Ltd. Wireless 900 MHz monitor system
US5809065A (en) * 1996-02-20 1998-09-15 Usa Digital Radio Partners, L.P. Method and apparatus for improving the quality of AM compatible digital broadcast system signals in the presence of distortion
US6005640A (en) * 1996-09-27 1999-12-21 Sarnoff Corporation Multiple modulation format television signal receiver system
US6374124B1 (en) 1997-12-24 2002-04-16 Transcept, Inc. Dynamic reallocation of transceivers used to interconnect wireless telephones to a broadband network
US6301240B1 (en) 1998-02-19 2001-10-09 Transcept, Inc. Centrally located equipment for wireless telephone system
US6122529A (en) * 1998-03-17 2000-09-19 Transcept, Inc. Simulcast with hierarchical cell structure overlay
EP1160978A1 (en) * 2000-05-29 2001-12-05 Sony International (Europe) GmbH Digital filter
US20050201494A1 (en) * 2004-03-15 2005-09-15 Samsung Electronics Co., Ltd. Apparatus and method for digital down-conversion in a multi-mode wireless terminal
US20050201501A1 (en) * 2004-03-15 2005-09-15 Samsung Electronics Co., Ltd. Apparatus and method for digital down-conversion in a multi-mode wireless terminal
US7792228B2 (en) * 2004-03-15 2010-09-07 Samsung Electronics Co., Ltd. Apparatus and method for digital down-conversion in a multi-mode wireless terminal

Also Published As

Publication number Publication date Type
CA2096476C (en) 1997-05-13 grant
CA2096476A1 (en) 1993-11-21 application
JP2970226B2 (en) 1999-11-02 grant
JPH05327793A (en) 1993-12-10 application

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