US5276804A - Display control system with memory access timing based on display mode - Google Patents

Display control system with memory access timing based on display mode Download PDF

Info

Publication number
US5276804A
US5276804A US07/833,644 US83364492A US5276804A US 5276804 A US5276804 A US 5276804A US 83364492 A US83364492 A US 83364492A US 5276804 A US5276804 A US 5276804A
Authority
US
United States
Prior art keywords
display
character
main system
display mode
pattern data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US07/833,644
Inventor
Yukio Ishiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63104756A external-priority patent/JPH01274194A/en
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to US07/833,644 priority Critical patent/US5276804A/en
Application granted granted Critical
Publication of US5276804A publication Critical patent/US5276804A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/40—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which both a pattern determined by character code and another pattern are displayed simultaneously, or either pattern is displayed selectively, e.g. with character code memory and APA, i.e. all-points-addressable, memory

Definitions

  • This invention relates to a display control system, which permits access to a memory for display data generation by a main system (for instance an external CPU or a personal computer system) according to a display mode command signal.
  • a main system for instance an external CPU or a personal computer system
  • FIG. 4 is a block diagram showing a prior art display control system.
  • reference numeral 1 designates a display controller (CRTC), 2 a display data memory (VRAM) as first memory means for storing display data, 3 and 4 display data hold circuits (F/F) for temporarily holding display data read out from the VRAM 2, 5 a display data generation memory (CG) as second memory means for storing character pattern data, 6 an image data generation circuit (DGL), 7 a display unit (CRT), 8 a main system side character code hold circuit (F/F), which serves to hold character code data from the main system side and includes a counter for counting bytes of character pattern data corresponding to one character code, 9 a selector for selectively providing an output of either F/F 3 or F/F 8 to the CG 5, 10 a display data generation memory access circuit (DCNT) for permitting access of the CG 5 from the main system side and including an edge trigger flip-flop (F/F) 10a as character pattern data holding means, 11 display data memory access circuit (VRIF),
  • FIG. 5 shows the image data generation circuit (DGL) 6 in detail.
  • DGL image data generation circuit
  • designated at 6a is a parallel-to-serial converter for graphics image
  • 6b an attribute data hold circuit
  • 6c a parallel-to-serial converter for character pattern
  • 6d a selector for character image
  • 6e a border color register
  • 6f an image data selector.
  • FIG. 6 shows the display data generation memory access circuit (DCNT) 10 in detail.
  • DCNT display data generation memory access circuit
  • the CRTC 1 provides a signal for controlling the display unit and a control signal for reading out display data of the VRAM 2 and timing signals to the DGL 6 and DCNT 10. From the main system, display data is supplied through the VRIF 11 to the VRAM 2. The CRTC 1 accesses the VRAM 2 and reads out data therefrom, the read-out data being temporarily held in the hold circuits F/F 3 and F/F 4. The subsequent operation is determined depending on display modes. As the display modes, there is a character display mode and a usual graphics display mode other than the character display mode. In the character display mode, character code data is held in the F/F 3, and attribute data in F/F 4.
  • the selector 9 is adapted such that it usually selects an output of the F/F 3.
  • the character code data from the F/F 3 is supplied through the selector 9 to the CG 5 which then provides corresponding character pattern data.
  • This character pattern data and the attribute data from the F/F 4 are supplied to the DGL 6 which produces from these data image data to be provided to the CRT 7.
  • the outputs of the F/Fs 3 and 4 are directly supplied to the DGL 6 which then produces image data supplied to the CRT 7.
  • the DGL 6 receives a signal from the display mode detection circuit 13 to effect switching between character image data and graphics image data.
  • the VRAM 2 contains graphic display data. This data is temporarily held in the F/Fs 3 and 4 and then supplied to the parallel-to-serial converter 6a for graphics image. As a result, graphics image data is generated and supplied to the image data selector 6f.
  • the VRAM 2 contains character display data, and,-as noted before, character code data is held in the F/F 3 and attribute data in the F/F 4. With the output of the F/F 3 the CG 5 is accessed through the selector 9, and read-out character pattern data is held in the parallel-to-serial converter 6c for character pattern.
  • the attribute data from the F/F 4 is held in the attribute data hold circuit 6b and supplied to the selector 6d for character image.
  • character color data and background color data in the attribute data are selected according to the output of the parallel-to-serial converter 6c, then the selected data is supplied to the video data selector 6f.
  • the border color register 6e contains data for determining a display color of border area.
  • the face area 7a on the screen of the CRT 7 consists of an intrinsic display area 7b and a border area 7c surrounding the display area 7b.
  • the CRTC 1 supplies a signal for selecting either the display area 7b or the border area 7c to switch the image data selector 6f.
  • a signal representing a display mode is supplied from the display mode detection circuit 13, and the video data selector 6f selects either graphics image data or character image data to be provided to the display area 7b.
  • FIG. 8 shows a timing signal DE which is supplied from the CRTC 1 to the timing detection circuit 10b in the DCNT 10.
  • Either access mode is set in the access mode detection circuit 12.
  • the F/F 8 supplies data to the CG 5, whereby corresponding character pattern data is provided.
  • This data is taken in the DCNT 10 and transmitted to the main system under control of a timing signal form the CRTC 1.
  • the main system can transmit character pattern data to the CG 5.
  • the character pattern data is transmitted to the CG 5 by a timing signal of the CRTC1.
  • the CG 5 should receive the character code data from the F/F 3 through the selector 9 for display data generation and supply corresponding character pattern data to the DGL 6.
  • the access mode I access of the main system is allowed only during the non-display period t2.
  • the non-display period t2 is as short as a fraction of the display period t1. Therefore, the access performance is inferior.
  • the selector 9 is switched to the side of the F/F 8 in response to an access from the main system, thus improving the access performance.
  • data of the main system is transmitted to the DGL 6 as well during the display period, thus resulting in disturbance of the display.
  • FIG. 9 shows a timing signal a which is obtained by dividing a character clock from the CRTC 1 into two. This signal is generated in the data take-in timing signal generation circuit 10c.
  • data representing the character display mode is set in the display mode detection circuit 13
  • data representing the access mode II is set in the access mode detection circuit 12. Character code data is written from the main system into the F/F 8.
  • the selector 9 When the data take-in timing generation circuit 10c detects the writing of the character code data in the F/F 8 from the rising of the timing signal ⁇ ,the selector 9 provides the data from the F/F 8 to the CG 5.
  • the CG 5 accordingly provides corresponding character pattern data to the flip-flop 10a.
  • the character pattern data is held in the flip-flop 10a with the falling of the timing signal ⁇ , the held data is then read out by the main system. Meanwhile, with the falling of the timing signal ⁇ a counter in the F/F 8 starts up-counting. Since the character pattern data consists of several bytes per character, after setting of one character code the main system should read out several bytes. These several bytes are set by the counter in the F/F 8.
  • the CG 5 is accessed in the manner as described above.
  • the CG 5 is not directly accessed by graphics image data, so that in the access mode II there is no possibility of disturbance of the display, thus improving the access performance.
  • the timing signal from the CRTC 1 is used as the timing of input of data to the DCNT 10 when reading out the character pattern data after writing of data in the F/F 8 and also as timing of input of data to the CG 5 when writing data.
  • This invention has been intended in order to solve the above problems, and its object is to provide a display control system, in which in a mode other than the character display mode the main system is allowed to make, without any timing restriction, access to second memory means which stores character pattern data.
  • a through latch is provided as character pattern data holding means, and there is provided timing signal generation means for generating a timing signal for the control of the through latch not according to a timing from the display controller but according to an access command from the main system in a mode other than the character display mode.
  • the through latch is controlled depending on a display mode.
  • the character display mode it is controlled according to a timing from the display controller, and in a mode other than the character display mode it is controlled according to an independent timing from the timing signal generation means on the basis of an access command from the main system.
  • access means for permitting access of the second memory means from the main system is perfectly separated from the display timing to permit high speed access from the main system.
  • FIG. 1 is a block diagram showing an embodiment of the invention
  • FIG. 2 is a block diagram showing an essential part of the same embodiment
  • FIG. 3 is a timing chart for explaining the operation of the embodiment
  • FIG. 4 is a block diagram showing a prior art system
  • FIGS. 5 and 6 are block diagrams showing essential parts of the same prior art system
  • FIG. 7 is a view showing the screen structure of a display unit.
  • FIGS. 8 and 9 are timing charts for explaining the operation of the prior art system.
  • FIG. 1 is a block diagram showing the construction of the embodiment. As shown in the FIGURE, a through latch 10d is provided as character pattern data holding means in a display data generation memory access circuit (DCNT) 10. An output of a display mode detection circuit 13 is also supplied to a selector 9. The selector 9 is adapted to select an output of a F/F 8 in a mode other than the character display mode.
  • DCNT display data generation memory access circuit
  • FIG. 2 shows the DCNT 10 in detail.
  • the character pattern data holding means is constituted by the through latch 10d.
  • a data take-in timing signal generation circuit 10e unlike the prior art system, is constructed such that in a mode other than the character display mode it generates and provides a data take-in signal not according to any timing signal from the CRTC 1 but in correspondence to a command signal (for instance I/O read signal) from the main system as shown in FIG. 3.
  • the character pattern data holding means of the DCNT 10 consists of an edge trigger flip-flop (F/F) 10a, so that it is done under control of the CRTC 1 for timing signal generation.
  • the, through latch 10d is provided in lieu of the edge trigger flip-flop 10a.
  • the output signal is changed with the rising edge of the timing signal.
  • the timing signal is "H" an input is directly provided as an output, and data is held with the falling of the timing signal. This function is utilized.
  • both access modes I and II are subject to timing restrictions, and in the access mode II disturbance of the display occurs.
  • the main system can access the CG 5 without timing control of the CRTC 1. More particularly, when the display mode detection circuit 13 recognizes a mode other than the character display mode, the selector 9 selects the F/F 8, and its output is supplied to the CG 5. Further, the timing signal of the through latch 10d in the DCNT 10 is fixed to "H" according to a command from the main system.
  • the through latch 10d serves as a mere gate, and its input is directly provided as an output. This means that the main system is directly connected to the CG 5 and is subject to no timing restriction at all. More particularly, the CG 5 is perfectly separated from the circuit other than that for the image generation, so that it can be freely accessed from the main system like a mere memory.
  • the data take-in timing generation circuit 10e When the graphics display mode is set in the display mode detection circuit 13, the data take-in timing generation circuit 10e is perfectly separated from a display timing detection circuit 10b and the CRTC 1. An access mode detection circuit 12 is ignored irrespective of the access modes I or II is set.
  • the main system first sets character code data in the F/F 8. Then, a command for taking in data of the CG 5 is provided to the data take-in timing generation circuit 10e.
  • the width or duration T of the command (see FIG. 3) is longer than the access time of the CG 5, so that the character pattern data of the CG 5 is supplied to the through latch 10d.
  • the CG 5 data take-in signal from the data take-in timing generation circuit 10e to the through latch 10d is "H", so that the function of holding the through latch 10d is not operated, and only the gate function is provided. More particularly, when a command signal is provided from the main system, the CG 5 data take-in signal from the data take-in timing generation circuit 10e goes to "H” to open the gate of the through latch 10d, so that data is transmitted to the main system. Meanwhile, a counter in the F/F 8 performs up-counting in response to the rising of the command signal, i.e., the falling of the CG 5 data take-in signal.
  • the above embodiment has been concerned with the CG 5, i.e., a memory for display data generation, as second memory means.
  • the invention is also applicable to the case where a display data memory is provided for each display mode.
  • character pattern data holding means is constituted by a through latch, and timing signal generation means is provided, which generates a timing signal to control the through latch not according to a timing from a display controller but on the basis of an access command from a main system in a mode other than the character display mode, so that in a mode other than the character display mode the main system can access a second memory means as a mere memory without any other timing restriction. It is thus possible to enhance the access performance of the second memory means and enhance performance inclusive of the main system.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

A character pattern data holding circuit includes a through latch. In a mode other than a character display mode, a gate of the through latch is opened according to an access command from the main system by making use of a data function of the through latch so that the main system and a second memory are directly connected to each other. In this way, display control timing restrictions are not imposed on the main system and access performance is enhanced.

Description

This application is a continuation, of application Ser. No. 343,048, filed Apr. 25, 1989, now abandoned.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a display control system, which permits access to a memory for display data generation by a main system (for instance an external CPU or a personal computer system) according to a display mode command signal.
2. Description of the Prior Art
FIG. 4 is a block diagram showing a prior art display control system. Referring to the FIGURE, reference numeral 1 designates a display controller (CRTC), 2 a display data memory (VRAM) as first memory means for storing display data, 3 and 4 display data hold circuits (F/F) for temporarily holding display data read out from the VRAM 2, 5 a display data generation memory (CG) as second memory means for storing character pattern data, 6 an image data generation circuit (DGL), 7 a display unit (CRT), 8 a main system side character code hold circuit (F/F), which serves to hold character code data from the main system side and includes a counter for counting bytes of character pattern data corresponding to one character code, 9 a selector for selectively providing an output of either F/F 3 or F/F 8 to the CG 5, 10 a display data generation memory access circuit (DCNT) for permitting access of the CG 5 from the main system side and including an edge trigger flip-flop (F/F) 10a as character pattern data holding means, 11 display data memory access circuit (VRIF), 12 an access mode detection circuit, and 13 a display mode detection circuit.
FIG. 5 shows the image data generation circuit (DGL) 6 in detail. In the FIGURE, designated at 6a is a parallel-to-serial converter for graphics image, 6b an attribute data hold circuit, 6c a parallel-to-serial converter for character pattern, 6d a selector for character image, 6e a border color register, and 6f an image data selector.
FIG. 6 shows the display data generation memory access circuit (DCNT) 10 in detail. In the FIGURE, designated at 10a is the flip-flop for holding the character pattern data noted above, 10b a display data timing detection circuit, and 10c a data take-in timing signal generation circuit.
The operation of the circuit shown in FIG. 4 will now be described. The CRTC 1 provides a signal for controlling the display unit and a control signal for reading out display data of the VRAM 2 and timing signals to the DGL 6 and DCNT 10. From the main system, display data is supplied through the VRIF 11 to the VRAM 2. The CRTC 1 accesses the VRAM 2 and reads out data therefrom, the read-out data being temporarily held in the hold circuits F/F 3 and F/F 4. The subsequent operation is determined depending on display modes. As the display modes, there is a character display mode and a usual graphics display mode other than the character display mode. In the character display mode, character code data is held in the F/F 3, and attribute data in F/F 4. The selector 9 is adapted such that it usually selects an output of the F/F 3. The character code data from the F/F 3 is supplied through the selector 9 to the CG 5 which then provides corresponding character pattern data. This character pattern data and the attribute data from the F/F 4 are supplied to the DGL 6 which produces from these data image data to be provided to the CRT 7. In the case of the graphics display mode, the outputs of the F/Fs 3 and 4 are directly supplied to the DGL 6 which then produces image data supplied to the CRT 7. The DGL 6 receives a signal from the display mode detection circuit 13 to effect switching between character image data and graphics image data.
Referring to FIG. 5, in the graphics display mode the VRAM 2 contains graphic display data. This data is temporarily held in the F/Fs 3 and 4 and then supplied to the parallel-to-serial converter 6a for graphics image. As a result, graphics image data is generated and supplied to the image data selector 6f. In the character display mode, the VRAM 2 contains character display data, and,-as noted before, character code data is held in the F/F 3 and attribute data in the F/F 4. With the output of the F/F 3 the CG 5 is accessed through the selector 9, and read-out character pattern data is held in the parallel-to-serial converter 6c for character pattern. Meanwhile, the attribute data from the F/F 4 is held in the attribute data hold circuit 6b and supplied to the selector 6d for character image. In the selector 6d character color data and background color data in the attribute data are selected according to the output of the parallel-to-serial converter 6c, then the selected data is supplied to the video data selector 6f. The border color register 6e contains data for determining a display color of border area. As shown in FIG. 7, the face area 7a on the screen of the CRT 7 consists of an intrinsic display area 7b and a border area 7c surrounding the display area 7b. The CRTC 1 supplies a signal for selecting either the display area 7b or the border area 7c to switch the image data selector 6f. A signal representing a display mode is supplied from the display mode detection circuit 13, and the video data selector 6f selects either graphics image data or character image data to be provided to the display area 7b.
The operation will now be described in connection with the case when the main system accesses the CG 5. FIG. 8 shows a timing signal DE which is supplied from the CRTC 1 to the timing detection circuit 10b in the DCNT 10. There are two access modes, i.e., an access mode I, in which the main system can access to the CG 5 only during a non-display period t2, and an access mode II, in which the main system can access to the CG 5 at all time, i.e., during either a display period t1 or the non-display period t2. Either access mode is set in the access mode detection circuit 12. In either mode, when character code data is written in the F/F 8 from the main system, the F/F 8 supplies data to the CG 5, whereby corresponding character pattern data is provided. This data is taken in the DCNT 10 and transmitted to the main system under control of a timing signal form the CRTC 1. On the other hand, the main system can transmit character pattern data to the CG 5. When character code data and character pattern data are written from the main system in the F/F 8 and DCNT 10 respectively the character pattern data is transmitted to the CG 5 by a timing signal of the CRTC1. In the character display mode, during the display period the CG 5 should receive the character code data from the F/F 3 through the selector 9 for display data generation and supply corresponding character pattern data to the DGL 6. While there are two different access modes, in the access mode I access of the main system is allowed only during the non-display period t2. The non-display period t2, however, is as short as a fraction of the display period t1. Therefore, the access performance is inferior. In the other access mode II, even during the display period the selector 9 is switched to the side of the F/F 8 in response to an access from the main system, thus improving the access performance. However, in this case data of the main system is transmitted to the DGL 6 as well during the display period, thus resulting in disturbance of the display.
Further detailed description will be given with reference to FIG. 6. The access mode I is the same as the access mode II except for that access is inhibited during the display period. For this reason, the access mode II will be described in detail. FIG. 9 shows a timing signal a which is obtained by dividing a character clock from the CRTC 1 into two. This signal is generated in the data take-in timing signal generation circuit 10c. First, data representing the character display mode is set in the display mode detection circuit 13, and data representing the access mode II is set in the access mode detection circuit 12. Character code data is written from the main system into the F/F 8. When the data take-in timing generation circuit 10c detects the writing of the character code data in the F/F 8 from the rising of the timing signal α,the selector 9 provides the data from the F/F 8 to the CG 5. The CG 5 accordingly provides corresponding character pattern data to the flip-flop 10a. The character pattern data is held in the flip-flop 10a with the falling of the timing signal α, the held data is then read out by the main system. Meanwhile, with the falling of the timing signal α a counter in the F/F 8 starts up-counting. Since the character pattern data consists of several bytes per character, after setting of one character code the main system should read out several bytes. These several bytes are set by the counter in the F/F 8. Unless the main system reads out data from the flip-flop 10a, new clock for holding of data in the CG 5 is not provided from the data take-in timing generation circuit 10c to the flip-flop 10a. Thus, data is preserved in the flip-flop 10a, and the data is normally transferred to the main system. When the data is read out from the flip-flop 10a, the main system provides a command (i.e., I/O read signal).
In the case of the graphics display mode, the CG 5 is accessed in the manner as described above. In the case of the graphics display mode, the CG 5 is not directly accessed by graphics image data, so that in the access mode II there is no possibility of disturbance of the display, thus improving the access performance. Again in this case, the timing signal from the CRTC 1 is used as the timing of input of data to the DCNT 10 when reading out the character pattern data after writing of data in the F/F 8 and also as timing of input of data to the CG 5 when writing data.
With the above construction of the prior art display control system, even in the case other than the character display mode, in which the CG 5 is unnecessary, the access to the CG 5 by the main system for reading and writing data is done under control of the timing signal from the CRTC 1, so that it is subject to that timing restriction, thus correspondingly limiting the access performance.
SUMMARY OF THE INVENTION
This invention has been intended in order to solve the above problems, and its object is to provide a display control system, in which in a mode other than the character display mode the main system is allowed to make, without any timing restriction, access to second memory means which stores character pattern data. In the display control system according to the invention, a through latch is provided as character pattern data holding means, and there is provided timing signal generation means for generating a timing signal for the control of the through latch not according to a timing from the display controller but according to an access command from the main system in a mode other than the character display mode. The through latch is controlled depending on a display mode. More specifically, in the character display mode it is controlled according to a timing from the display controller, and in a mode other than the character display mode it is controlled according to an independent timing from the timing signal generation means on the basis of an access command from the main system. In a mode other than the character display mode, access means for permitting access of the second memory means from the main system is perfectly separated from the display timing to permit high speed access from the main system.
The above and other objects, features and advantages will become more apparent from the following description when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram showing an embodiment of the invention;
FIG. 2 is a block diagram showing an essential part of the same embodiment;
FIG. 3 is a timing chart for explaining the operation of the embodiment;
FIG. 4 is a block diagram showing a prior art system;
FIGS. 5 and 6 are block diagrams showing essential parts of the same prior art system;
FIG. 7 is a view showing the screen structure of a display unit; and
FIGS. 8 and 9 are timing charts for explaining the operation of the prior art system.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Now, an embodiment of the invention will be described with reference to the drawings. Parts like or corresponding to those in the prior art system are designated by like reference numerals with omission of the description.
FIG. 1 is a block diagram showing the construction of the embodiment. As shown in the FIGURE, a through latch 10d is provided as character pattern data holding means in a display data generation memory access circuit (DCNT) 10. An output of a display mode detection circuit 13 is also supplied to a selector 9. The selector 9 is adapted to select an output of a F/F 8 in a mode other than the character display mode.
FIG. 2 shows the DCNT 10 in detail. In the DCNT 10, the character pattern data holding means is constituted by the through latch 10d. A data take-in timing signal generation circuit 10e, unlike the prior art system, is constructed such that in a mode other than the character display mode it generates and provides a data take-in signal not according to any timing signal from the CRTC 1 but in correspondence to a command signal (for instance I/O read signal) from the main system as shown in FIG. 3.
The operation will now be described.
With the prior art system, when the main system accesses a CG 5, transfer of data requires a data take-in timing signal at all times since the character pattern data holding means of the DCNT 10 consists of an edge trigger flip-flop (F/F) 10a, so that it is done under control of the CRTC 1 for timing signal generation. In contrast, according to the invention the, through latch 10d is provided in lieu of the edge trigger flip-flop 10a. In the case of the edge trigger flip-flop 10a, the output signal is changed with the rising edge of the timing signal. In the case of the through latch 10d, when the timing signal is "H" an input is directly provided as an output, and data is held with the falling of the timing signal. This function is utilized.
In the character display mode, as in the prior art, both access modes I and II are subject to timing restrictions, and in the access mode II disturbance of the display occurs. However, in a mode other than the character display mode, i.e., in a mode which does not require the CG 5 for the image data generation such as a graphics display mode, the main system can access the CG 5 without timing control of the CRTC 1. More particularly, when the display mode detection circuit 13 recognizes a mode other than the character display mode, the selector 9 selects the F/F 8, and its output is supplied to the CG 5. Further, the timing signal of the through latch 10d in the DCNT 10 is fixed to "H" according to a command from the main system. The through latch 10d serves as a mere gate, and its input is directly provided as an output. This means that the main system is directly connected to the CG 5 and is subject to no timing restriction at all. More particularly, the CG 5 is perfectly separated from the circuit other than that for the image generation, so that it can be freely accessed from the main system like a mere memory.
A further detailed description will now be given with reference to FIG. 2. What takes place in the character display mode is the same as in the prior art system, so that the description will be given in conjunction with other mode, i.e., graphics display mode.
When the graphics display mode is set in the display mode detection circuit 13, the data take-in timing generation circuit 10e is perfectly separated from a display timing detection circuit 10b and the CRTC 1. An access mode detection circuit 12 is ignored irrespective of the access modes I or II is set. The main system first sets character code data in the F/F 8. Then, a command for taking in data of the CG 5 is provided to the data take-in timing generation circuit 10e. The width or duration T of the command (see FIG. 3) is longer than the access time of the CG 5, so that the character pattern data of the CG 5 is supplied to the through latch 10d. In this mode, the CG 5 data take-in signal from the data take-in timing generation circuit 10e to the through latch 10d is "H", so that the function of holding the through latch 10d is not operated, and only the gate function is provided. More particularly, when a command signal is provided from the main system, the CG 5 data take-in signal from the data take-in timing generation circuit 10e goes to "H" to open the gate of the through latch 10d, so that data is transmitted to the main system. Meanwhile, a counter in the F/F 8 performs up-counting in response to the rising of the command signal, i.e., the falling of the CG 5 data take-in signal.
It will be seen that the access to the CG 5 from the main system, which has been effected under control of the timing of the display control system in the prior art, can be effected according to the invention without any timing restriction as if the CG 5 is an ordinary memory.
The above embodiment has been concerned with the CG 5, i.e., a memory for display data generation, as second memory means. However, the invention is also applicable to the case where a display data memory is provided for each display mode.
As has been described in the foregoing, according to the invention character pattern data holding means is constituted by a through latch, and timing signal generation means is provided, which generates a timing signal to control the through latch not according to a timing from a display controller but on the basis of an access command from a main system in a mode other than the character display mode, so that in a mode other than the character display mode the main system can access a second memory means as a mere memory without any other timing restriction. It is thus possible to enhance the access performance of the second memory means and enhance performance inclusive of the main system.

Claims (3)

What is claimed is:
1. A display control system responsive to a main system, for controlling operation of a video display system, the video display system having at least a character display mode for causing the video display system to display characters selected from a predetermined set of characters defined by character pattern data and a non-character display mode for causing the video display system to display images corresponding to graphical data, the main system providing at least main system timing signals and character pattern data, the display control system comprising:
a memory for storing the character pattern data;
means connected to the main system for detecting which one of character display mode and non-character display mode the video display system is in;
a display controller connected to the main system for receiving the main system timing signals and the character pattern data from the main system and including
means for generating display control timing signals, and
transfer means having means connected to the main system for receiving the character pattern data from the main system, means connected to the means for generating display timing control signals for receiving display timing control signals, means connected to the main system for receiving main system timing signals, means connected to the means for detecting for receiving therefrom an indication of which one of character display mode and non-character display mode the video display system is in, and means connected to the means for receiving an indication for providing received character pattern data to the memory, whereby said transfer means transfers the character pattern data from the main system to the memory in accordance with the display control timing signals when the video display system is in the character display mode and in accordance with the main system timing signals when the video display system is in the non-character display mode.
2. A display control system as recited in claim 1, wherein the means for transferring further comprises:
means for generating transfer timing signals, responsive to the means for detecting, the main system timing signals and the display control timing signals; and
means for receiving the character pattern data from the main system and for transferring the character pattern data to the memory in response to the transfer timing signals.
3. A display control system responsive to a main system, for controlling operation of a video display system, the video display system having at least a character display mode for causing the video display system to display characters selected from a predetermined set of characters defined by character pattern data and a non-character display mode, for causing the video display system to display images corresponding to graphical data, the main system providing main system timing signals and character pattern data, the display control system comprising:
a memory for storing the character pattern data;
means connected to the main system for detecting which one of character display mode and non-character display mode the video display system is in;
a display controller for receiving the main system timing signals and the character pattern data from the main system and including
a through latch,
means for generating display control timing signals,
means connected to the means for detecting which one of character display mode and non-character display mode the video display system is in, to the means for generating and to the main system, for controlling through latch timing by generating a through latch timing control signal in accordance with the display control timing signals when the video display system is in the character display mode and in accordance with the main system timing signals when the video display system is in the non-character display
the through latch having means connected to the main system for receiving the character pattern data from the main system, means connected to the means for controlling through latch timing receiving the through latch timing control signal, and means connected thereto and responsive thereto for providing received character pattern data to the memory, whereby said through latch transfers the character pattern data form the main system to the memory in accordance with the display control timing signals when the video display system is in the character display mode and in accordance with the main system timing signals when the video display system is in the non-character display mode.
US07/833,644 1988-04-27 1992-02-10 Display control system with memory access timing based on display mode Expired - Fee Related US5276804A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US07/833,644 US5276804A (en) 1988-04-27 1992-02-10 Display control system with memory access timing based on display mode

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP63104756A JPH01274194A (en) 1988-04-27 1988-04-27 Display controller
JP63-104756 1988-04-27
US34304889A 1989-04-25 1989-04-25
US07/833,644 US5276804A (en) 1988-04-27 1992-02-10 Display control system with memory access timing based on display mode

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US34304889A Continuation 1988-04-27 1989-04-25

Publications (1)

Publication Number Publication Date
US5276804A true US5276804A (en) 1994-01-04

Family

ID=27310313

Family Applications (1)

Application Number Title Priority Date Filing Date
US07/833,644 Expired - Fee Related US5276804A (en) 1988-04-27 1992-02-10 Display control system with memory access timing based on display mode

Country Status (1)

Country Link
US (1) US5276804A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6044420A (en) * 1997-02-03 2000-03-28 Fuji Xerox Co., Ltd. Tacit viewing system, method and medium for representing peripheral data related to focused data with timing of representation determined by a representation timing determining element

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4180805A (en) * 1977-04-06 1979-12-25 Texas Instruments Incorporated System for displaying character and graphic information on a color video display with unique multiple memory arrangement
US4511965A (en) * 1983-03-21 1985-04-16 Zenith Electronics Corporation Video ram accessing system
US4595996A (en) * 1983-04-25 1986-06-17 Sperry Corporation Programmable video display character control circuit using multi-purpose RAM for display attributes, character generator, and refresh memory
US4622547A (en) * 1981-07-07 1986-11-11 Sony Corporation Memory access control apparatus
US4646077A (en) * 1984-01-16 1987-02-24 Texas Instruments Incorporated Video display controller system with attribute latch
US4646261A (en) * 1983-09-27 1987-02-24 Motorola Computer Systems, Inc. Local video controller with video memory update detection scanner
US4660155A (en) * 1984-07-23 1987-04-21 Texas Instruments Incorported Single chip video system with separate clocks for memory controller, CRT controller
US4663619A (en) * 1985-04-08 1987-05-05 Honeywell Inc. Memory access modes for a video display generator
US4686521A (en) * 1984-03-07 1987-08-11 International Business Machines Corporation Display apparatus with mixed alphanumeric and graphic image
US4694392A (en) * 1983-04-27 1987-09-15 Ballard Jerry L Video display control
US4695967A (en) * 1984-03-09 1987-09-22 Daikin Industries, Ltd. High speed memory access circuit of CRT display unit
US4723226A (en) * 1982-09-29 1988-02-02 Texas Instruments Incorporated Video display system using serial/parallel access memories
US4755814A (en) * 1986-02-21 1988-07-05 Prime Computer, Inc. Attribute control method and apparatus
US4782462A (en) * 1985-12-30 1988-11-01 Signetics Corporation Raster scan video controller with programmable prioritized sharing of display memory between update and display processes and programmable memory access termination
US4789963A (en) * 1983-09-21 1988-12-06 Fujitsu Limited Display control apparatus for controlling to write image data to a plurality of memory planes
US4815033A (en) * 1985-12-10 1989-03-21 Advanced Micro Devices, Inc. Method and apparatus for accessing a color palette synchronously during refreshing of a monitor and asynchronously during updating of the palette

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4180805A (en) * 1977-04-06 1979-12-25 Texas Instruments Incorporated System for displaying character and graphic information on a color video display with unique multiple memory arrangement
US4622547A (en) * 1981-07-07 1986-11-11 Sony Corporation Memory access control apparatus
US4723226A (en) * 1982-09-29 1988-02-02 Texas Instruments Incorporated Video display system using serial/parallel access memories
US4511965A (en) * 1983-03-21 1985-04-16 Zenith Electronics Corporation Video ram accessing system
US4595996A (en) * 1983-04-25 1986-06-17 Sperry Corporation Programmable video display character control circuit using multi-purpose RAM for display attributes, character generator, and refresh memory
US4694392A (en) * 1983-04-27 1987-09-15 Ballard Jerry L Video display control
US4789963A (en) * 1983-09-21 1988-12-06 Fujitsu Limited Display control apparatus for controlling to write image data to a plurality of memory planes
US4646261A (en) * 1983-09-27 1987-02-24 Motorola Computer Systems, Inc. Local video controller with video memory update detection scanner
US4646077A (en) * 1984-01-16 1987-02-24 Texas Instruments Incorporated Video display controller system with attribute latch
US4686521A (en) * 1984-03-07 1987-08-11 International Business Machines Corporation Display apparatus with mixed alphanumeric and graphic image
US4695967A (en) * 1984-03-09 1987-09-22 Daikin Industries, Ltd. High speed memory access circuit of CRT display unit
US4660155A (en) * 1984-07-23 1987-04-21 Texas Instruments Incorported Single chip video system with separate clocks for memory controller, CRT controller
US4663619A (en) * 1985-04-08 1987-05-05 Honeywell Inc. Memory access modes for a video display generator
US4815033A (en) * 1985-12-10 1989-03-21 Advanced Micro Devices, Inc. Method and apparatus for accessing a color palette synchronously during refreshing of a monitor and asynchronously during updating of the palette
US4782462A (en) * 1985-12-30 1988-11-01 Signetics Corporation Raster scan video controller with programmable prioritized sharing of display memory between update and display processes and programmable memory access termination
US4755814A (en) * 1986-02-21 1988-07-05 Prime Computer, Inc. Attribute control method and apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6044420A (en) * 1997-02-03 2000-03-28 Fuji Xerox Co., Ltd. Tacit viewing system, method and medium for representing peripheral data related to focused data with timing of representation determined by a representation timing determining element

Similar Documents

Publication Publication Date Title
KR100221028B1 (en) Graphic accelerator and memory-prefetching method of it
EP0473391A2 (en) Display of scrolling background images composed of characters
KR960009655A (en) Bit mapping on-screen display device for television receivers
US4802118A (en) Computer memory refresh circuit
US4368461A (en) Digital data processing device
KR100196686B1 (en) Apparatus for fast copy between frame buffers in a double buffered output display system
US4323891A (en) Cursor display control system for a raster scan type display system
US5276804A (en) Display control system with memory access timing based on display mode
US4924432A (en) Display information processing apparatus
KR970003090B1 (en) Control device for recording display data
JPH075870A (en) Display control system
KR920008958B1 (en) Display control apparatus
US4777484A (en) Display control device
JPH0683289A (en) Display control device
EP0420291B1 (en) Display control device
KR970000273B1 (en) Apparatus for processing korean alphabet on p.c.
JPS5893097A (en) Color switching circuit
JPS62113193A (en) Memory circuit
KR0152347B1 (en) Data access method of video ram
JP2595243Y2 (en) Microcomputer
KR920005294B1 (en) Chip enable signal control circuit of dual port memory device
JPH0427571B2 (en)
KR900005589B1 (en) Interfacing circuits for lcd displayer
JPS61223787A (en) Document generator
JPS6321211B2 (en)

Legal Events

Date Code Title Description
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
FP Lapsed due to failure to pay maintenance fee

Effective date: 19980107

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362