US5214703A - Device for the conversion of a digital block and use of same - Google Patents

Device for the conversion of a digital block and use of same Download PDF

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US5214703A
US5214703A US07/781,235 US78123592A US5214703A US 5214703 A US5214703 A US 5214703A US 78123592 A US78123592 A US 78123592A US 5214703 A US5214703 A US 5214703A
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Prior art keywords
block
output
output block
operation unit
subblock
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James L. Massey
Xuejia Lai
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Nagravision SARL
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Ascom Tech AG
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/24—Key scheduling, i.e. generating round keys or sub-keys for block encryption
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
    • Y04S40/20—Information technology specific aspects, e.g. CAD, simulation, modelling, system security

Definitions

  • the invention is directed to a device for the block-by-block conversion of a first digital block into a second digital block using at least one freely selectable control block, each of the blocks having an equal number of digits.
  • DES Data Encryption Standard
  • NSS National Bureau of Standards
  • Every plaintext block has a length of 64 bits, as does the ciphertext block.
  • the transmission of the ciphertext block is effected via a public network.
  • This kind of block encryption will make use of all known encryption techniques of confusion, diffusion, etc. and, above all, will use a longer key providing first input means for receiving at least two initial subblocks, wherein the initial digital block is subdivided to form the initial subblocks. Each of the initial subblocks have m digits.
  • a second input means is provided for receiving at least two control blocks, each control block also having m digits.
  • Logic means perform serial operations of at least two different types upon the initial subblocks and the control blocks.
  • the logic means include at least four operation units, each having first and second inputs for receiving blocks to be operated upon and an output for sending an output block resulting from the logical operation performed.
  • the blocks operated upon and the output block each have m digits.
  • the blocks operated upon by the operation units include the initial subblocks, the control blocks, and the output blocks.
  • the majority of the operation units are arranged so that the operation unit which operates upon the output block of a previous operation unit performs an operation different from that of the previous operation unit.
  • the operation units perform the operations selected from and and .
  • Output means are provided for transmitting at least two final subblocks, the final subblocks forming the assigned final digital block, wherein the final subblocks are converted blocks which correspond to the initial subblocks.
  • FIG. 1 shows a basic block wiring diagram of a device for the transmission of data in encrypted form
  • FIG. 2 shows a block wiring diagram of an encrypter
  • FIG. 3 shows a block wiring diagram of a primary encryption logic
  • FIG. 4 shows a truth table of operation units of a first kind
  • FIG. 5 shows a truth table of operation units of a second kind
  • FIG. 6 shows a block wiring diagram of an extended encryption logic
  • FIG. 7 shows a truth table of operation units of a third kind
  • FIG. 8 shows a block wiring diagram of a supplementary encryption logic
  • FIG. 9 shows a block wiring diagram of an encryption stage
  • FIG. 10 shows a table of key subblocks and decryption subblocks
  • FIG. 11 shows a block wiring diagram of a second supplementary encryption logic
  • FIG. 12 shows a block wiring diagram of a second encryption stage
  • FIG. 13 shows a block wiring diagram of a second encrypter
  • FIG. 14 shows a second table of key subblocks and decryption subblocks.
  • FIG. 1 shows a basic block wiring diagram of a device for the transmission of data in encrypted form.
  • the data (plaintext X) to be transmitted originate in a message source 11, e.g. a computer. These data are encrypted in an encrypter 12 and transmitted as ciphertext Y on a public network transmission line 13.
  • the ciphertext Y reaches a decrypter 14 on the receiver side which feeds it to a destination 15, e.g. a second computer, in decrypted form.
  • the encrypter 12 and the decrypter 14 use a secret key block Z which is provided by means f a key source 16 and supplied via secure channel 17 to the two units 12, 14.
  • This channel 17 is e.g. a courier with sealed cover.
  • the ciphertext Y on the transmission line 13 is always exposed to the risk that an enemy cryptanalyst 19 will also read this text Y and attempt to obtain the assigned plaintext X or the key block Z (The results of these attempts are designated X and Z).
  • the cipher should be resistant to these attempts in principle, at least for a sufficient length of time.
  • FIG. 2 shows a block wiring diagram of the encrypter 12 in the case of a step-by-step block encryption.
  • the plaintext X to be encrypted arrives continuously from the message source 11 and reaches an input unit 21, e.g. a series/parallel converter in the case of a serial bit stream.
  • These plaintext subblocks of the respective plaintext blocks X reach a first encryption stage 61.1 via first inputs 25 to 28, each consisting of sixteen parallel lines.
  • the subblocks X 1 to X 4 are grouped together with six different control blocks by means of suitable logical functions.
  • the (general) control blocks are (special) key subblocks Z 1 to Z 6 , and during the decryption process they are decryption subblocks U 1 to U 6 , which are derived from the key block Z. This will be discussed in more detail later.
  • the encryption process is described primarily in the following, for which reason the term key subblock is preferred.
  • the key subblocks Z 1 to Z 6 are connected to second inputs 29, 30, 32, 33, 49, 52 of the first encryption stage 61.1. They, as well as additional key subblocks Z 7 to Z 52 , are delivered by a key subblock generation unit 63.
  • the method for obtaining the key subblocks Z 1 to Z 8 from the key block Z consists in that the latter is divided into eight identical parts of 16 bits length each.
  • the 128 bits of the key block Z are then cyclically shifted (cyclically exchanged) by 25 bits in a uniform direction, e.g. to the left, and the new sequence of 128 bits which is thus formed is, in turn, divided into eight identical parts for forming the key subblocks Z 9 to Z 16 , and so forth, until the formation of Z 52 .
  • Every key subblock Z 1 to Z 52 accordingly has a (second) length m of 16 bits, is derived in an unequivocal manner from the key block Z and is generally distinguished from every other key subblock.
  • the key subblocks Z 1 to Z 6 are connected to the aforementioned six second inputs 29, 30, 32, 33, 49, 52 of the first encryption stage 61.1.
  • the first intersubblocks W 11 to W 14 are connected to the connections or inputs 35 to 38 (identical to the outputs of the preceding stage 61.1) of a second encryption stage 61.2 for the second encryption step.
  • This encryption stage 61.2 is constructed so as to be identical to the first encryption stage 61.1.
  • the described key subblocks Z 7 to Z 12 are connected to their six second key inputs, and the second intersubblocks W 21 , W 22 , W 23 , W 24 or the second interblock W 2 , in its entirety, appear at their outputs.
  • the second intersubblocks W 21 to W 24 are connected to a third encryption stage, not shown, for the third encryption step; the third intersubblocks W 31 to W 34 are connected to a fourth encryption stage, etc. up to a ninth encryption stage 69 which is different from the preceding stages and comprises four second inputs 129, 130, 132, 133.
  • This ciphertext block Y is converted in an output unit 79, e.g. a parallel/series converter, in such a way that it can be transmitted on the transmission line 13.
  • the encryption process is accordingly effected in nine successive encryption stages 61.1, 61.2, 69, the first eight of which are identical.
  • the total of fifty-two aforementioned different key subblocks Z 1 to Z 52 serve as a key.
  • the encryption unit 60 necessary for the encryption process X ⁇ Y is indicated in a dashed line in FIG. 2.
  • the encryption stages 61.1, 61.2, 69 can be realized in various ways.
  • a so-called software implementation in which one or more processors work according to a predetermined program.
  • each input e.g. the first inputs 25 to 28
  • a hardware implementation can also be provided in which the logical function elements are in the form of independent circuit units. The latter are then either constructed from discrete chip elements or preferably from several largescale integration modules (very large scale integration VLSI).
  • VLSI very large scale integration
  • all lines of all inputs are preferably processed in parallel.
  • a partial series procedure is also possible in this case in that e.g. the different inputs (e.g. 25 to 28) are serially connected to partial central circuit units via multiplexers.
  • the hardware implementation has the advantage over the software implementation that it can work substantially faster, specifically up to clock frequencies of approximately 100 Mbits/s and more. For this reason and for purposes of description, the hardware implementation for the encryption stages 61.1, 61.2, 69 is emphasized in the following.
  • FIG. 3 shows the block wiring diagram of a primary encryption logic 40.
  • This logic comprises four operation units 41 to 44 of two different kinds which are connected with one another by means of three connections 45 to 47, the last (47) of which simultaneously forms an output of the logic 40.
  • Every operation unit 41 to 44 has two inputs and an output. Every input and output is constructed as a 16-bit parallel input or output, to which a 16-bit block is connected in a bit-parallel manner.
  • the operation units 41 to 44 are constructed for the logical joining of two input blocks E 1 , E 2 , in each instance, and for forming an assigned output block A of 16 bits.
  • the operation units are connected one after the other in four stages, wherein the two kinds of units 41 to 44 alternate.
  • the operation units of the first kind i.e. the units 42 and 44, have the following characteristics: these units interpret every input block E 1 , E 2 as an integer in binary representation, wherein this number belongs to the number set or set ⁇ 0, 1, 2, . . . , (2 m -1) ⁇ (the number m (second length) is preferably the number 16, but can also be 4 or 8).
  • the units 42, 44 then form the sum modulo 2 m from the input blocks E 1 , E 2 and deliver a corresponding output block A.
  • the operation units 42, 44 of the first kind are accordingly adder modulo 2 m .
  • the two input blocks E 1 , E 2 and the output block A are delivered, respectively, as a number in binary and decimal representation.
  • the respective output block A is then the product modulo (2 m +1) of the input blocks E 1 , E 2 .
  • the units 41, 43 are accordingly multiplier modulo (2 m +1).
  • the primary encryption logic 40 effects a very good diffusion, since each of its two output blocks a 1 , a 2 depends on the two input blocks e 1 , e 2 and on the two key subblocks Z 5 , Z 6 , that is on the values at all inputs. It can be proved that the quantity of four operations is a minimum for meeting the object of diffusion. The aforementioned use of operation units of different kinds serves to produce the necessary confusion.
  • FIG. 6 shows the block wiring diagram of an extended encryption logic 140.
  • This encryption logic comprises four first inputs 125 to 128 for four input blocks e 5 to e 8 to be encrypted in a parallel manner, four outputs 35 to 38 for delivering four output blocks a 5 to a 8 , and two second inputs 49, 52, which have already been mentioned, for the input of two key subblocks Z 5 , Z 6 .
  • the core of the extended encryption logic 140 is formed by the primary logic 40, which was already described. This is supplemented by six operation units 115 to 120 of a third kind , specifically in such a way that the input 125 leads the units 115 and 117, the input 126 leads to the units 116 and 118, the input 127 leads to the units 115 and 119, the input 128 leads to the units 116 and 120, the outputs of the units 15 and 116 form the inputs 50 and 51, respectively, of the logic 40, the outputs 47, 48 of the logic 40 form the inputs of the units 117, 119 and 118, 120, respectively, and the outputs of the units 117 to 120 form the outputs 35 to 38.
  • the extended encryption logic 140 is constructed in such a way that every output 35 to 38 depends on all inputs 125 to 128 and 49, 52, that operation units of different kinds , , follow one another and the characteristic of the involution is given.
  • This last characteristic means that the extended encryption logic 140 is a self-inverse function for the blocks e 5 to e 8 connected to their first inputs 125 to 128, specifically for every given pair of key subblocks Z 5 , Z 6 .
  • Bit-by-bit exclusive-OR is preferably used as operation units 115 to 120 of the third kind .
  • FIG. 8 shows the block wiring diagram of a supplementary encryption logic 240.
  • the latter comprises two operation units 111, 112 of the second kind and two operation units 113, 114 of the first kind .
  • the outputs of the logic 240 are identical to the outputs 135 to 138 of the operation units 111 to 114.
  • FIG. 9 shows the block wiring diagram of one of the first eight identical encryption stages of FIG. 2, e.g. the first stage 61.1. Accordingly, this encryption stage is formed from the combination of a supplementary encryption logic 240 and an extended encryption logic 140, wherein the outputs 135 to 138 of the logic 240 are directly (galvanically) connected with the inputs 125 to 128 of the following logic 140.
  • the inputs 25 to 28 of the respective encryption stage (61.1) are identical to the inputs 225 to 228 of the supplementary encryption logic 240.
  • the outputs of the extended logic 140 when crossed, form the outputs 35 to 38 of the encryption stage 61.1.
  • Six key subblocks e.g.
  • blocks Z 1 to Z 6 are connected to the second inputs 29, 30, 32, 33, 49, 52, and either four plaintext subblocks X 1 to X 4 or four intersubblocks W n1 to W n4 are connected to the first inputs 25 to 28.
  • the ninth encryption stage 69 corresponds exclusively to the supplementary encryption logic 240, wherein the four outputs 135 to 138 of this logic 240 are identical to the four outputs 75 to 78 of the encryption stage 69.
  • the encryption unit 60 (FIG. 2), as overall logic for the encryption of plaintext blocks X which correspond to a sequence of 64 bits in each instance, comprises the following characteristics as a whole:
  • It comprises four first inputs 25 to 28, fifty-two second inputs 28, 29, 30, 32, 33, 49, 52 and four outputs 75 to 78.
  • It comprises eight identical encryption stages 61.1, 61.2, plus another encryption stage 69.
  • It comprises one hundred and sixteen operation units of a total of three different kinds , , .
  • the kinds , , of successive operations alternate in general and continuously in the flow direction of the logical operations.
  • Every block at the outputs 75 to 78 is dependent on all blocks at the first inputs 25 to 28 and on almost all blocks at the second inputs 29, 30, 32, 33, 49, 52, on a total of fifty-three blocks. (The output blocks of three respective blocks connected to the second inputs 129, 130, 132, 133 of the ninth encryption stage 69 are not dependent.)
  • every bit of every block W.sub.(n+1)1 to W.sub.(n+1)4 at the outputs 35 to 38 is dependent on all bits of all blocks W n1 to W n4 and Z n at the first (25 to 28) and second inputs 29, 30, 32, 33, 49, 52, respectively.
  • an encryption unit 60 can serve either for the encryption of a plaintext block X or for the decryption of a ciphertext block Y.
  • the unit 60 can accordingly be used for the encryption process X ⁇ Y as well as for the decryption process Y ⁇ X.
  • FIG. 10 no shows fifty-two decryption subblocks U 1 to U 52 which are used for the decryption process Y ⁇ X, specifically in comparison to the key subblocks Z 1 to Z 52 and in relation to these key subblocks and to the nine encryption stages 61.1, 61.2, 69 (FIG. 2).
  • the key subblocks Z 1 to Z 6 are used in the first stage, the blocks Z 7 to Z 12 are used in the second stage, and so on. Finally, in the ninth stage, blocks Z 49 to Z 52 are used.
  • Z -1 j modulo (2 16 +1) multiplied by Z j is 1. Further, -Z j modulo 2 16 added to Z j is 0.
  • the invention allows a large number of variants. Some of these are listed as follows:
  • the different kinds of operation units 41 to 44, 111 to 114, 115 to 120 are divided differently in the various aforementioned logics 40, 240, 140.
  • the operation units of the two kinds are exchanged in the primary encryption logic 40.
  • the first two decryption subblocks of every stage i are identical to the modulo (2 m +1) multiplication inverses of the first or second key subblock of the first or second key subblock in the (S-i+2)th stage of the encryption process,
  • the fifth and sixth decryption subblocks in the ith stage are identical to the fifth and sixth key subblock, respectively, in the (S-i+1)th stage of the encryption process.
  • the derivation of the key subblocks Z 1 to Z 52 from the key subblock Z is effected according to a method other than that described.
  • the construction of the encryption unit 60 is effected predominantly with the use of discrete operation units 41 to 44, 111 to 114, 115 to 120 as special logic units (hardware implementation), predominantly with the use of commercially available processors and storages, which work according to an assigned program (software implementation) or in mixed construction.
  • Each of the described logics 40, 140, 240, 60, 61.1, 61.2, 69 can be conceived as a "black box" with first and second inputs and outputs.
  • Each of these logics converts the two or four first subblocks connected to the first inputs into assigned second subblocks of the same length which can be tapped at the outputs.
  • the conversion process is influenced by the key subblocks connected to the second inputs or in general by suitable control blocks. Parallel inputs and outputs are advantageous if higher working speeds are desired.
  • An individual first and second input and an individual single output are preferably to be provided for said software implementation, the assigned input and output blocks being inputted and outputted serially by means of them.
  • the (second) length m be either 4, 8 or preferably 16 bits.
  • the encryption logics 40, 140, 240 can be constructed from VLSI semiconductor modules (VLSI very large scale integration) and can accordingly be inexpensively produced.
  • FIGS. 11 to 14 are modifications of FIGS. 8, 9, 2 and 10.
  • FIG. 11 shows the block wiring diagram of a second supplementary encryption logic 240v.
  • the latter comprises two operation units 111v, 114v of the second kind and two operation units 112v, 113v of the first kind .
  • the outputs of the logic 240 are identical to the outputs 135 to 138 of the operation units 111v to 114v.
  • FIG. 12 shows the block wiring diagram of a second encryption stage 61.1v.
  • the latter is formed from the combination of the supplementary encryption logic 240v and an extended encryption logic 140, wherein the outputs 135 to 138 of the logic 240v are (galvanically) connected directly with the inputs 125 to 128 of the following logic 140.
  • the inputs 25 to 28 of the respective encryption stage (61.1v) are identical to the inputs 225 to 228 of the second, supplementary encryption logic 240v.
  • the outputs of the extended logic 140 directly form the outputs 35 to 38 and, when crossed, the outputs 36 and 37 of the encryption stage 61.1v.
  • the remaining construction corresponds completely to that of FIG. 9.
  • FIG. 13 shows the block wiring diagram of a second encryption unit 60v which corresponds to a great extent to FIG. 2.
  • Eight identical second encryption stages 61.1v, 61.2v are connected one after the other in this instance, a second, supplementary encryption logic 240v being connected subsequent to the latter as last stage 69v.
  • the inputs W 82 and W 83 are connected in a crossed manner with . . . W 22 and . . . W 23 , respectively.
  • FIG. 14 shows a second table of key subblocks Z n and decryption subblocks U n , corresponding to FIG. 10.
  • Z -1 j modulo (2 16 +1) multiplied by Z j is 1.
  • -Z j modulo 2 16 added to Z j is 0.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Storage Device Security (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
US07/781,235 1990-05-18 1991-05-16 Device for the conversion of a digital block and use of same Expired - Lifetime US5214703A (en)

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EP (1) EP0482154B1 (ja)
JP (1) JP3225440B2 (ja)
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WO1991018459A2 (de) 1991-11-28
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JP3225440B2 (ja) 2001-11-05
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EP0482154A1 (de) 1992-04-29
HK1003338A1 (en) 1998-10-23

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