US5188974A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

Info

Publication number
US5188974A
US5188974A US07/747,486 US74748691A US5188974A US 5188974 A US5188974 A US 5188974A US 74748691 A US74748691 A US 74748691A US 5188974 A US5188974 A US 5188974A
Authority
US
United States
Prior art keywords
layer
semiconductor
semiconductor layer
manufacturing
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US07/747,486
Inventor
Chiori Mochizuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62276348A external-priority patent/JP2831997B2/en
Application filed by Canon Inc filed Critical Canon Inc
Priority to US07/747,486 priority Critical patent/US5188974A/en
Application granted granted Critical
Publication of US5188974A publication Critical patent/US5188974A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00—Charge transfer devices
    • H10D44/01—Manufacture or treatment
    • H10D44/041—Manufacture or treatment having insulated gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/10—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices being sensitive to infrared radiation, visible or ultraviolet radiation, and having no potential barriers, e.g. photoresistors
    • H10F30/15—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices being sensitive to infrared radiation, visible or ultraviolet radiation, and having no potential barriers, e.g. photoresistors comprising amorphous semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/191—Photoconductor image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/10—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material
    • H10F71/103—Manufacture or treatment of devices covered by this subclass the devices comprising amorphous semiconductor material including only Group IV materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/105—Masks, metal

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device, and more particularly to a semiconductor device manufacturing method suitable for use in manufacturing particularly a photoelectric conversion device wherein an insulating layer and a photoconductive semiconductor layer are formed in association with a photoelectric conversion region, a charge storage region for storing an output of the photoelectric conversion region, and a switch region connected to the charge storage region.
  • a reader system of a facsimile with an image reduction optical system and a CCD sensor of semiconductor device has been used.
  • photoconductive semiconductor material a typical example of which is amorphous silicon hydride (hereinafter abbreviated as a-Si:H)
  • a so-called contact type line sensor of semiconductor device has been developed extensively, wherein a photoelectric conversion region and a signal processing region are formed on an elongated substrate to read an original document with an equal magnification optical system.
  • an a-Si:H can be used not only as photoelectric converting material but also as semiconductor material of field effect transistors. Therefore, the photoconductive semiconductor layer of a photoelectric conversion region and the semiconductor layer of a driving element region (signal processing region) can be formed at the same time. Thus, it is possible to provide a photoelectric conversion device having a plurality of elements each having a photoelectric conversion region and a driving element region both formed integrally on the same substrate.
  • FIG. 1 is a partial cross sectional vertical view showing the structure of a line sensor as an example of a semiconductor device.
  • a wiring region 2 As shown in FIG. 1, there are formed on a substrate 1 a wiring region 2, photoelectric conversion region 3, charge storage region 4, and switch region 5. Formed on the substrate 1 are an underlying electrode wiring 6 in the wiring region 2, an underlying electrode wiring 7 in the charge storage region 4, and an underlying electrode wiring 8 serving as the gate electrode in the switch region 5.
  • An insulating layer 9 is formed on these underlying electrode wiring layers 6, 7 and 8.
  • a semiconductor layer (a-Si:H) 11 is formed on the insulating layer 9 in the switch region 5, whereas a photoconductive semiconductor layer (a-Si:H) 10 of photoconductive material is formed on the substrate 1 in the photoelectric conversion region 3. In this case, &he semiconductor layer 11 and photoconductive semiconductor layer 10 are formed at the same time.
  • a matrix wiring is formed between the underlying electrode wiring 6 and an overlying electrode wiring 12 with an insulating layer interposed therebetween.
  • the photoconductive semiconductor layer 10 and the semiconductor layer 11 are connected by an overlying electrode wiring 13 which runs above the insulating layer 9 in the charge storage region 4.
  • the overlying electrode wiring 13, insulating layer 9 and underlying electrode wiring 7 constitute a storage capacitor.
  • a portion of the overlying electrode wiring 13 connected to one end of the semiconductor layer 11 serves as the drain electrode, and a portion of an overlying electrode wiring 14 connected to the other end of the semiconductor layer 11 serves as the source electrode.
  • the structure described above has the photoelectric conversion region and signal processing region on the same substrate.
  • the semiconductor layer is formed only in the photoelectric conversion region 3 and switch region 5.
  • the insulating layer 9, and the photoconductive semiconductor layer 10 and semiconductor layer 11 on the insulating layer are formed by a film forming method such as glow discharge, and patterned by means of photolithography similar to the case of patterning the overlying and underlying electrode wirings.
  • FIG. 2 is a schematic plan view showing another example of a line sensor wherein although only two bit elements are shown, the actual line sensor has 1728 bits in total (corresponding to an A4 size readable length, with the density of 8 elements per mm).
  • FIG. 3 is a partial cross sectional vertical view of the line sensor shown in FIG. 2, wherein an n + layer shown in FIG. 4E is omitted for the sake of brevity.
  • FIGS. 4A to 4E are schematic cross sectional vertical views along line A--A' of FIG. 2 showing conventional line sensor manufacturing steps.
  • FIGS. 4D' and 4E' corresponding to FIGS. 4D and 4E are schematic cross sectional lateral views along line B--B' of FIG. 2.
  • FIGS. 4A to 4E' differ from FIG. 3 in that an n + layer is shown and the insulating layer is removed from a wiring region 102.
  • a glass substrate manufactured by Corning Company Ltd. #7059 whose opposite sides were polished was washed in an ordinary manner using neutral detergent (or organic alkali based detergent).
  • a photoresist pattern of desired configuration was formed using a positive type photoresist (Tokyo Ohka NMD-3). Thereafter, an unnecessary portion of Al was etched using an etching liquid made of a mixture of phosphoric acid (85% in volume solution), glacial acetic acid and water with 16:1:2:1: in volume ratio.
  • the glass substrate 100 was set in a capacitive coupling type glow discharge decomposer which was maintained at 230° C. and at a vacuum pressure of 1 ⁇ 10 -6 Torr.
  • SiH 4 diluted to 10% with H 2 was introduced into the decomposer at a flow rate of 5 SCCM, and at the same time NH 3 was introduced therein at a flow rate of 20 SCCM.
  • a glow discharge was effected for 2 hours at an RF discharge power 15 W using a high frequency power source at 13.56 MHz, to thus form an insulating layer 109 made of silicon nitride to the thickness of 0.3 micron.
  • SiH 4 was introduced at the flow rate of 10 SCCM and a glow discharge was effected for 5 hours at the discharge power 8 W and at a gas pressure 0.07 Torr, to thus form an amorphous silicon intrinsic layer 110 to the thickness of 0.50 micron.
  • a gaseous mixture of SiH 4 diluted to 10% with H 2 and PH 3 diluted to 100 ppm with H 2 at a mixture ratio of 1:10 an ohmic contact n + layer 115 was deposited to the thickness of 0.12 micron at a discharge power 30 W (FIG. 4B).
  • a contact hole pattern was formed using a positive type photoresist (Tokyo Ohka NMD-3). Unnecessary portions of the n + layer and amorphous silicon intrinsic layer were etched by means of the chemical dry etching method (CDE method) with CF 4 gas to thus form a contact hole 116. In this case, there is no need of selective etching among the n + layer, photoconductive semiconductor layer and insulating layer. (FIG. 4C).
  • Al was deposited to the thickness of 1.0 to 1.5 micron by the sputtering method, to form a conductive layer.
  • the exposed conductive layer was etched using an etching liquid made of a mixture of phosphoric acid (85% in volume solution), glacial acetic acid and water with 16:1:2:1 in volume ratio, to thus form an overlying electrode.
  • the exposed n + layer was dry etched by means of the reactive ion etching method (RIE method) with CF 4 gas, to thus form the n + layer into a desired configuration (n + etching process).
  • RIE method reactive ion etching method
  • CF 4 gas CF 4 gas
  • a passivation film (not shown) was formed using silicon nitride by the CVD method, organic resin by coating method, or the like, to thus complete an optical sensor array.
  • the patterning of overlying electrode Al is performed through wet etching so that the resist pattern design takes a side etching amount into consideration.
  • the RIE method i.e., anisotropic etching
  • the resist pattern for the Al patterning is used as a mask, the design values are not satisfied sufficiently.
  • a problem associated with a sensor characteristic may occur.
  • FIG. 1 is a schematic cross sectional vertical view showing the structure of a line sensor to which the present invention is applicable;
  • FIG. 2 is a schematic cross sectional vertical view showing the structure of another line sensor to which the present invention is applicable;
  • FIG. 3 is a schematic cross sectional view showing the line sensor shown in FIG. 2;
  • FIGS. 4A to 4D are schematic cross sectional vertical views showing the conventional processes of manufacturing the line sensor shown in FIG. 2;
  • FIGS. 4D' and 4E' corresponding to FIGS. 4D and 4E are the schematic cross sectional lateral views
  • FIGS. 5A to 5E are schematic cross sectional vertical views showing the method of manufacturing the line sensor shown in FIG. 2 according to the present invention.
  • FIGS. 5D' and 5E' corresponding to FIGS. 5D and 5E are the schematic cross sectional lateral views.
  • an element isolation process to remove the semiconductor layer except the necessary portions by means of dry etching such as reactive ion etching, chemical ion etching or the like using, for example, a gas such as CF 4 , CHF 3 , CCl 2 F 2 , CF 3 Br, CF 4 +Cl 2 , CF 4 'O 2 , and CF 4 'H 2 .
  • dry etching such as reactive ion etching, chemical ion etching or the like using, for example, a gas such as CF 4 , CHF 3 , CCl 2 F 2 , CF 3 Br, CF 4 +Cl 2 , CF 4 'O 2 , and CF 4 'H 2 .
  • the invention is also properly applied to the method of manufacturing a photoelectric conversion device as described in the following Example.
  • FIGS. 5A to 5E are schematic cross sectional vertical views showing the steps of manufacturing an optical line sensor array according to the present invention.
  • FIGS. 5D' and 5E' corresponding to FIGS. 5D and 5E are schematic cross sectional vertical views.
  • a glass substrate manufactured by Corning Company Ltd. #7059 whose opposite sides were polished was washed in an ordinary manner using neutral detergent (or organic alkali based detergent).
  • a photoresist pattern of desired configuration was formed using a positive type photoresist (Tokyo Ohka NMD-3). Thereafter, an unnecessary portion of Al was etched using an etching liquid made of a mixture of phosphoric acid (85% in volume solution), glacial acetic acid and water with 16:1:2:1 in volume ratio.
  • the glass substrate 100 was set in a capacitive coupling type glow discharge decomposer which was maintained at 230° C. and at a vacuum pressure of 1 ⁇ 10 -6 Torr.
  • SiH 4 diluted to 10% with H 2 was introduced into the decomposer at a flow rate of 5 SCCM, and at the same time NH 3 was introduced therein at a flow rate of 20 SCCM.
  • a glow discharge was effected for 2 hours at an RF discharge power 15 W using a high frequency power source at 13.56 MHz, to thus form an insulating layer 109 made of silicon nitride to the thickness of 0.3 micron.
  • SiH 4 was introduced at the flow rate of 10 SCCM and a glow discharge was effected for 5 hours at the discharge power 8 W and at a gas pressure 0.07 Torr, to thus form an amorphous silicon intrinsic layer 110 to the thickness of 0.50 micron.
  • a gaseous mixture of SiH 4 diluted to 10% with H 2 and PH 3 diluted to 100 ppm with H 2 at a mixture ratio of 1:10 an ohmic contact n + layer 115 was deposited to the thickness of 0.12 micron at a discharge power 30 W (FIG. 5B).
  • a contact hole pattern was formed using a positive type photoresist (Tokyo Ohka NMD-3). Unnecessary portion of the n + layer and amorphous silicon intrinsic layer were etched by means of the chemical dry etching method (CDE method) with CF 4 gas to thus form a contact hole 116. In this case, there is no need of selective etching among the n + layer, photoconductive semiconductor layer and insulating layer (FIG. 5C).
  • CDE method chemical dry etching method
  • Al was deposited to the thickness of 1.0 to 1.5 micron by the sputtering method, to form a conductive layer.
  • the exposed conductive layer was etched using an etching liquid made of a mixture of phosphoric acid (85% in volume solution), glacial acetic acid and water with 16:1:2:1 in volume ratio, to thus form an overlying electrode.
  • the unnecessary portions of the intrinsic semiconductor layer and insulating layer were dry etched by means of the reactive ion etching method (RIE method) with CF 4 gas.
  • RIE method reactive ion etching method
  • the exposed n + layer was etched by the RIE method, to thus form the gap in the photoelectric region 3 and the channel of the transfer transistor in the switch region 5.
  • a passivation film (not shown) was formed using silicon nitride by the CVD method, organic resin by coating method, or the like to thus complete an optical sensor array.
  • the pattern for etching the n + layer can be formed within the allowance of design values.
  • the isolation step which takes a longer etching time than that of the n + layer etching is carried out first so that partial damage, if any, of the gap in the photoelectric conversion region and the channel of the transfer transistor can be removed at the next n + layer etching process, to thus allow a more stable sensor characteristic.
  • the senor characteristic satisfying the design values becomes possible, and a highly densed patterning can be easily realized.

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)

Abstract

A method of manufacturing a semiconductor device having a photoconductive semiconductor layer formed on a substrate and a pair of electrodes formed on the semiconductor layer with an ohmic contact layer interposed therebetween, wherein the ohmic contact layer is removed after the etching process of the semiconductor layer.

Description

This application is a continuation of application Ser. No. 07/470,406 filed Jan. 29, 1990, now abandoned, which is a continuation of application Ser. No. 07/264,083 filed Oct. 28, 1988, now abandoned.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a semiconductor device manufacturing method suitable for use in manufacturing particularly a photoelectric conversion device wherein an insulating layer and a photoconductive semiconductor layer are formed in association with a photoelectric conversion region, a charge storage region for storing an output of the photoelectric conversion region, and a switch region connected to the charge storage region.
2. Related Background Art
Conventionally, as a reader system of a facsimile, with an image reduction optical system and a CCD sensor of semiconductor device has been used. Following the development of photoconductive semiconductor material, a typical example of which is amorphous silicon hydride (hereinafter abbreviated as a-Si:H), a so-called contact type line sensor of semiconductor device has been developed extensively, wherein a photoelectric conversion region and a signal processing region are formed on an elongated substrate to read an original document with an equal magnification optical system.
Particularly, an a-Si:H can be used not only as photoelectric converting material but also as semiconductor material of field effect transistors. Therefore, the photoconductive semiconductor layer of a photoelectric conversion region and the semiconductor layer of a driving element region (signal processing region) can be formed at the same time. Thus, it is possible to provide a photoelectric conversion device having a plurality of elements each having a photoelectric conversion region and a driving element region both formed integrally on the same substrate.
FIG. 1 is a partial cross sectional vertical view showing the structure of a line sensor as an example of a semiconductor device.
As shown in FIG. 1, there are formed on a substrate 1 a wiring region 2, photoelectric conversion region 3, charge storage region 4, and switch region 5. Formed on the substrate 1 are an underlying electrode wiring 6 in the wiring region 2, an underlying electrode wiring 7 in the charge storage region 4, and an underlying electrode wiring 8 serving as the gate electrode in the switch region 5. An insulating layer 9 is formed on these underlying electrode wiring layers 6, 7 and 8. A semiconductor layer (a-Si:H) 11 is formed on the insulating layer 9 in the switch region 5, whereas a photoconductive semiconductor layer (a-Si:H) 10 of photoconductive material is formed on the substrate 1 in the photoelectric conversion region 3. In this case, &he semiconductor layer 11 and photoconductive semiconductor layer 10 are formed at the same time.
A matrix wiring is formed between the underlying electrode wiring 6 and an overlying electrode wiring 12 with an insulating layer interposed therebetween. The photoconductive semiconductor layer 10 and the semiconductor layer 11 are connected by an overlying electrode wiring 13 which runs above the insulating layer 9 in the charge storage region 4. The overlying electrode wiring 13, insulating layer 9 and underlying electrode wiring 7 constitute a storage capacitor. A portion of the overlying electrode wiring 13 connected to one end of the semiconductor layer 11 serves as the drain electrode, and a portion of an overlying electrode wiring 14 connected to the other end of the semiconductor layer 11 serves as the source electrode.
The structure described above has the photoelectric conversion region and signal processing region on the same substrate. As shown in FIG. 1, the semiconductor layer is formed only in the photoelectric conversion region 3 and switch region 5. The insulating layer 9, and the photoconductive semiconductor layer 10 and semiconductor layer 11 on the insulating layer are formed by a film forming method such as glow discharge, and patterned by means of photolithography similar to the case of patterning the overlying and underlying electrode wirings.
FIG. 2 is a schematic plan view showing another example of a line sensor wherein although only two bit elements are shown, the actual line sensor has 1728 bits in total (corresponding to an A4 size readable length, with the density of 8 elements per mm).
FIG. 3 is a partial cross sectional vertical view of the line sensor shown in FIG. 2, wherein an n+ layer shown in FIG. 4E is omitted for the sake of brevity.
FIGS. 4A to 4E are schematic cross sectional vertical views along line A--A' of FIG. 2 showing conventional line sensor manufacturing steps. FIGS. 4D' and 4E' corresponding to FIGS. 4D and 4E are schematic cross sectional lateral views along line B--B' of FIG. 2.
FIGS. 4A to 4E' differ from FIG. 3 in that an n+ layer is shown and the insulating layer is removed from a wiring region 102.
The manufacturing method of the line sensor in FIG. 3 will be described with reference to FIGS. 4A to 4E'.
A glass substrate (manufactured by Corning Company Ltd. #7059) whose opposite sides were polished was washed in an ordinary manner using neutral detergent (or organic alkali based detergent).
Cr was deposited to the thickness of 500 Å by the sputter method. Al was then deposited to the thickness of 500 Å by the sputtering method.
A photoresist pattern of desired configuration was formed using a positive type photoresist (Tokyo Ohka NMD-3). Thereafter, an unnecessary portion of Al was etched using an etching liquid made of a mixture of phosphoric acid (85% in volume solution), glacial acetic acid and water with 16:1:2:1: in volume ratio.
Next, an unnecessary portion of Cr was etched using an aqueous solution of a mixture of ammonium cerium (IV) nitrate and perchloric acid, to thereby form underlying electrode wirings 106, 107 and 108 in wiring region 102, charge storage region 104 and transfer switch region 105, respectively (FIG. 4A).
Next, the glass substrate 100 was set in a capacitive coupling type glow discharge decomposer which was maintained at 230° C. and at a vacuum pressure of 1×10-6 Torr. SiH4 diluted to 10% with H2 was introduced into the decomposer at a flow rate of 5 SCCM, and at the same time NH3 was introduced therein at a flow rate of 20 SCCM. A glow discharge was effected for 2 hours at an RF discharge power 15 W using a high frequency power source at 13.56 MHz, to thus form an insulating layer 109 made of silicon nitride to the thickness of 0.3 micron. Next, SiH4 was introduced at the flow rate of 10 SCCM and a glow discharge was effected for 5 hours at the discharge power 8 W and at a gas pressure 0.07 Torr, to thus form an amorphous silicon intrinsic layer 110 to the thickness of 0.50 micron. Subsequently, using as a raw material a gaseous mixture of SiH4 diluted to 10% with H2 and PH3 diluted to 100 ppm with H2 at a mixture ratio of 1:10, an ohmic contact n+ layer 115 was deposited to the thickness of 0.12 micron at a discharge power 30 W (FIG. 4B).
Next, a contact hole pattern was formed using a positive type photoresist (Tokyo Ohka NMD-3). Unnecessary portions of the n+ layer and amorphous silicon intrinsic layer were etched by means of the chemical dry etching method (CDE method) with CF4 gas to thus form a contact hole 116. In this case, there is no need of selective etching among the n+ layer, photoconductive semiconductor layer and insulating layer. (FIG. 4C).
Next, Al was deposited to the thickness of 1.0 to 1.5 micron by the sputtering method, to form a conductive layer. Succeedingly, after forming a photoresist pattern of desired configuration, the exposed conductive layer was etched using an etching liquid made of a mixture of phosphoric acid (85% in volume solution), glacial acetic acid and water with 16:1:2:1 in volume ratio, to thus form an overlying electrode. Thereafter, the exposed n+ layer was dry etched by means of the reactive ion etching method (RIE method) with CF4 gas, to thus form the n+ layer into a desired configuration (n+ etching process). Next, the photoresist was removed (FIGS. 4D and 4D').
Next, a photoresist pattern was formed for isolating each element.
Thereafter, unnecessary portions of the intrinsic semiconductor layer and insulating layer were dry etched by means of the RIE method with CF4 gas. As a result, respective elements integrally coupled and electrically connected via the photoconductive semiconductor layer were made independent and separate (isolation process) and only the necessary electrode wirings were used for electrical connection. Next, the photoresist was removed (FIGS. 4E and 4E').
Next, a passivation film (not shown) was formed using silicon nitride by the CVD method, organic resin by coating method, or the like, to thus complete an optical sensor array.
In the line sensor of semiconductor device described above, the patterning of overlying electrode Al is performed through wet etching so that the resist pattern design takes a side etching amount into consideration. However, since the following process of etching the n+ layer is performed by the RIE method, i.e., anisotropic etching, if the resist pattern for the Al patterning is used as a mask, the design values are not satisfied sufficiently. Thus, in a semiconductor device requiring a highly densed pattern, a problem associated with a sensor characteristic may occur.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of manufacturing a semiconductor device having a photoconductive semiconductor layer formed on a substrate and a pair of electrodes formed on the semiconductor layer with an ohmic contact layer interposed therebetween, wherein the ohmic contact layer is removed after the etching process of the semiconductor layer.
It is another object of the present invention to provide a method of patterning an n+ layer capable of satisfying the design values, by changing the order of the n+ etching process and the isolation process.
It is a further object of the present invention to provide a photoelectric conversion device manufactured by the above method which can provide a uniform characteristic of each element and a large S/N ratio.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic cross sectional vertical view showing the structure of a line sensor to which the present invention is applicable;
FIG. 2 is a schematic cross sectional vertical view showing the structure of another line sensor to which the present invention is applicable;
FIG. 3 is a schematic cross sectional view showing the line sensor shown in FIG. 2;
FIGS. 4A to 4D are schematic cross sectional vertical views showing the conventional processes of manufacturing the line sensor shown in FIG. 2;
FIGS. 4D' and 4E' corresponding to FIGS. 4D and 4E are the schematic cross sectional lateral views;
FIGS. 5A to 5E are schematic cross sectional vertical views showing the method of manufacturing the line sensor shown in FIG. 2 according to the present invention; and
FIGS. 5D' and 5E' corresponding to FIGS. 5D and 5E are the schematic cross sectional lateral views.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
A preferred embodiment of the present invention will be described below. It is to be understood that the present invention is not limited to the embodiment only, but the invention is applicable to other modifications which achieve the above objects.
According to the present invention, after forming a semiconductor layer on a substrate and forming a plurality of pairs of electrodes with an ohmic contact layer on the semiconductor layer interposed therebetween, an element isolation process to remove the semiconductor layer except the necessary portions by means of dry etching such as reactive ion etching, chemical ion etching or the like using, for example, a gas such as CF4, CHF3, CCl2 F2, CF3 Br, CF4 +Cl2, CF4 'O2, and CF4 'H2. Thereafter, by removing the exposed ohmic contact layer by the etching method similar to the above, active regions of functional element such as the gap in photoelectric conversion region and/or the switch region, the channel and the like are formed.
The invention is also properly applied to the method of manufacturing a photoelectric conversion device as described in the following Example.
Example
FIGS. 5A to 5E are schematic cross sectional vertical views showing the steps of manufacturing an optical line sensor array according to the present invention. FIGS. 5D' and 5E' corresponding to FIGS. 5D and 5E are schematic cross sectional vertical views.
A glass substrate (manufactured by Corning Company Ltd. #7059) whose opposite sides were polished was washed in an ordinary manner using neutral detergent (or organic alkali based detergent).
Cr was deposited to the thickness of 500 Å by the sputtering method. Al was then deposited to the thickness of 500 Å by the sputter method.
A photoresist pattern of desired configuration was formed using a positive type photoresist (Tokyo Ohka NMD-3). Thereafter, an unnecessary portion of Al was etched using an etching liquid made of a mixture of phosphoric acid (85% in volume solution), glacial acetic acid and water with 16:1:2:1 in volume ratio.
Next, an unnecessary portion of Cr was etched using an aqueous solution of a mixture of ammonium cerium (IV) nitrate and perchloric acid, to thereby form underlying electrode wirings 106, 107 and 108 in wiring region 102, charge storage region 104 and transfer switch region 105, respectively (FIG. 5A).
Next, the glass substrate 100 was set in a capacitive coupling type glow discharge decomposer which was maintained at 230° C. and at a vacuum pressure of 1×10-6 Torr. SiH4 diluted to 10% with H2 was introduced into the decomposer at a flow rate of 5 SCCM, and at the same time NH3 was introduced therein at a flow rate of 20 SCCM. A glow discharge was effected for 2 hours at an RF discharge power 15 W using a high frequency power source at 13.56 MHz, to thus form an insulating layer 109 made of silicon nitride to the thickness of 0.3 micron. Next, SiH4 was introduced at the flow rate of 10 SCCM and a glow discharge was effected for 5 hours at the discharge power 8 W and at a gas pressure 0.07 Torr, to thus form an amorphous silicon intrinsic layer 110 to the thickness of 0.50 micron. Subsequently, using as a raw material a gaseous mixture of SiH4 diluted to 10% with H2 and PH3 diluted to 100 ppm with H2 at a mixture ratio of 1:10, an ohmic contact n+ layer 115 was deposited to the thickness of 0.12 micron at a discharge power 30 W (FIG. 5B).
Next, a contact hole pattern was formed using a positive type photoresist (Tokyo Ohka NMD-3). Unnecessary portion of the n+ layer and amorphous silicon intrinsic layer were etched by means of the chemical dry etching method (CDE method) with CF4 gas to thus form a contact hole 116. In this case, there is no need of selective etching among the n+ layer, photoconductive semiconductor layer and insulating layer (FIG. 5C).
Next, Al was deposited to the thickness of 1.0 to 1.5 micron by the sputtering method, to form a conductive layer. Succeedingly, after forming a photoresist pattern of desired configuration, the exposed conductive layer was etched using an etching liquid made of a mixture of phosphoric acid (85% in volume solution), glacial acetic acid and water with 16:1:2:1 in volume ratio, to thus form an overlying electrode. Thereafter, the unnecessary portions of the intrinsic semiconductor layer and insulating layer were dry etched by means of the reactive ion etching method (RIE method) with CF4 gas. As a result, respective elements integrally coupled and electrically connected via the photoconductive semiconductor layer were made independent and separate (isolation process) and only the necessary electrode wirings were used for electrical connection. Next, the photoresist was removed (FIGS. 5D and 5D').
Next, as shown in FIGS. 5E and 5E', using the overlying electrode pattern as a mask, the exposed n+ layer was etched by the RIE method, to thus form the gap in the photoelectric region 3 and the channel of the transfer transistor in the switch region 5.
Next, a passivation film (not shown) was formed using silicon nitride by the CVD method, organic resin by coating method, or the like to thus complete an optical sensor array.
As described so far, according to the method of manufacturing a semiconductor device of this invention, the pattern for etching the n+ layer can be formed within the allowance of design values. According to the method of manufacturing a photoelectric conversion device of this invention, the isolation step which takes a longer etching time than that of the n+ layer etching is carried out first so that partial damage, if any, of the gap in the photoelectric conversion region and the channel of the transfer transistor can be removed at the next n+ layer etching process, to thus allow a more stable sensor characteristic.
Since respective elements have already been isolated during the n+ layer etching process, voltage withstanding between elements and of elements becomes great and the electrical corrosion can be prevented because of the side wall effect (deposition of fluoride on the wall) during the n+ layer etching process.
As above, according to the present invention, the sensor characteristic satisfying the design values becomes possible, and a highly densed patterning can be easily realized.

Claims (9)

What is claimed is:
1. A method for manufacturing a semiconductor device on a substrate, said semiconductor device including a plurality of semiconductor elements having a semiconductor region and a pair of electrodes disposed on said semiconductor region through an ohmic contact region disposed on said semiconductor region, comprising the sequential steps of:
forming a semiconductor layer on said substrate, an ohmic contact layer on said semiconductor layer, and a conductive layer on said ohmic contact layer;
removing a portion of said conductive layer, whereby said pair of electrodes are formed on said ohmic contact layer;
removing a portion of said semiconductor layer and said ohmic contact layer to isolate each of said plurality of semiconductor elements;
removing a portion of said ohmic contact layer between said pair of electrodes by utilizing said pair of electrodes as a mask.
2. A method of manufacturing a semiconductor device according to claim 1, wherein said ohmic contact layer is patterned using said electrodes as a mask.
3. A method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor layer is made of amorphous silicon hydride.
4. A method of manufacturing a semiconductor device according to claim 1, wherein said semiconductor layer and/or said ohmic contact layer is removed by a reactive ion etching method.
5. A method for manufacturing a semiconductor device according to claim 1, wherein said semiconductor element is a photosensor.
6. A method for manufacturing a semiconductor device according to claim 1, wherein said semiconductor element is a transistor.
7. A method for manufacturing a semiconductor device on a substrate, said semiconductor device including a plurality of semiconductor elements having a first semiconductor layer and a pair of electrodes disposed on said first semiconductor layer through a second semiconductor layer having a lower resistivity than said first semiconductor layer, comprising the sequential steps of:
forming a first semiconductor layer on said substrate;
forming a second semiconductor layer on said first semiconductor layer; and
forming a conductive layer on said second semiconductor layer;
removing a portion of said conductive layer, whereby said pair of electrodes are formed on said second semiconductor layer;
removing a portion of said first semiconductor layer and said second semiconductor layer to isolate each of the plurality of semiconductor elements; and
removing a portion of said second semiconductor layer between said pair of electrodes by utilizing said pair of electrodes as a mask.
8. A method for manufacturing a semiconductor device according to claim 7, wherein said semiconductor element is a photosensor.
9. A method for manufacturing a semiconductor device according to claim 7, wherein said semiconductor element is a transistor.
US07/747,486 1987-10-31 1991-08-19 Method of manufacturing semiconductor device Expired - Lifetime US5188974A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US07/747,486 US5188974A (en) 1987-10-31 1991-08-19 Method of manufacturing semiconductor device

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP62276348A JP2831997B2 (en) 1987-10-31 1987-10-31 Method for manufacturing semiconductor device
JP62-276348 1987-10-31
US26408388A 1988-10-28 1988-10-28
US47040690A 1990-01-29 1990-01-29
US07/747,486 US5188974A (en) 1987-10-31 1991-08-19 Method of manufacturing semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US47040690A Continuation 1987-10-31 1990-01-29

Publications (1)

Publication Number Publication Date
US5188974A true US5188974A (en) 1993-02-23

Family

ID=27479079

Family Applications (1)

Application Number Title Priority Date Filing Date
US07/747,486 Expired - Lifetime US5188974A (en) 1987-10-31 1991-08-19 Method of manufacturing semiconductor device

Country Status (1)

Country Link
US (1) US5188974A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5496749A (en) * 1992-10-15 1996-03-05 Fujitsu Limited Method of manufacturing thin film transistors in a liquid crystal display apparatus
US5547879A (en) * 1995-05-03 1996-08-20 Dierschke; Eugene G. Method of making position sensing photosensor device
US5686326A (en) * 1985-08-05 1997-11-11 Canon Kabushiki Kaisha Method of making thin film transistor
US6121094A (en) * 1998-07-21 2000-09-19 Advanced Micro Devices, Inc. Method of making a semiconductor device with a multi-level gate structure

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4405915A (en) * 1980-03-28 1983-09-20 Canon Kabushiki Kaisha Photoelectric transducing element
JPS58190061A (en) * 1982-04-28 1983-11-05 Toshiba Corp Amorphous silicon semiconductor device
US4545111A (en) * 1983-01-18 1985-10-08 Energy Conversion Devices, Inc. Method for making, parallel preprogramming or field programming of electronic matrix arrays
US4581099A (en) * 1985-01-30 1986-04-08 Canon Kabushiki Kaisha Method for preparation of a photosensor
JPS61201461A (en) * 1985-03-05 1986-09-06 Oki Electric Ind Co Ltd Manufacture of photosensor element
US4857751A (en) * 1987-06-26 1989-08-15 Canon Kabushiki Kaisha Photoelectric conversion apparatus with separating electrodes
US4931661A (en) * 1986-01-24 1990-06-05 Canon Kabushiki Kaisha Photoelectric conversion device having a common semiconductor layer for a portion of the photoelectric conversion element and a portion of the transfer transistor section

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4405915A (en) * 1980-03-28 1983-09-20 Canon Kabushiki Kaisha Photoelectric transducing element
JPS58190061A (en) * 1982-04-28 1983-11-05 Toshiba Corp Amorphous silicon semiconductor device
US4545111A (en) * 1983-01-18 1985-10-08 Energy Conversion Devices, Inc. Method for making, parallel preprogramming or field programming of electronic matrix arrays
US4581099A (en) * 1985-01-30 1986-04-08 Canon Kabushiki Kaisha Method for preparation of a photosensor
JPS61201461A (en) * 1985-03-05 1986-09-06 Oki Electric Ind Co Ltd Manufacture of photosensor element
US4931661A (en) * 1986-01-24 1990-06-05 Canon Kabushiki Kaisha Photoelectric conversion device having a common semiconductor layer for a portion of the photoelectric conversion element and a portion of the transfer transistor section
US4857751A (en) * 1987-06-26 1989-08-15 Canon Kabushiki Kaisha Photoelectric conversion apparatus with separating electrodes

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5686326A (en) * 1985-08-05 1997-11-11 Canon Kabushiki Kaisha Method of making thin film transistor
US5496749A (en) * 1992-10-15 1996-03-05 Fujitsu Limited Method of manufacturing thin film transistors in a liquid crystal display apparatus
US5547879A (en) * 1995-05-03 1996-08-20 Dierschke; Eugene G. Method of making position sensing photosensor device
US6121094A (en) * 1998-07-21 2000-09-19 Advanced Micro Devices, Inc. Method of making a semiconductor device with a multi-level gate structure

Similar Documents

Publication Publication Date Title
US4931661A (en) Photoelectric conversion device having a common semiconductor layer for a portion of the photoelectric conversion element and a portion of the transfer transistor section
US5338690A (en) Photoelectronic conversion device
US7560353B2 (en) Methods of fabricating memory devices with memory cell transistors having gate sidewall spacers with different dielectric properties
US5202575A (en) TFT-driven image sensor including a reduced-size capacitor structure
KR960003773B1 (en) DRAM Cell Manufacturing Method
US5188974A (en) Method of manufacturing semiconductor device
US6218234B1 (en) Dual gate and double poly capacitor analog process integration
US5366921A (en) Process for fabricating an electronic circuit apparatus
US5318921A (en) Method for making a high density ROM or EPROM integrated circuit
JPH07211795A (en) Method of manufacturing semiconductor memory device
JP3154850B2 (en) Photoelectric conversion device and method of manufacturing the same
JPH01259565A (en) Thin film transistor and its manufacturing method
JP3123722B2 (en) Method of manufacturing thin film semiconductor transistor and thin film transistor
JPH0732245B2 (en) Photosensor manufacturing method
JP2831997B2 (en) Method for manufacturing semiconductor device
KR19990036598A (en) Capacitors in Semiconductor Integrated Circuits and Manufacturing Method Thereof
US5940703A (en) Method for manufacturing DRAM capacitors with T-shape lower electrodes by etching oxide sidewalls
JPH0732244B2 (en) Photo sensor
KR20020028014A (en) Method for fabricating tft-lcd
JPH08321621A (en) Thin film transistor
US5038190A (en) Photoelectric conversion device with disabled electrode
US6362102B1 (en) Method of forming top metal contact to antifuse
EP0304336A2 (en) Photoelectric conversion device and method for producing the same
JPH02226766A (en) Semiconductor device and photoelectric conversion device using same
JPH0394467A (en) Electronic circuit device

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

FEPP Fee payment procedure

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12