US5083294A - Semiconductor memory device having a redundancy - Google Patents
Semiconductor memory device having a redundancy Download PDFInfo
- Publication number
- US5083294A US5083294A US07/562,512 US56251290A US5083294A US 5083294 A US5083294 A US 5083294A US 56251290 A US56251290 A US 56251290A US 5083294 A US5083294 A US 5083294A
- Authority
- US
- United States
- Prior art keywords
- memory cell
- redundant
- column
- cell array
- main memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
- G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
Abstract
Description
U=Y.sub.cell ×Y.sub.PER
Y.sub.cell =(Y.sub.BLOCK).sup.n
Y.sub.cell =exp(-Aδ)
Y.sub.BLOCK =exp(-Aδ/n)+Aδ/n.exp(-Aδ/n).
Y.sub.cell =(Y.sub.BLOCK).sup.n =(1+Aδ/n).sup.n exp(-Aδ) (1)
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1-203001 | 1989-08-04 | ||
JP20300189 | 1989-08-04 |
Publications (1)
Publication Number | Publication Date |
---|---|
US5083294A true US5083294A (en) | 1992-01-21 |
Family
ID=16466688
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/562,512 Expired - Lifetime US5083294A (en) | 1989-08-04 | 1990-08-03 | Semiconductor memory device having a redundancy |
Country Status (5)
Country | Link |
---|---|
US (1) | US5083294A (en) |
EP (1) | EP0411626B1 (en) |
JP (1) | JP2545490B2 (en) |
KR (1) | KR940007946B1 (en) |
DE (1) | DE69023181T2 (en) |
Cited By (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5193074A (en) * | 1990-02-09 | 1993-03-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having hierarchical row selecting lines |
US5222047A (en) * | 1987-05-15 | 1993-06-22 | Mitsubishi Denki Kabushiki Kaisha | Method and apparatus for driving word line in block access memory |
US5249158A (en) * | 1991-02-11 | 1993-09-28 | Intel Corporation | Flash memory blocking architecture |
US5299164A (en) * | 1992-02-24 | 1994-03-29 | Kabushiki Kaisha Toshiba | Semiconductor memory device having redundant circuit |
US5347484A (en) * | 1992-06-19 | 1994-09-13 | Intel Corporation | Nonvolatile memory with blocked redundant columns and corresponding content addressable memory sets |
US5355337A (en) * | 1991-08-21 | 1994-10-11 | Samsung Electronics Co., Ltd. | Arrangement of redundant cell array for semiconductor memory device |
US5359572A (en) * | 1991-04-23 | 1994-10-25 | Hitachi, Ltd. | Semiconductor storage device |
US5381370A (en) * | 1993-08-24 | 1995-01-10 | Cypress Semiconductor Corporation | Memory with minimized redundancy access delay |
US5386386A (en) * | 1990-03-22 | 1995-01-31 | Kabushiki Kaisha Toshiba | Redundancy circuit having a spare memory block replacing defective memory cells in different blocks |
US5414660A (en) * | 1992-10-01 | 1995-05-09 | Nec Corporation | Double word line type dynamic RAM having redundant sub-array of cells |
US5424987A (en) * | 1992-09-29 | 1995-06-13 | Nec Corporation | Semiconductor memory device having redundant memory cells and circuit therefor |
US5426608A (en) * | 1993-09-20 | 1995-06-20 | Fujitsu Limited | Word line redundancy nonvolatile semiconductor memory |
US5438546A (en) * | 1994-06-02 | 1995-08-01 | Intel Corporation | Programmable redundancy scheme suitable for single-bit state and multibit state nonvolatile memories |
US5493241A (en) * | 1994-11-16 | 1996-02-20 | Cypress Semiconductor, Inc. | Memory having a decoder with improved address hold time |
US5519657A (en) * | 1993-09-30 | 1996-05-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having a redundant memory array and a testing method thereof |
US5555212A (en) * | 1994-09-19 | 1996-09-10 | Kabushiki Kaisha Toshiba | Method and apparatus for redundancy word line replacement in a semiconductor memory device |
US5574729A (en) * | 1990-09-29 | 1996-11-12 | Mitsubishi Denki Kabushiki Kaisha | Redundancy circuit for repairing defective bits in semiconductor memory device |
US5596536A (en) * | 1992-12-30 | 1997-01-21 | Hyundai Electronics Industries Co., Ltd. | Redundancy circuit |
US5689463A (en) * | 1994-10-04 | 1997-11-18 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US5712664A (en) * | 1993-10-14 | 1998-01-27 | Alliance Semiconductor Corporation | Shared memory graphics accelerator system |
US5768196A (en) * | 1996-03-01 | 1998-06-16 | Cypress Semiconductor Corp. | Shift-register based row select circuit with redundancy for a FIFO memory |
US5793942A (en) * | 1996-03-26 | 1998-08-11 | Lucent Technologies Inc. | Memory chip architecture and packaging method for increased production yield |
US5875148A (en) * | 1993-01-29 | 1999-02-23 | Oki Electric Industry Co., Ltd. | Semiconductor memory |
US5875149A (en) * | 1997-02-06 | 1999-02-23 | Hyndai Electronics America | Word line driver for semiconductor memories |
US6011746A (en) * | 1997-02-06 | 2000-01-04 | Hyundai Electronics America, Inc. | Word line driver for semiconductor memories |
US6023441A (en) * | 1995-08-30 | 2000-02-08 | Intel Corporation | Method and apparatus for selectively enabling individual sets of registers in a row of a register array |
US6041010A (en) * | 1994-06-20 | 2000-03-21 | Neomagic Corporation | Graphics controller integrated circuit without memory interface pins and associated power dissipation |
US6049641A (en) * | 1998-02-24 | 2000-04-11 | Gemfire Corporation | Connection system for optical redundancy |
US20040233716A1 (en) * | 1999-01-14 | 2004-11-25 | Agate Semiconductor, Inc. | Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
US20080291760A1 (en) * | 2007-05-23 | 2008-11-27 | Micron Technology, Inc. | Sub-array architecture memory devices and related systems and methods |
US20090168572A1 (en) * | 2005-03-24 | 2009-07-02 | Tomoyuki Shibata | Semiconductor memory |
US20090285035A1 (en) * | 2008-05-16 | 2009-11-19 | Tyler Lee Brandon | Pipelined wordline memory architecture |
US7821866B1 (en) | 2007-11-14 | 2010-10-26 | Cypress Semiconductor Corporation | Low impedance column multiplexer circuit and method |
US7888962B1 (en) | 2004-07-07 | 2011-02-15 | Cypress Semiconductor Corporation | Impedance matching circuit |
US8036846B1 (en) | 2005-10-20 | 2011-10-11 | Cypress Semiconductor Corporation | Variable impedance sense architecture and method |
US20210202024A1 (en) * | 2019-12-30 | 2021-07-01 | Micron Technology, Inc. | Memory redundancy repair |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
IT1256664B (en) | 1992-12-28 | 1995-12-12 | Spherilene Srl | BITUMINOUS COMPOSITIONS MODIFIED WITH POLYOLEFINIC MATERIALS. |
JPH08227597A (en) * | 1995-02-21 | 1996-09-03 | Mitsubishi Electric Corp | Semiconductor storage device |
GB2292236A (en) * | 1995-04-04 | 1996-02-14 | Memory Corp Plc | Improved partial memory engine |
US5621690A (en) * | 1995-04-28 | 1997-04-15 | Intel Corporation | Nonvolatile memory blocking architecture and redundancy |
JP4111486B2 (en) * | 2002-01-31 | 2008-07-02 | シャープ株式会社 | Semiconductor memory device and electronic information device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4918662A (en) * | 1987-03-27 | 1990-04-17 | Nec Corporation | Semiconductor memory device having redundant structure for segmented word line arrangement |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4422161A (en) * | 1981-10-08 | 1983-12-20 | Rca Corporation | Memory array with redundant elements |
EP0198935A1 (en) * | 1985-04-23 | 1986-10-29 | Deutsche ITT Industries GmbH | Electrically erasable programmable redundant semiconductor memory |
JPS62149095A (en) * | 1986-12-12 | 1987-07-03 | Mitsubishi Electric Corp | Semiconductor memory device |
JP2590897B2 (en) * | 1987-07-20 | 1997-03-12 | 日本電気株式会社 | Semiconductor memory |
-
1990
- 1990-08-02 EP EP90114851A patent/EP0411626B1/en not_active Expired - Lifetime
- 1990-08-02 DE DE69023181T patent/DE69023181T2/en not_active Expired - Fee Related
- 1990-08-03 JP JP2206021A patent/JP2545490B2/en not_active Expired - Lifetime
- 1990-08-03 US US07/562,512 patent/US5083294A/en not_active Expired - Lifetime
- 1990-08-04 KR KR1019900011972A patent/KR940007946B1/en not_active IP Right Cessation
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4918662A (en) * | 1987-03-27 | 1990-04-17 | Nec Corporation | Semiconductor memory device having redundant structure for segmented word line arrangement |
Cited By (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5222047A (en) * | 1987-05-15 | 1993-06-22 | Mitsubishi Denki Kabushiki Kaisha | Method and apparatus for driving word line in block access memory |
US5371714A (en) * | 1987-05-15 | 1994-12-06 | Mitsubishi Denki Kabushiki Kaisha | Method and apparatus for driving word line in block access memory |
US5193074A (en) * | 1990-02-09 | 1993-03-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having hierarchical row selecting lines |
US5386386A (en) * | 1990-03-22 | 1995-01-31 | Kabushiki Kaisha Toshiba | Redundancy circuit having a spare memory block replacing defective memory cells in different blocks |
US5574729A (en) * | 1990-09-29 | 1996-11-12 | Mitsubishi Denki Kabushiki Kaisha | Redundancy circuit for repairing defective bits in semiconductor memory device |
US5249158A (en) * | 1991-02-11 | 1993-09-28 | Intel Corporation | Flash memory blocking architecture |
US5359572A (en) * | 1991-04-23 | 1994-10-25 | Hitachi, Ltd. | Semiconductor storage device |
US5355337A (en) * | 1991-08-21 | 1994-10-11 | Samsung Electronics Co., Ltd. | Arrangement of redundant cell array for semiconductor memory device |
US5299164A (en) * | 1992-02-24 | 1994-03-29 | Kabushiki Kaisha Toshiba | Semiconductor memory device having redundant circuit |
US5347484A (en) * | 1992-06-19 | 1994-09-13 | Intel Corporation | Nonvolatile memory with blocked redundant columns and corresponding content addressable memory sets |
US5424987A (en) * | 1992-09-29 | 1995-06-13 | Nec Corporation | Semiconductor memory device having redundant memory cells and circuit therefor |
US5414660A (en) * | 1992-10-01 | 1995-05-09 | Nec Corporation | Double word line type dynamic RAM having redundant sub-array of cells |
US5596536A (en) * | 1992-12-30 | 1997-01-21 | Hyundai Electronics Industries Co., Ltd. | Redundancy circuit |
US5875148A (en) * | 1993-01-29 | 1999-02-23 | Oki Electric Industry Co., Ltd. | Semiconductor memory |
US5381370A (en) * | 1993-08-24 | 1995-01-10 | Cypress Semiconductor Corporation | Memory with minimized redundancy access delay |
US5426608A (en) * | 1993-09-20 | 1995-06-20 | Fujitsu Limited | Word line redundancy nonvolatile semiconductor memory |
US5519657A (en) * | 1993-09-30 | 1996-05-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having a redundant memory array and a testing method thereof |
US6317135B1 (en) | 1993-10-14 | 2001-11-13 | Alliance Semiconductor Corporation | Shared memory graphics accelerator system |
US6081279A (en) * | 1993-10-14 | 2000-06-27 | Alliance Semiconductor Corporation | Shared memory graphics accelerator system |
US5712664A (en) * | 1993-10-14 | 1998-01-27 | Alliance Semiconductor Corporation | Shared memory graphics accelerator system |
US5438546A (en) * | 1994-06-02 | 1995-08-01 | Intel Corporation | Programmable redundancy scheme suitable for single-bit state and multibit state nonvolatile memories |
US20060208764A1 (en) * | 1994-06-20 | 2006-09-21 | Puar Deepraj S | Graphics Controller Integrated Circuit without Memory Interface |
US7106619B2 (en) | 1994-06-20 | 2006-09-12 | Neomagic Corporation | Graphics controller integrated circuit without memory interface |
US20050180225A1 (en) * | 1994-06-20 | 2005-08-18 | Neomagic Corporation | Graphics Controller Integrated Circuit without Memory Interface |
US6920077B2 (en) | 1994-06-20 | 2005-07-19 | Neomagic Corporation | Graphics controller integrated circuit without memory interface |
US20040179015A1 (en) * | 1994-06-20 | 2004-09-16 | Neomagic Corporation | Graphics controller integrated circuit without memory interface |
US6041010A (en) * | 1994-06-20 | 2000-03-21 | Neomagic Corporation | Graphics controller integrated circuit without memory interface pins and associated power dissipation |
US6771532B2 (en) | 1994-06-20 | 2004-08-03 | Neomagic Corporation | Graphics controller integrated circuit without memory interface |
US6356497B1 (en) | 1994-06-20 | 2002-03-12 | Neomagic Corporation | Graphics controller integrated circuit without memory interface |
US5555212A (en) * | 1994-09-19 | 1996-09-10 | Kabushiki Kaisha Toshiba | Method and apparatus for redundancy word line replacement in a semiconductor memory device |
US5689463A (en) * | 1994-10-04 | 1997-11-18 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US5493241A (en) * | 1994-11-16 | 1996-02-20 | Cypress Semiconductor, Inc. | Memory having a decoder with improved address hold time |
US6023441A (en) * | 1995-08-30 | 2000-02-08 | Intel Corporation | Method and apparatus for selectively enabling individual sets of registers in a row of a register array |
US5768196A (en) * | 1996-03-01 | 1998-06-16 | Cypress Semiconductor Corp. | Shift-register based row select circuit with redundancy for a FIFO memory |
US5793942A (en) * | 1996-03-26 | 1998-08-11 | Lucent Technologies Inc. | Memory chip architecture and packaging method for increased production yield |
US6011746A (en) * | 1997-02-06 | 2000-01-04 | Hyundai Electronics America, Inc. | Word line driver for semiconductor memories |
US5875149A (en) * | 1997-02-06 | 1999-02-23 | Hyndai Electronics America | Word line driver for semiconductor memories |
US6049641A (en) * | 1998-02-24 | 2000-04-11 | Gemfire Corporation | Connection system for optical redundancy |
US20110110170A1 (en) * | 1999-01-14 | 2011-05-12 | Hieu Van Tran | Non-volatile memory systems and methods including page read and/or configuration features |
US7035151B2 (en) * | 1999-01-14 | 2006-04-25 | Silicon Storage Technology, Inc. | Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
US9640263B2 (en) | 1999-01-14 | 2017-05-02 | Silicon Storage Technology, Inc. | Non-volatile memory systems and methods |
US8614924B2 (en) | 1999-01-14 | 2013-12-24 | Silicon Storage Technology, Inc. | Non-volatile memory systems and methods |
US8432750B2 (en) | 1999-01-14 | 2013-04-30 | Silicon Storage Technology, Inc. | Non-volatile memory systems and methods including page read and/or configuration features |
US20040233716A1 (en) * | 1999-01-14 | 2004-11-25 | Agate Semiconductor, Inc. | Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
US7888962B1 (en) | 2004-07-07 | 2011-02-15 | Cypress Semiconductor Corporation | Impedance matching circuit |
US7808848B2 (en) * | 2005-03-24 | 2010-10-05 | Elpida Memory, Inc. | Semiconductor memory |
US20090168572A1 (en) * | 2005-03-24 | 2009-07-02 | Tomoyuki Shibata | Semiconductor memory |
US8036846B1 (en) | 2005-10-20 | 2011-10-11 | Cypress Semiconductor Corporation | Variable impedance sense architecture and method |
US20080291760A1 (en) * | 2007-05-23 | 2008-11-27 | Micron Technology, Inc. | Sub-array architecture memory devices and related systems and methods |
US7821866B1 (en) | 2007-11-14 | 2010-10-26 | Cypress Semiconductor Corporation | Low impedance column multiplexer circuit and method |
US20090285035A1 (en) * | 2008-05-16 | 2009-11-19 | Tyler Lee Brandon | Pipelined wordline memory architecture |
US20210202024A1 (en) * | 2019-12-30 | 2021-07-01 | Micron Technology, Inc. | Memory redundancy repair |
US11710531B2 (en) * | 2019-12-30 | 2023-07-25 | Micron Technology, Inc. | Memory redundancy repair |
Also Published As
Publication number | Publication date |
---|---|
EP0411626A3 (en) | 1992-01-02 |
EP0411626A2 (en) | 1991-02-06 |
KR910005320A (en) | 1991-03-30 |
DE69023181T2 (en) | 1996-04-18 |
JP2545490B2 (en) | 1996-10-16 |
EP0411626B1 (en) | 1995-10-25 |
DE69023181D1 (en) | 1995-11-30 |
JPH03162799A (en) | 1991-07-12 |
KR940007946B1 (en) | 1994-08-29 |
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Legal Events
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Owner name: FUJITSU LIMITED, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:OKAJIMA, YOSHINORI;REEL/FRAME:005427/0164 Effective date: 19900802 |
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