JPH08227597A - Semiconductor storage device - Google Patents

Abstract

PURPOSE: To reduce current consumption at the time of standby. CONSTITUTION: A cell plate CP corresponding to each memory array block MB is provided in a DRAM which has plural memory array blocks MB,... each of which has plural subword lines SWL1,... connected to the main word line MWL. In addition, a fuse F1 is provided between the cell plate potential feeding line VCP which feeds the cell plate potential to the cell plate of each memory array block MB and the cell plate CP. The supply of the cell plate potential to the memory array block having failed is interrupted by cutting the fuse F1. By this, current consumption at the time of standby can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (hereinafter referred to as DRAM) having divided word lines.

[0002]

2. Description of the Related Art FIG. 12 is a circuit diagram showing a structure of a main part of a conventional DRAM having divided word lines.

Referring to FIG. 12, this DRAM has a memory cell array 1, a plurality of main word lines MWL, ..., A spare main word line SMWL, and a plurality of sub word lines SW.
L1 to SWL4, ..., Multiple main word drivers 3
, A plurality of sub-word drivers 31 to 34, a plurality of bit line pairs BL, / BL, ..., A plurality of sense amplifiers 51, ... And an equalize circuit EQ.

The memory cell array 1 includes a plurality of memory cells MC, MC, .... In the memory cell array 1, a plurality of main word lines MWL, ... And a spare main word line SMWL are arranged in parallel.

A plurality of main word lines MWL, ... Are respectively driven by corresponding main word drivers 3M ,. Spare main word line SMWL is driven by spare main word driver 3S.
In the memory cell array 1, the main word line MWL
And a plurality of bit line pairs BL, / BL, ... Are arranged in a direction intersecting spare main word line SMWL.

The memory cell array 1 is divided into a plurality of memory array blocks MB, ... In units of a predetermined number of bit lines. One cell plate CP is provided corresponding to each memory array block MB. Therefore, in the memory cell array 1, the cell plate CP is divided into a plurality.

A plurality of sub-word lines SWL1 to SWL4 are provided corresponding to each of the plurality of main word lines MWL, ... And spare main word line SMWL. The set of sub-word lines SWL1 to SWL4 includes sub-word drivers 3
1 to 34 through one corresponding main word line MW
It is connected to L or spare main word line SMWL.
The sub word lines SWL1 to SWL4 are connected to the sub word driver 31.
Driven by the corresponding driver of ~ 34.

Each of the sub-word drivers 31 to 34 corresponding to each set of sub-word lines SWL1 to SWL4 is an AND gate and receives the following input signals.

Sub word driver 31 receives the potential of corresponding main word line MWL or spare word line SMWL and decode signal X4 based on the row address.
The sub word driver 32 has a corresponding main word line M.
It receives the potential of WL or spare main word line SMWL and decode signal X3 based on the row address.

The sub word driver 33 has a corresponding main word line MWL or spare main word line SMWL.
And the decode signal X2 based on the row address. Sub word driver 34 receives the potential of corresponding main word line MWL or spare main word line SMWL and decode signal X2 based on the row address.
The decode signals X1 to X4 are generated by a decode circuit described later.

A plurality of sense amplifiers 51, ... Are provided corresponding to each pair of a plurality of bit line pairs BL, / BL ,. Each bit line pair BL, / BL is connected to the corresponding sense amplifier 51 via the transistors T4, T5.
Connected to. Each sense amplifier 51 is for sensing and amplifying the potential difference between the corresponding bit line pair BL, / BL.

Further, an equalize circuit EQ is provided corresponding to each bit line pair BL, / BL. Each equalize circuit EQ is for equalizing the potentials of the corresponding bit line pair BL, / BL, and includes three N channel MOSs.
Transistor (hereinafter called NMOS transistor) T1
~ Including T3. In each equalize circuit EQ, the transistor T1 is connected between the bit line pair BL, / BL, and the transistors T2 and T3 are connected between the bit line pair BL, / BL.
/ BL is connected in series.

The spare main word line SMWL is for relieving the defective main word line MWL. The defective main word line MWL is replaced with the spare main word line SMWL in the operation. The replacement is performed by the spare main word driver 3S activating the spare main word line SMWL in place of the main word driver 3M corresponding to the defective main word line MWL.

In other words, in this DRAM,
Replacement is performed in units of main word drivers. Since the replacement is performed in units of the main word driver in this manner, the main word line MWL is replaced even if a defect occurs only in the sub word line SWL.

In the DRAM thus constructed, potential supply lines and signal lines are wired as follows in order to supply various potentials and various signals to each section.

The cell plate potential supply line VC is arranged along the plurality of memory array blocks MB, ... Of the memory cell array 1.
P is extended. A cell plate potential is supplied from the potential supply line VCP to the cell plate CP of each memory array block MB.

A plurality of bit line connection / disconnection signal lines BLI for supplying a bit line connection / disconnection signal for controlling connection / disconnection between the corresponding bit line pair BL, / BL and the sense amplifier 51. The memory array blocks MB, ... From the signal line BLI to each bit line pair BL,
Signals for controlling the transistors T4 and T5 corresponding to / BL are supplied to the respective gate electrodes thereof.

A sense amplifier activation signal line S0 for supplying a sense amplifier activation signal for activating sense amplifiers 51, ... Also extends along a plurality of memory array blocks MB ,. From the signal line S0 to the sense amplifier 5
A sense amplifier activation signal is supplied to each of 1, ....

A bit line equalize signal line BLEQ for supplying a bit line equalize signal for equalizing the bit line pair BL, / BL, ... Also extends along a plurality of memory array blocks MB ,. A bit line equalize signal is supplied from the signal line BLEQ to the gate electrodes of the transistors T1 to T3 of each equalize circuit EQ.

The bit line equalize potential supply line VBL for supplying the equalize potentials of the bit line pairs BL, / BL, ... Also extends along the plurality of memory array blocks MB ,. The bit line equalize potential is supplied from the potential supply line VBL to the source electrodes of the transistors T2 and T3 of each equalize circuit EQ.

As described above, in the conventional DRAM,
Each of the potential supply lines VCP, VBL, the signal lines BLEQ, S0, and BLI has a plurality of memory array blocks MB,
One was provided for all of ... Therefore, each potential and each signal were supplied from one wiring.
In addition, the potential supply line VCP, the plurality of cell plates CP,
Each of ... Was directly connected.

Next, the decode signal X1 shown in FIG.
An example of the configuration of the decoding circuit for generating X4 will be described.

First, the DR of the address multiplex system
The configuration of the decoding circuit in AM will be described. The address multiplex system is a system in which a row address and a column address input to the DRAM are input at a predetermined time interval.

FIG. 13 is a circuit diagram showing a structure of a decode circuit of an address multiplex type DRAM. With reference to FIG. 13, this decoding circuit includes an AND gate 3
01-304 and inverters 305 and 306.

The address signal R1 based on the row address is
AND gates 301 and 3 via inverter 305
It is supplied to the input terminal of 03 and directly ANDed.
It is supplied to the gates 302 and 304. The address signal R2 based on the row address is supplied to the AND gates 301 and 302 via the inverter 306 and directly to the input terminals of the AND gates 303 and 304. The AND gates 301 to 304 output the decode signals X1 to X4 as outputs in response to the inputs, respectively.
Is output.

Next, the structure of the decoding circuit in the address non-multiplex type DRAM will be described. The address non-multiplex method is a method in which a row address and a column address are input at the same time.

FIG. 14 is a circuit diagram showing a structure of a decode circuit of an address non-multiplex type DRAM. Referring to FIG. 14, the decoding circuit includes AND gates 3010 to 3040 and inverters 3050 and 3060. Address signals R1 and R2 based on the input row address and a block selection signal BS based on the column address are input to the decoding circuit.

The address signal R1 is supplied to the inverter 3050.
Is supplied to the respective input terminals of the AND gates 3010 and 3030, and is also directly supplied to the respective input terminals of the AND gates 3020 and 3040. The address signal R2 is supplied to the input terminals of the AND gates 3010 and 3020 via the inverter 3060, and is also directly supplied to the input terminals of the AND gates 3030 and 3040.

The block selection signal BS is directly ANDed.
It is supplied to the respective input terminals of the gates 3010 to 3040. AND gates 3010 to 3040 output decode signals X1 to X4 as outputs for their respective inputs.

Next, the structure of the memory cell MC shown in FIG. 12 will be described. FIG. 15 is a circuit diagram showing the configuration of a memory cell of DRAM. Referring to FIG. 15, the memory cell MC includes a transfer gate transistor TR.
And a capacitor C.

Transfer gate transistor TR
Is connected between one of the bit line pair BL, / BL and one electrode of the capacitor C. The gate electrode of the transfer gate transistor TR has a sub word line S.
Connected to WL. The other electrode of the capacitor C is connected to the cell plate CP. In the memory cell MC having such a configuration, when the sub word line SWL is activated, the writing to the capacitor C or the capacitor C is performed.
Is read.

Next, a method of replacing a word line in such a conventional DRAM will be described. FIG. 16 is a block diagram showing a structure of a conventional DRAM in which word lines can be replaced. 16, the same parts as those in FIG. 12 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

Referring to FIG. 16, this DRAM includes a memory cell array 1, a plurality of main word lines MWL1 and MWL2,
Spare main word lines SMWL, sub word lines SWL11 to SWL22, spare sub word lines SS
WL1 and WL2, a plurality of bit line pairs BLP1 and BLP2, a plurality of main word drivers 3Ma and 3Mb, a spare main word driver 3S, and a plurality of sub word drivers G1.
1 to G22, a plurality of spare sub-word drivers SG1,
SG2, normal row decoder 30M, spare row decoder 30S, a plurality of segment drivers 61 and 62, address comparison circuit 600, normal deactivation signal generation circuit 60.
4 and a spare activation signal generation circuit 605.

The memory cell array 1 is divided into a plurality of memory array blocks MB1 and MB2. Main word lines MWL1 and MWL2 and spare main word line SMWL pass through memory array blocks MB1 and MB2, respectively.

Memory array block MB1 includes sub word lines SWL11 to SWL21 and spare sub word line SS.
WL1, bit line pair BLP1, memory cells MC, MC,
Spare memory cell MC1, sub-word driver G11,
Includes G21 and spare subword driver SG1.
A segment driver 61 is provided corresponding to the memory array block MB1.

The memory array block MB2 includes sub word lines SWL12 to SWL22 and a spare sub word line SS.
WL2, bit line pair BLP2, memory cells MC, MC,
Spare memory cell MC2, sub word driver G12,
G22 and spare subword driver SG2 are included.
A segment driver 62 is provided corresponding to the memory array block MB2.

The sub word line SWL11 is connected to the main word line MWL1 via the sub word driver G11, and the sub word line SLW12 is connected to the main word line MWL1 via the sub word driver G12. The main word line MWL2 is connected to the sub word line S via the sub word driver G21.
The WL21 is connected, and the sub-word line SWL22 is connected via the sub-word driver G22.

The spare subword line SSWL is connected to the spare subword line SSWL1 via the spare subword driver SG1.
The spare sub word line SSWL2 is connected via G2.

Each of segment drivers 61 and 62 outputs a signal for activating a sub word line and a spare sub word line of the corresponding memory array block when the corresponding memory array block is selected based on the column address.

Each of subword drivers G11 and G21 and spare subword driver SG21 is an AND gate and receives an output signal of segment word driver 61. Sub word driver G11, G21
Each of spare sub-word drivers SG1 activates the corresponding sub-word line in response to the level of the potential of the corresponding main word line (including the spare main word line) and the level of the output signal of segment word driver 61.

Sub-word lines SWL11 and SWL21,
Each intersection with bit line pair BLP1 and sub word line SW
A normal memory cell MC is arranged at each intersection of L12 and SWL22 and the bit line pair BLP2. Spare memory cells MC are provided at the intersections of spare subword line SSWL1 and bit line pair BLP1 and at the intersections of spare subword line SSWL2 and bit line pair BLP2, respectively.
1 is arranged.

Memory cell MC and spare memory cell M
Each of C1 is connected to a sub word line (including a spare sub word line) and a bit pair at each intersection.

Normal row decoder 30M receives row address RA and outputs a signal for selectively operating one main word driver. Spare row decoder 30
S receives the row address RA and receives the spare word driver 3
A signal for operating S is output.

The address comparison circuit 600 is programmed with a defective row address. Address comparison circuit 6
00 receives the row address RA and compares the row address with the programmed row address.

Then, the address comparison circuit 600 sets the output signal to the first level when the row addresses match, and sets the output signal to the second level when the row addresses do not match. Address comparison circuit 60
The output signal of 0 is the normal deactivation signal generation circuit 604.
And spare activation signal generation circuit 605.

The normal deactivation signal generating circuit 604 is
The level of the signal received from the address comparison circuit 600 is the first
The output signal is at the L level when
The level of the signal received from the address comparison circuit 600 is the second level.
If it is the level of, the output signal is set to the H level. The output signal of normal deactivation signal generation circuit 604 is applied to main word drivers 3Ma and 3Mb, respectively.

Spare activation signal generation circuit 605 raises the output signal to H level when the level of the signal received from address comparison circuit 600 is the first level, while the level of the signal received from address comparison circuit 600 is high. Is the second level, the output signal is set to the L level. The output signal of spare activation signal generation circuit 605 is applied to spare main word driver 3S.

Main word drivers 3Ma and 3Mb
Receive the output signal of normal row decoder 30M and the output signal of normal deactivation signal generation circuit 604. Main word driver 3Ma activates main word line MWL1 when the received signals are both at H level. Main word driver 3Mb activates main word line MWL2 when the received signals are both at H level.

Spare main word driver 3S receives an output signal of spare row decoder 30S and an output signal of spare activation signal generating circuit 605. Spare main word driver 3S activates spare main word line SMWL when both received signals are at H level.

In the address comparison circuit 600, when the programmed row address and the input row address RA do not match, the normal deactivation signal generation circuit 60.
The output signal of 4 goes high and the output signal of spare activation signal generating circuit 605 goes low. In response to this, the main word driver corresponding to the row address RA activates the corresponding main word line.

On the other hand, when the row addresses do not match, the output signal of normal inactivation signal generating circuit 604 attains the L level and the output signal of spare activation signal generating circuit 605 attains the H level. In response to this, spare row decoder 30S activates spare main word line SMWL.

In the DRAM thus constructed, replacement is performed in units of main word lines when a defect occurs. That is, in operation, spare word driver 3S is replaced with the main word driver associated with the defective portion (main word line or sub word line). Therefore, spare sub word lines SWL11-SWL
Even if a defect occurs in any of WL22, replacement is performed in units of main word lines.

[0053]

The conventional DRAM having the divided word lines described above has the following problems.

In the conventional DRAM as shown in FIG. 12,
In the memory cell array 1, sub word lines SWL1 to SW
When L4 and the bit line pair BL, / BL are short-circuited, the potential supply line VBL to the main word line MWL G
A leak path to the ND potential is formed.

In the memory cell array 1, when the cell plate CP and the bit line pair BL, / BL are short-circuited, the potential supply line VCP to the main word line MWL.
A leak path to the GND potential of is formed.

When such a state occurs, the standby current, which is a current generated during standby, becomes larger than the specified value. This causes a problem that the DRAM chip becomes a defective product.

Further, the conventional DRAM shown in FIG.
In the method of replacing the word line in (1), replacement is performed in units of main word lines even when a defect occurs only in the sub word line. Therefore, there is a problem that the efficiency of replacement is low (bad).

An object of the present invention is to reduce the standby current of DRAM having divided word lines. Another object of the present invention is to increase the replacement efficiency of word lines when a defect occurs in a DRAM having divided word lines. Still another object of the present invention is to speed up the operation of a DRAM having divided word lines.

[0059]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising a memory cell array, a plurality of main word lines, a cell plate potential supply line, and a plurality of interruption means.

The memory cell array has a plurality of dynamic type memory cells and is divided into a plurality of memory array blocks. The plurality of main word lines pass through the plurality of memory array blocks.

Each of the plurality of memory cells includes a memory transistor and a memory capacitor. Each of the plurality of memory array blocks includes a plurality of sub word lines and a cell plate. The plurality of sub word lines are connected to a plurality of memory cells in the memory array block, and
It is connected to each of a plurality of main word lines. The cell plate is divided into a plurality of portions corresponding to the plurality of memory array blocks, and forms a common electrode of the memory capacitors of the plurality of memory cells in one memory array block.

The cell plate potential supply line supplies the cell plate potential to each cell plate of the plurality of memory array blocks. The plurality of cutoff means are respectively provided between the cell plates of the plurality of memory array blocks and the cell plate potential supply line, and cut off the supply of the cell plate potential to the defective memory array block. Is.

The present invention according to claim 2 is a semiconductor memory device, comprising a memory cell array, a plurality of main word lines, a plurality of bit line pairs, a plurality of equalizing means, a main equalizing control signal supply line, and a plurality of sub-lines. An equalizing control signal supply line and a plurality of interruption means are provided.

The memory cell array has a plurality of dynamic type memory cells and is divided into a plurality of memory array blocks. The plurality of main word lines pass through the plurality of memory array blocks. The plurality of bit line pairs are provided in each of the plurality of memory array blocks in a direction intersecting with the main word line and connected to the plurality of memory cells in the corresponding memory array block.

Each of the plurality of memory array blocks is connected to a plurality of memory cells in the memory array block and also to a plurality of main word lines.

The plurality of equalizing means are provided corresponding to each of the plurality of bit line pairs, and each is for equalizing the potential of the corresponding bit line pair.

The main equalize control signal supply line is provided along a plurality of memory array blocks and is for supplying an equalize control signal for controlling a plurality of equalize means.

The plurality of sub-equalize control signal supply lines are
Equalization supplied from the main equalization control signal supply line to each of a plurality of equalizing means provided corresponding to each of the plurality of memory array blocks and each of which equalizes a plurality of bit line pairs in the corresponding memory array block. It is for transmitting a control signal.

The plurality of cutoff means are provided corresponding to each of the plurality of sub-equalization control signal supply lines, and the main equalization control signal supply line to the sub-equalization control signal supply line corresponding to the defective memory array block is provided. This is for cutting off the supply of the equalize control signal from the.

According to a third aspect of the present invention, a memory cell array, a plurality of main word lines, a plurality of bit line pairs, a plurality of sense amplifier means, a plurality of switching means, a main switching control signal supply line, and a plurality of sub switchings. A control signal supply line and a plurality of interruption means are provided.

The memory cell array has a plurality of dynamic type memory cells and is divided into a plurality of memory array blocks. The plurality of main word lines pass through the plurality of memory array blocks. The plurality of bit line pairs are provided in each of the plurality of memory array blocks in a direction intersecting with the main word line and connected to the plurality of memory cells in the corresponding memory array block.

Each of the plurality of memory array blocks is connected to a plurality of memory cells in the memory array block and also to a plurality of main word lines.

The plurality of sense amplifier means are provided corresponding to each of the plurality of bit line pairs, and each senses and amplifies the potential difference between the corresponding bit line pairs. The plurality of switching means are respectively provided between the corresponding bit line pair and the sense amplifier means, and switch the connection state between them. The main switching control signal supply line is provided along the plurality of memory array blocks and supplies a switching control signal for controlling the plurality of switching means.

The plurality of sub-switching control signal supply lines are provided corresponding to each of the plurality of memory array blocks, and each of the plurality of switching means corresponding to the plurality of bit line pairs in the corresponding memory array block. For transmitting the switching control signal supplied from the main switching control signal supply line.

The plurality of cutoff means are provided corresponding to each of the plurality of sub-switching control signal supply lines, and the main switching control signal supply line to the sub-switching control signal supply line corresponding to the defective memory array block is provided. It is for cutting off the supply of the switching control signal from the.

The present invention according to claim 4 is a semiconductor memory device, comprising a memory cell array, a plurality of main word lines, a plurality of bit line pairs, a plurality of equalizing means, a main equalizing potential supply line, and a plurality of sub-equalizing. A potential supply line and a plurality of interruption means are provided.

The memory cell array has a plurality of dynamic memory cells and is divided into a plurality of memory array blocks. The plurality of main word lines pass through the plurality of memory array blocks. The plurality of bit line pairs are provided in each of the plurality of memory array blocks in a direction intersecting with the main word line and connected to the plurality of memory cells in the corresponding memory array block.

Each of the plurality of memory array blocks is connected to a plurality of memory cells in the memory array block and also to a plurality of main word lines.

The plurality of equalizing means are provided corresponding to each of the plurality of bit line pairs, and each is for equalizing the potential of the corresponding bit line pair. The main equalizing potential supply line is provided along the plurality of memory array blocks and supplies an equalizing potential for equalizing each of the plurality of bit line pairs.

A plurality of sub-equalization potential supply lines are provided corresponding to each of the plurality of memory array blocks, and each sub-equalizing potential supply line is provided to each of a plurality of equalizing means for equalizing a plurality of bit line pairs in the corresponding memory array block. , For transmitting the equalizing potential supplied from the main equalizing potential supply line.

A plurality of cutoff means are provided corresponding to each of the plurality of sub-equalization potential supply lines, and equalize from the main equalization potential supply line to the sub-equalization potential supply line corresponding to the defective memory array block. This is for cutting off the supply of electric potential.

The present invention according to claim 5 is a semiconductor memory device, comprising a memory cell array, a plurality of main word lines, a plurality of bit line pairs, a plurality of sense amplifier means, a main sense amplifier activation signal supply line, A plurality of sub-sense amplifier activation signal supply lines and a plurality of cutoff means are provided.

The memory cell array has a plurality of dynamic type memory cells and is divided into a plurality of memory array blocks. The plurality of main word lines pass through the plurality of memory array blocks. The plurality of bit line pairs are provided in each of the plurality of memory array blocks in a direction intersecting with the main word line and connected to the plurality of memory cells in the corresponding memory array block.

Each of the plurality of memory array blocks has a plurality of sub-word lines connected to the plurality of memory cells in the memory array block and to the plurality of main word lines.

The plurality of sense amplifier means are provided corresponding to each of the plurality of bit line pairs, and each senses and amplifies the potential difference between the corresponding bit line pairs.

The main sense amplifier activation signal supply line is
It is provided along a plurality of memory array blocks and is for supplying a sense amplifier activation signal for activating a plurality of switching means.

A plurality of sub-sense amplifier activation signal supply lines are provided corresponding to a plurality of memory array blocks, and a plurality of sense amplifiers respectively corresponding to a plurality of bit line pairs in the corresponding memory array block. It is for transmitting the sense amplifier activation signal supplied from the main sense amplifier activation signal supply line to each of the means.

A plurality of cutoff means are provided corresponding to each of the plurality of sub-sense amplifier activation signal supply lines, and the main sense to the sub-sense amplifier activation signal supply line corresponding to the defective memory array block is performed. This is for cutting off the supply of the sense amplifier activation signal from the amplifier activation signal supply line.

The present invention according to claim 6 provides the following:
In the invention described in 2, 3, 4 or 5, all or some of the plurality of breaking means are fuse elements.

The present invention according to claim 7 relates to claim 1,
In the invention described in 2, 3, 4 or 5, all or some of the plurality of breaking means are transistor elements.

The present invention described in claim 8 is, in the invention described in claim 7, characterized in that the operation of the transistor element is controlled by a signal for selecting a plurality of memory array blocks.

According to a ninth aspect of the present invention, in the invention according to the seventh aspect, the operation of the transistor element is controlled by a signal indicating a result of determination as to whether the corresponding memory array block is in a defective state. It is characterized by

The present invention according to claim 10 provides the invention according to claim 2,
In the invention described in 3 or 5, all or a part of the plurality of blocking means are logic means.

The present invention according to claim 11 is the tenth aspect.
In the invention described in (3), the logic means receives a signal from the corresponding signal supply line and a signal indicating a determination result of whether or not the corresponding memory array block is in a defective state, and responds to the signals. The operation is controlled.

A twelfth aspect of the present invention is a semiconductor memory device, comprising a memory cell array, a plurality of normal main word lines, a redundant main word line, a plurality of normal subword line activation means and a plurality of redundant subword line activations. Equipped with a conversion means.

The memory cell array has a plurality of memory cells and is divided into a plurality of memory array blocks.
The plurality of normal main word lines pass through the plurality of memory array blocks. The redundant main word line passes through a plurality of memory array blocks.

Each of the plurality of memory array blocks includes a plurality of normal subword lines, a plurality of normal memory cells, redundant subword lines and redundant memory cells.

The plurality of normal sub-word lines are connected to each of the plurality of normal main word lines. The plurality of normal memory cells are connected to the respective normal subword lines. The redundant sub word line is connected to the redundant main word line and is replaced with the defective normal sub word line.
The redundant memory cell is connected to the redundant sub word line.

The plurality of normal subword line activation means are provided corresponding to each of the plurality of memory array blocks, and each activates the plurality of normal subword lines in the corresponding memory array block. is there.

A plurality of redundant subword line activating means are provided corresponding to each of the plurality of memory array blocks, and each of them has a redundant subword line instead of a normal subword line in which a defect occurs in the corresponding memory array block. Is for activating.

The present invention according to claim 13 provides the invention according to claim 12.
In the invention described in (1), a redundant main word line activation means for always activating the redundant main word line is further provided.
Further, each of the plurality of redundant sub-word line selecting means receives an address for selecting a normal sub-word line, and activates the corresponding redundant sub-word line in response to the address.

The present invention according to claim 14 relates to claim 12.
In the invention described in (1), a column address is input after a row address including an address for selecting a normal subword line to be activated is input, and a plurality of normal subword line activating means and a plurality of redundant subword line activating means are It is characterized in that a plurality of corresponding normal subword lines and corresponding redundant subword lines are respectively selected in relation to the row address.

The present invention according to claim 15 provides the invention according to claim 12.
In the invention described in (1), a row address and a column address are input at the same time, and a plurality of normal subword line activating means and a plurality of redundant subword line activating means are associated with a plurality of corresponding normal addresses in relation to the row address or the column address. The sub-word line and the redundant sub-word line are selected respectively.

The present invention according to claim 16 provides a method according to claim 12.
In the invention described in [1], the memory cell array further includes a redundant memory array block, and the redundant memory array block is connected to a plurality of spare subword lines respectively connected to a plurality of normal main word lines and a plurality of spare subword lines. And a plurality of spare memory cells.

Further, a spare sub word line selection means is provided. The spare sub-word selection means activates a plurality of spare sub-word lines connected to the normal main word line to which the normal sub-word line is connected, instead of the normal sub-word line in which a defect occurs in one of the memory array blocks. It is for doing.

Further, the normal subword line in each of the plurality of memory array blocks is replaced by the redundant subword line in the corresponding memory array block or the spare subword line connected to the corresponding normal main word line.

A seventeenth aspect of the present invention is a semiconductor memory device, comprising a memory cell array, a normal main word line, a plurality of sense amplifier means, a plurality of switching means and an address comparison control means.

The memory cell array has a plurality of memory cells and is divided into a plurality of normal memory array blocks and redundant memory array blocks. The normal main word line passes through a plurality of normal memory array blocks and redundant memory array blocks.

Each of the plurality of normal memory array blocks includes a plurality of normal subword lines, a plurality of normal memory cells and a pair of normal bit lines. The plurality of regular sub word lines are connected to each of the regular main word lines. The plurality of normal memory cells are connected to the respective normal subword lines. The normal bit line pair is provided so as to intersect with the normal main word lines, and the data from the normal memory cells is selectively transmitted.

The redundant memory array block includes a plurality of redundant subword lines, a plurality of redundant memory cells and redundant bit line pairs.

The plurality of redundant sub word lines are connected to each of the plurality of normal main word lines. The plurality of redundant memory cells are connected to each of the plurality of redundant subword lines. The redundant bit line pair is provided so as to intersect the plurality of normal main word lines, and the data from the plurality of redundant memory cells is selectively transmitted.

Each of the plurality of redundant sub word lines is replaced with a defective normal sub word line connected to the corresponding main word line.

A plurality of sense amplifier means are provided corresponding to each of the normal bit line pair and the redundant bit line pair of the plurality of memory array blocks, and each senses and amplifies the potential difference of the corresponding bit line pair. To do.

The respective outputs of the plurality of sense amplifier means are transmitted to the input / output line pair. The plurality of switching means are respectively provided between the plurality of sense amplifier means and the input / output line pair, and are selectively turned on / off for selectively transmitting the outputs of the plurality of sense amplifier means to the input / output line pair.

The address comparison control means stores in advance an address corresponding to the normal subword line replaced with the redundant subword line, and compares the address with the address input to select the normal subword line. ,
When the addresses match, the plurality of switching means are controlled so that the output of the sense amplifier means corresponding to the redundant bit line pair is transmitted to the input / output line pair, and when the addresses do not match, , The plurality of switching means are controlled so that the output of the sense amplifier means corresponding to the normal bit line pair is transmitted to the input / output line pair.

Then, the amplification operation by the plurality of sense amplifier means and the address comparison operation by the address comparison control means are executed in parallel.

The present invention according to claim 18 is a semiconductor memory device comprising a memory cell array, a normal main word line, a plurality of sense amplifier means, a plurality of input / output line pairs, an address comparison means and a multiplexer means.

The memory cell array has a plurality of memory cells and is divided into a plurality of normal memory array blocks and redundant memory array blocks. The normal main word line passes through a plurality of normal memory array blocks and redundant memory array blocks.

Each of the plurality of normal memory array blocks includes a plurality of normal subword lines, a plurality of normal memory cells and a pair of normal bit lines. The plurality of regular sub word lines are connected to each of the regular main word lines. The plurality of normal memory cells are connected to the respective normal subword lines. The normal bit line pair is provided so as to intersect with the normal main word lines, and the data from the normal memory cells is selectively transmitted.

The redundant memory array block includes a plurality of redundant subword lines, a plurality of redundant memory cells and redundant bit line pairs.

The plurality of redundant sub word lines are connected to each of the plurality of normal main word lines. The plurality of redundant memory cells are connected to each of the plurality of redundant subword lines. The redundant bit line pair is provided so as to intersect the plurality of normal main word lines, and the data from the plurality of redundant memory cells is selectively transmitted.

Each of the plurality of redundant subword lines is replaced with a defective normal subword line connected to the corresponding main word line.

A plurality of sense amplifier means are provided corresponding to each of the normal bit line pair and the redundant bit line pair of the plurality of memory array blocks, and each senses / amplifies the potential difference of the corresponding bit line pair. To do.

The plurality of input / output line pairs are provided corresponding to each of the plurality of sense amplifier means, and the output of the sense amplifier means corresponding to each is transmitted.

The address comparison means stores in advance an address corresponding to the normal subword line replaced with the redundant subword line, compares the address with the address input to select the normal subword line, The comparison result is output.

The multiplexer means receives the information of the comparison result of the address comparing means, and when the compared addresses match, the multiplexer means of the input / output line pair to which the output of the sense amplifier means corresponding to the redundant bit line pair is transmitted. The potential difference is output, and if the compared addresses do not match, the potential difference of the input / output line pair to which the output of the sense amplifier means corresponding to the normal bit line is transmitted is output.

The amplifying operation by the plurality of sense amplifier means and the address comparing operation by the address comparing means are executed in parallel.

The present invention according to claim 19 is a semiconductor memory device comprising a memory cell array and a plurality of main word lines.

The memory cell array has a plurality of dynamic type memory cells. Multiple main word lines
It passes through the memory cell array.

The memory cell array is divided into a plurality of normal memory array blocks and a redundant memory array block which replaces the defective normal memory array block.

Each memory array block of the plurality of normal memory array blocks and the redundant memory array block is
It has a plurality of sub-word lines connected to a plurality of memory cells in the memory array block and to each of a plurality of main word lines.

In the refresh operation, the sub word line connected to the activated main word line is activated in all the memory array blocks of the normal memory array block and the redundant memory array block.

The present invention according to claim 20 is a semiconductor memory device in which a row address and a column address are sequentially input, and a memory cell is selected in accordance with the row address and the column address. And a plurality of main word lines.

The memory cell array has a plurality of dynamic type memory cells. The plurality of main word lines pass through the memory cell array and are selected according to the row address.

Further, the memory cell array is divided into a plurality of normal memory array blocks and a redundant memory array block which replaces the defective normal memory array block.

Each memory array block of the plurality of normal memory array blocks and the redundant memory array block is
It has a plurality of sub-word lines connected to a plurality of memory cells in the memory array block and to each of a plurality of main word lines.

In the normal operation and the refresh operation, the sub word line connected to the activated main word line is activated in all the normal memory array blocks and the redundant memory array blocks.

A twenty-first aspect of the present invention is a semiconductor memory device in which a memory cell is selected according to a row address and a column address which are simultaneously input, and includes a memory cell array and a plurality of main word lines.

The memory cell array has a plurality of dynamic type memory cells. The plurality of main word lines pass through the memory cell array and are selected according to the row address.

Further, the memory cell array is divided into a plurality of normal memory array blocks and a redundant memory array block which replaces the defective normal memory array block.

Each memory array block of the plurality of normal memory array blocks and the redundant memory array block is
It has a plurality of sub-word lines connected to a plurality of memory cells in the memory array block and to each of a plurality of main word lines.

In the refresh operation, the sub word line connected to the activated main word line is activated in all the normal memory array blocks and the redundant memory array blocks.

[0143]

According to the present invention described in claim 1, in a DRAM, a word line is divided into a main word line and a sub word line, and each of a plurality of memory array blocks has a sub word line. Then, the cell plate is divided into a plurality of sections corresponding to the plurality of memory array blocks.

Then, the cell plate potential of each memory array block is supplied from the cell plate potential supply line through the interruption means. The blocking means is
It is provided individually corresponding to each of the plurality of memory array blocks. Therefore, when a defect occurs in the memory array block, the supply of the cell plate potential may be interrupted by the interruption means corresponding to the memory array block.

As a result, even if a defect occurs in which the main word line and the cell plate are short-circuited, no current path is formed between the main word line and the cell plate potential supply line. Therefore, the current consumption during standby can be reduced.

According to the present invention as set forth in claim 2, a DRAM is provided.
In, the word line is divided into a main word line and a sub word line, and each of the plurality of memory array blocks has a sub word line. A signal line for supplying an equalizing signal for controlling the equalizing means provided corresponding to each memory array block is hierarchized into a main equalizing control signal supplying line and a plurality of sub-equalizing control signal supplying lines. Has been done.

The main equalize control signal supply line is provided along a plurality of memory array blocks in order to supply the equalize control signals to all the memory array blocks. The plurality of sub-equalization control signal supply lines are individually provided corresponding to each of the plurality of memory array blocks, and are connected to the main equalization control signal supply line through the corresponding cutoff means.

Therefore, when a memory array block is defective, the supply of the equalizing control signal to the equalizing means corresponding to the defective memory array block is cut off by the cutoff means corresponding to the memory array block. You can get drunk. Therefore, the current consumption during standby can be reduced.

According to the present invention described in claim 3, the DRA
In M, the word line is divided into a main word line and a sub word line, and each of the plurality of memory array blocks has a sub word line. A signal line for supplying a switching control signal for controlling the switching means between the bit line pair of each memory array block and the sense amplifier means corresponding to the bit line pair is a main switching control signal supply line and a plurality of sub switches. Control signal supply lines are layered.

The main switching control means supply line is provided along a plurality of memory array blocks in order to supply switching control signals to all the memory array blocks. The plurality of sub-switching control signal supply lines are individually provided corresponding to each of the plurality of memory array blocks, and are connected to the main switching control signal supply line via the corresponding cutoff means.

Therefore, when a defect occurs in the memory array block, the cutoff means corresponding to the memory array block cuts off the supply of the switching control signal to the switching means corresponding to the defective memory array block. You can get drunk. Therefore, the current consumption during standby can be reduced.

According to the present invention described in claim 4, DRA is provided.
In M, the word line is divided into a main word line and a sub word line, and each of the plurality of memory array blocks has a sub word line. Then, an equalizing potential supply line for supplying the equalizing potential of the bit line pair to the equalizing means provided corresponding to each memory array block is provided as a main equalizing potential supplying line and a plurality of sub equalizing potential supplying lines. It is layered.

The main equalizing potential supply line is provided along a plurality of memory array blocks in order to supply the equalizing potentials to all the memory array blocks.
The plurality of sub-equalize potential supply lines are individually provided corresponding to the plurality of memory array blocks, and are connected to the main equalize potential supply lines via the corresponding cutoff means.

Therefore, when a defect occurs in the memory array block, the supply of the equalizing potential to the equalizing unit corresponding to the defective memory array block is cut off by the cutoff unit corresponding to the memory array block. obtain.

As a result, even if a defect occurs in which the main word line and the bit line pair are short-circuited, no current path is formed between the main word line and the main equalizing potential supply line. Therefore, the current consumption during standby can be reduced.

According to the present invention described in claim 5, DRA is provided.
In M, the word line is divided into a main word line and a sub word line, and each of the plurality of memory array blocks has a sub word line. A signal line for supplying a sense amplifier activation signal for activating the sense amplifier means provided corresponding to the bit line pair of each memory array block is a main sense amplifier activation signal supply line,
It is layered into a plurality of sub-sense amplifier activation signal supply lines.

The main sense amplifier activation signal supply line is
It is provided along a plurality of memory array blocks in order to supply a sense amplifier activation signal to all the memory array blocks. The plurality of sub-sense amplifier activation signal supply lines are individually provided corresponding to the plurality of memory array blocks, and are connected to the main sense amplifier activation signal supply line through the corresponding cutoff means.

Therefore, when a defect occurs in the memory array block, the interrupting means corresponding to the memory array block sends the sense amplifier activation signal to the sense amplifier means corresponding to the defective memory array block. Supply can be cut off. Therefore, the current consumption during standby can be reduced.

According to the sixth aspect of the present invention, specifically, by configuring all or some of the plurality of breaking means by fuse elements, it is possible to reduce current consumption during standby.

According to the seventh aspect of the present invention, specifically, by configuring all or some of the plurality of interrupting means by transistor elements, it is possible to reduce current consumption during standby.

According to the present invention described in claim 8, specifically, a block for selecting the operation of the transistor elements forming all or a part of the plurality of cut-off means from each of the plurality of memory array blocks. By controlling with the selection signal, it is possible to reduce current consumption during standby.

According to the present invention as defined in claim 9, specifically, the operation of the transistor elements forming all or a part of the plurality of cutoff means is determined by whether or not the corresponding memory array block is in a defective state. By controlling with a signal indicating the determination result of, it is possible to reduce the current consumption during standby.

According to the tenth aspect of the present invention, specifically, by configuring all or part of the plurality of breaking means by the logic means, the current consumption during standby can be reduced.

According to the eleventh aspect of the present invention, specifically, the operation of the logic means constituting all or a part of the plurality of cutoff means is controlled by the signal from the corresponding signal supply line and the corresponding memory. By controlling in response to the signal indicating the determination result of whether the array block is in the defective state,
The current consumption during standby can be reduced.

According to the present invention of claim 12, DR
In the AM, a plurality of normal subword line activating means and a plurality of redundant subword line activating means are provided corresponding to each of the plurality of memory array blocks.

In each memory array block, the corresponding normal subword line activating means activates the normal subword line connected to the normal main word line, and the corresponding redundant subword line activating means operates the redundant main word line. The redundant sub word line connected to is activated.

When the normal subword line of the corresponding memory array block is defective, the redundant subword line activating means activates the redundant subword line of the corresponding memory array block instead. That is,
In each memory array block, when a defect occurs in the normal subword line, replacement is performed in subword line units.

According to the thirteenth aspect of the present invention, the redundant main word line of each memory array block is always activated by the redundant main word line activation means. When the normal subword line of each memory array block is defective, the redundant subword line of each memory array block is selected by the redundant subword line activating means responding to the address for selecting the memory array block. .

Therefore, in the access in the case where the normal subword line is replaced with the redundant subword line, the address related to the selection of the memory array block is not required in the address comparison operation for selecting the redundant main word line. The replaced redundant subword line can be selected only by selecting the responding redundant subword line. Therefore, the access speed can be increased.

According to the fourteenth aspect of the present invention, in the address multiplex type DRAM in which the column address is input after the row address including the address for selecting the normal sub-word line to be activated is input, A plurality of normal subword lines and corresponding redundant subword lines are selected in relation to the input row address. Therefore, in the address multiplex type DRAM, sub-word line units can be replaced in each memory array block.

According to the fifteenth aspect of the present invention, in an address non-multiplex type DRAM in which a row address and a column address are input at the same time, a plurality of normal subword lines and a plurality of normal subword lines are provided in association with the row address or the column address. Corresponding redundant sub-word lines are selected.
Therefore, address non-multiplex type DRAM
In, each memory array block can be replaced in units of sub word lines.

According to the sixteenth aspect of the present invention, there is provided the redundant memory array block including the spare sub-word line connected to each of the plurality of normal main word lines.

When a defect occurs in the normal subword line connected to the same normal main word line, each spare subword line is activated by the spare subword line selecting means in place of the defective normal subword line.

The defective normal subword line is replaced by a redundant subword line in the corresponding memory array block or a spare subword line connected to the normal main word line to which the normal subword line is connected.
Therefore, the degree of freedom of replacement of the regular sub word line is increased.

According to the seventeenth aspect of the present invention, the potential differences between the normal bit line pairs and the redundant bit line pairs are amplified by the plurality of sense amplifier means.
In parallel with the amplifying operation of the potential difference of each bit line pair, the address comparing operation by the address comparing control means is executed.

In the address comparison control means, when the prestored address corresponding to the replaced normal subword line and the address inputted for selecting the normal subword line match, the redundant bit line pair is detected. The plurality of switching means are controlled so that the output of the sense amplifier means corresponding to the above is selectively transmitted to the input / output line pair.

On the other hand, when the addresses do not match, the address comparison control means has a plurality of switching means so that the output of the sense amplifier means corresponding to the normal bit line pair is selectively transmitted to the input / output line pair. To control.

As described above, since the amplification operation by the sense amplifier means and the address comparison operation by the address comparison control means are performed in parallel, the operation speed can be increased.

According to the eighteenth aspect of the present invention, the plurality of sense amplifier means amplify the potential differences between the plurality of normal bit line pairs and the redundant bit line pairs.
Further, the outputs of those sense amplifier means are individually transmitted to the corresponding input / output line pairs.

In parallel with the amplification operation by each of the sense amplifier means, the address comparison operation by the address comparison means is executed.

In the address comparison control means, the address stored in advance and corresponding to the replaced normal subword line is compared with the address inputted for selecting the normal subword line. In the multiplexer means,
When the addresses compared by the address comparison unit match, the potential difference of the input / output line pair to which the output of the sense amplifier unit corresponding to the redundant bit line is transmitted is selectively output.

On the other hand, when the addresses do not match, the multiplexer means selectively outputs the potential difference of the input / output line pair to which the output of the sense amplifier means corresponding to the normal bit line pair is transmitted.

In this way, the amplification operation by the sense amplifier means and the address comparison operation by the address comparison means are performed in parallel. In other words, the data transmission operation of the input / output line pair and the address comparison operation are performed in parallel. Therefore, the operation can be speeded up.

According to the nineteenth aspect of the present invention, in the DRAM in which the word line is divided into the main word line and the sub word line, the memory cell array is divided into a plurality of normal memory array blocks and redundant memory array blocks. ing. The defective normal memory array block is replaced with the redundant memory array block.

Therefore, in a DRAM having divided word lines, when a sub word line is defective, sub word lines can be replaced in memory array block units.

In a general DRAM, only a row address is input during the refresh operation, and the word line is activated based on the row address. Then, the data in the memory cell connected to the activated main word line is refreshed.

In such a refresh operation, in each of the normal memory array block and the redundant memory array block, the sub word line connected to the activated main word line is activated. Therefore, proper refresh can be performed in a DRAM having a sub word line for each memory array block and a redundant memory array block.

According to the twentieth aspect of the present invention, the word line is divided into a main word line and a sub-word line, and an address at which a memory cell is selected according to a row address and a column address that are sequentially input. In a multiplex type DRAM, a memory cell array is divided into a plurality of normal memory array blocks and redundant memory array blocks. The defective normal memory array block is replaced with the redundant memory array block.

Therefore, in a DRAM having divided word lines, when a sub word line is defective, sub word lines can be replaced in memory array block units.

In a general DRAM, only the row address is input during the refresh operation, and the word line is activated based on the row address. And
The data in the memory cell connected to the activated main word line is refreshed.

In such a refresh operation, in each of the normal memory array block and the redundant memory array block, the sub word line connected to the activated main word line is activated. Therefore, proper refresh can be performed in the address multiplex type DRAM having a structure in which each memory array block has a sub word line and has a redundant memory array block.

Address multiplex type DRA
In M, when the row address is input and the main word line is activated, the column address is not yet input. In address multiplex type DRAM,
Even in the normal operation, the sub word line connected to the activated main word line is activated in all the normal and redundant memory array blocks.

Therefore, in an address multiplexer type DRAM having a sub word line for each memory array block and a redundant memory array block,
Appropriate normal operation can be performed according to the address input method.

According to the twenty-first aspect of the present invention, the word line is divided into a main word line and a sub-word line, and an address at which a memory cell is selected according to a row address and a column address inputted at the same time. In a non-multiplex type DRAM, a memory cell array is divided into a plurality of normal memory array blocks and redundant memory array blocks. The defective normal memory array block is replaced with the redundant memory array block.

Therefore, in a DRAM having divided word lines, when a defect occurs in a sub word line, the sub word line can be replaced in memory array block units.

In a general DRAM, only the row address is input during the refresh operation, and the word line is activated based on the row address. Then, the data in the memory cell connected to the activated main word line is refreshed.

In such a refresh operation, the sub word line connected to the activated main word line in each normal memory array block and all redundant memory array blocks is activated. Therefore, in the address non-multiplex type DRAM having the sub-word line for each memory array block and the redundant memory array block, proper refreshing can be performed.

Address non-multiplex type D
In the RAM, the column address is input when the row address is input. In the address non-multiplex type DRAM, the sub word line connected to the activated main word line is activated in the selected memory array block during the normal operation.

Therefore, in the address non-multiplexer type DRAM having the sub-word line for each memory array block and the redundant memory array block, proper normal operation can be performed according to the address input method. is there.

[0200]

Embodiments of the present invention will now be described in detail with reference to the drawings.

First Embodiment First, the overall structure of an address multiplex type DRAM and an address non-multiplex type DRAM to which the present invention is applied will be described.

First, the DR of the address multiplex system
AM will be described. FIG. 1 is a block diagram showing the overall configuration of an address multiplex type DRAM.

Referring to FIG. 1, this address multiplex type DRAM 100A includes a memory cell array 1,
Address buffer 2, row decoder 3, column decoder 4, sense refresh amplifier / input / output control circuit 5, clock generation circuit 6, lower input buffer 7L, upper input buffer 7U, lower output buffer 8L, upper output buffer 8U,
AND gates 11 and 12, signal input terminals 91 to 95, an address input terminal 96, a lower data input / output terminal 97 and an upper data input / output terminal 98 are included.

The memory cell array 1 has a plurality of memory cells and stores stored information. The address buffer 2 is
Address signal A from the outside via the address input terminal 96
Receive 0-A9. The address buffer 2 applies the received address signals A0 to A9 to the row decoder 3 as internal address signals, and also receives the received address signals A0 to A9.
7 is applied to the column decoder 4 as an internal address signal.

Row decoder 3 specifies a row of memory cell array 1 in response to a given address signal. A word line (not shown) is selected to make the designation. The column decoder 4 specifies a column of the memory cell array 1 in response to the applied address signal. A bit line pair (not shown) is selected for the designation.

In the read operation, the data read from the selected memory cell of the memory cell array 1 is transferred to the lower data input / output terminal via the sense refresh amplifier / input / output control circuit 5, the lower output buffer 8L and the upper output buffer 8U. 97 and upper data input / output terminal 98. The transmitted data is data DQ1 to DQ
Sixteen. The data transmitted to the lower data input / output terminal 97 and the upper data input / output terminal 98 are output to the outside.

In the write operation, the data DQ1 to DQ16 input from the lower data input / output terminal 97 and the upper data input / output terminal 98 are transferred to the lower input buffer 7L and the upper input buffer 7U, and the sense refresh amplifier / input / output control. It is written in the selected memory cell of the memory cell array 1 via the circuit 5.

This DRAM 100A is controlled by the row address strobe signal / R input from the signal input terminal 91.
AS, the lower column address strobe signal / LCAS input from the signal input terminal 92, the upper column address strobe signal / UCAS, the write designation signal / W input from the signal input terminal 94, and the signal input terminal 95. This is performed in response to output enable signal / OE.

Clock generation circuit 6 receives signal / RAS, signal / LCAS and signal / UCAS, and generates a clock signal in response to these signals. The clock signal output from the clock generation circuit 6 includes an address buffer 2, a row decoder 3, a column decoder 4, a sense refresh amplifier / input / output control circuit 5, a lower output buffer 8L,
It is applied to upper output buffer 8U and AND gates 11 and 12, respectively.

Address buffer 2, row decoder 3, column decoder 4 and sense refresh amplifier / input / output control circuit 5 operate in response to respective clock signals applied thereto.

Write designating signal / W is applied to AND gates 11 and 12, respectively. The output signal of AND gate 11 is applied to lower input buffer 7L and lower output buffer 8L, respectively. The output signal of AND gate 12 is applied to upper input buffer 7U and upper output buffer 8U, respectively. Output enable signal / OE
Is a lower output buffer 8L and an upper output buffer 8U
Given to each.

The lower input buffer 7L has an AND gate 1
It operates in response to a signal given from 1. The upper input buffer 7U operates in response to the signal given from the AND gate 12. The lower output buffer 8L receives the signal supplied from the AND gate 11 and the output enable signal /
It operates in response to OE. The upper output buffer 8U is
It operates in response to the signal applied from AND gate 12 and output enable signal / OE.

In the DRAM 100A thus constructed, the column address is input after the row address is input. Then, the word line and the bit line pair are selected based on the row address and the column address thus input, and the memory cell to be accessed is selected.

Next, an address non-multiplex type DRAM will be described. FIG. 2 is a block diagram showing the overall configuration of an address non-multiplex type DRAM.

In FIG. 2, parts common to those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

Referring to FIG. 2, this address non-multiplex type DRAM 100B includes a memory cell array 1, address input buffers 21 and 22, a row decoder 3,
Column decoder 4, sense amplifier 50, data input buffer 7, data output buffer 8, clock generation circuit 60, inverter 13, AND gates 14 and 15, address input terminal 960, signal input terminals 94, 95 and 99, and data input / output terminals. 970 is included.

Address buffer 21 receives row addresses A8, A13, ... From address input terminal 960. Address input buffer 22 receives column addresses A2, A1, ... From address input terminal 960.

Address input buffer 21 applies the received address to row decoder 3 and clock generation circuit 60 as an internal row address signal. Address input buffer 22 applies the received row address to column decoder 4 and clock generation circuit 60 as an internal row address signal.
The row decoder 3 and the column decoder 4 have the same functions as in FIG.

In the read operation, the data read from the selected memory cell of memory cell array 1 is sensed / amplified by sense amplifier 50 and applied to data input / output terminal 970 via data output buffer 8. Data DQ1 to DQ provided to the data input / output terminal 970
8 is output to the outside.

In the write operation, the data input / output terminal 9
Data DQ1 to DQ8 input from 70 are written into the selected memory cell of the memory cell array 1 via the data input buffer 7.

Chip select signal / S is input from signal input terminal 99 and applied to AND gates 14 and 15 via inverter 13. AND gate 14 also receives write designating signal / W. AND gate 15 also receives output enable signal / OE. The output signal of AND gate 14 is applied to clock generation circuit 60 and data input buffer 7. AND
The output signal of the gate 15 is given to the data output buffer 8.

Furthermore, the output signal of the inverter 13 is the address input buffers 21 and 22, the clock generation circuit 60.
And the data input buffer 7. The clock generation circuit 60 generates a clock signal in response to various input signals. The clock signal generated in clock generation circuit 60 is applied to row decoder 3 and sense amplifier 50.

The address input buffers 21 and 22 are
Each operates in response to the output signal of the inverter 13. Row decoder 3 and sense amplifier 50 each operate in response to a clock signal output from clock generation circuit 60. Data input buffer 7 operates in response to the output signal of AND gate 14 and the output signal of inverter 13. The output buffer 8 has an AND gate 15
It operates in response to the output signal of.

In the DRAM 100B thus configured, the row address and the column address are input at the same time.
Then, the memory cell is selected by selecting the word line and the bit line in the memory cell array 1 based on the row address and the column address input at the same time.

In the DRAM shown in FIGS. 1 and 2,
A normal operation of writing and reading data and a refresh operation of refreshing data stored in a memory cell are executed.

Next, a DRA having divided word lines
In M, a configuration for replacing a defective portion in units of memory array blocks will be described. FIG. 3 is a block diagram showing the structure of the DRAM according to the first embodiment.

Referring to FIG. 1, memory cell array 1 is
A plurality of regular memory array blocks NB, NB, ...
It includes a spare memory array block and SB. Thus, the memory cell array 1 is divided into a plurality of memory array blocks.

A plurality of main word lines MWL, MW are provided in all of memory array blocks NB, NB, ... And SB.
L, ... pass. Each of the memory array blocks NB and SB has a plurality of main word lines MWL and MW.
Sub word lines SWL, ... Connected to each of L ,.

The detailed structure of each memory array block is as follows.
It becomes like FIG. 4, FIG. 5 and FIG. 6 shown later. The main word lines MWL, ... Are driven by the main word driver group 31, respectively. The main word driver group 31 includes a plurality of main word drivers.

A sense amplifier group 500 for sensing and amplifying the potential difference between bit line pairs (not shown) included in each memory array block is arranged adjacent to memory cell array 1. This sense amplifier group 500 includes a plurality of sense amplifiers.

In the DRAM of FIG. 3 having the above-described structure, when a defect occurs in any of the normal memory array blocks NB, NB, ..., In operation, a defect occurs in the normal memory array block NB. , And spare memory array block SB is replaced. in this way,
In the DRAM of FIG. 3, the defective normal memory array block NB is relieved by the spare memory array block SB. The relief is realized by replacing the memory array block in the column direction.

The following points are characteristic in controlling the DRAM having the structure shown in FIG. That is, the method of activating the spare sub-word line SWL differs between the case of the address multiplex system and the case of the address non-multiplex system. The details are as follows.

When the DRAM of FIG. 3 is of the address multiplex type, all the memories including the spare memory array block SB at the time of inputting the row address both in the normal operation and the refresh operation. In the array block, sub word line SWL is activated.

The reason is as follows. In the address multiplex type DRAM, a column address is input after a row address is input. In general, the address that selects a block is included in the column address.
Therefore, in normal operation, when the column address is input, the input column address is compared with the column address programmed in advance to replace the memory array block, and based on the comparison result, It is possible to determine the memory array block to be replaced.

Therefore, in the normal operation, the DRAM
Cannot determine whether the memory array block is replaced at the time when the row address is input. Further, the refresh operation is executed in response to the input of the row address.

Therefore, in the address multiplex type DRAM, the sub word line SWL is activated in all the memory array blocks both in the normal operation and the refresh operation.

On the other hand, in the address non-multiplex type DRAM, unlike the address multiplex type DRAM, the sub-word lines of all memory array blocks are activated only during the refresh operation. This is because, in the case of the address non-multiplex system, the column address is input at the same time as the row address, so that it is possible to determine the memory array block to be replaced at the time when the row address is input.

By implementing the structure and control as described above, in the DRAM according to the first embodiment, when the divided word lines are provided, replacement can be performed in memory array block units, and With the configuration, the refresh operation can be realistically performed.

Second Embodiment Next, a second embodiment will be described. In the second embodiment, an example in which various potential supply lines and various signal lines are hierarchized and the supply of potentials and signals to the defective memory array block can be cut off will be described.

FIG. 4 is a circuit diagram showing the structure of the DRAM according to the second embodiment. In FIG. 4, the same parts as those in FIG. The DRAM of FIG. 4 differs from that of FIG. 12 in the following points.

A fuse F1 is provided in the potential supply path between the cell plate potential supply line VCP and the cell plate CP of each memory array block MB.

The bit line equalize potential supply line is divided into a main bit line equalize potential supply line MVBL and a plurality of sub bit line equalize potential supply lines SVBL, ... The plurality of sub bit line equalizing potential supply lines SVBL, ... Are provided corresponding to the plurality of memory array blocks MB ,.

Each potential supply line SVBL is connected to the transistors T2 and T3 of each equalize circuit EQ in the corresponding memory array block MB. Each potential supply line SV
Main bit line equalizing potential supply line MV in BL
The fuse F2 is interposed at a position close to the connection portion with BL.

With such a structure, the bit line equalize potential is equal to the main bit line equalize potential supply line MVB.
It is supplied from L to each equalize circuit EQ of each memory array block MB through a plurality of sub bit line equalize potential supply lines SVBL, ... With a fuse F2 interposed.

A signal line for supplying a bit line connection disconnection signal for connecting and disconnecting bit line pair BL, / BL and sense amplifier 51 is a main bit line connection disconnection signal line MBLI and a plurality of sub bit lines. Connection disconnection signal line SBL
It is divided into I, ... And hierarchically. The plurality of sub bit line connection disconnection signal lines SBLI, ... Are provided corresponding to the plurality of memory array blocks MB ,.

Each signal line SBLI is connected to each transistor pair T4, T5 in the corresponding memory array block MB. In each signal line SBLI, a fuse F3 is provided at a position close to a connection portion with the main bit line connection disconnection signal line MBLI.

With such a configuration, the bit line connection disconnection signal is transmitted from the main bit line connection disconnection signal line MBLI.
It is supplied to each gate electrode of each transistor pair T54, T5 of each memory array block MB through a plurality of sub-bit line connection disconnection lines SBLI, ... With a fuse F3 interposed.

The bit line activation signal line is divided into a main bit line activation signal line MS0 and a plurality of sub bit line activation signal lines SS0, ... The plurality of sub bit line activation signal lines SS0, ... Are provided corresponding to the plurality of memory array blocks MB ,.

Each signal line SS0 is connected to each sense amplifier 51 in the corresponding memory array block MB. In each signal line SS0, the main bit line activation signal line M
The fuse F4 is interposed at a position close to the connection portion with S0.

With this structure, the bit line activation signal is transmitted from the main bit line activation signal line MS0 to the plurality of sub bit line activation signal lines S with the fuse F4 interposed.
It is supplied to each sense amplifier 51 of each memory array block MB via S0, ....

The bit line equalize signal line is divided into a main bit line equalize signal line MBLEQ and a plurality of sub bit line equalize signal lines SBLEQ, ... A plurality of sub bit line equalize signal lines S
BLEQ, ... Are a plurality of memory array blocks MB ,.
It is provided corresponding to each of.

Each signal line SBLEQ is connected to the gate electrode of the transistor T1 of each equalize circuit EQ in the corresponding memory array block MB. Each signal line SBLE
In Q, main bit line equalize signal line MBLE
The fuse F5 is interposed at a position close to the connection portion with Q.

With such a structure, the bit line equalize signal is transmitted to the main bit line equalize signal line MBLEQ.
From the plurality of sub-bit line equalize signal lines SBLEQ, ... Through which the fuse F5 is interposed, the transistor T of each equalize circuit EQ of each memory array block MB.
1 is supplied.

In the DRAM of FIG. 4, the spare word driver and the spare main word line as shown in FIG. 12 are not provided. In this DRAM, the spare memory array block SB as shown in FIG.
Is provided. Therefore, a certain memory block M
When a defect occurs in B, replacement is performed in memory array block units.

DRA according to the second embodiment having such a configuration
In M, when a defect occurs in a certain memory array block, the fuse F1 corresponding to that memory array block
All of ~ F5 are disconnected.

If such cutting is performed, word lines MWL, ... And SWL1 ,.
Short circuit with BL or cell plate CP
Even if a defect such as the occurrence of a short circuit between the bit line pair BL, / BL that may form a current leakage path occurs, the path through which the leakage current flows is not formed. Therefore, according to the DRAM of the second embodiment, the standby current can be suppressed.

The structure including such fuses F1 to F5 can be applied to both the address multiplex type DRAM and the address non-multiplex type DRAM. The operation when the configuration including such a fuse is applied to those DRAMs will be described below.

In the case of the address multiplex type DRAM, the column address is input after the row address is input. Therefore, when the row address is input, all the sub-word lines SWL1, ... Connected to the main word line MWL are activated. However, in such a case, if the fuses F1 to F5 are all blown in advance, various potentials and various signals are not supplied to the defective memory array block MB, so that the standby current is suppressed.

Address non-multiplex type DRA
In the case of M, the row address and the column address are input at the same time. Therefore, when the row address is input, the memory array block MB to be activated can be selected by the block selection signal included in the column address.

Therefore, when the defective memory array block MB is selected by the block selection signal, address comparison is performed by a predetermined address comparison circuit. Then, in response to the comparison result, the replaced spare memory array block is selected.

In that case, since the defective memory array block MB is not activated, the sub-word lines SWL1, ... In the memory array block MB are not activated. Address non-multiplex type DR
Also in AM, the fuses F1 to F5 corresponding to the defective memory array block are blown in advance, so that the standby current is suppressed.

Third Embodiment Next, a third embodiment will be described. In the third embodiment, the fuse F in the DRAM shown in FIG. 4 is used.
An example in which each of 1 to F5 is replaced with a transistor element will be described. Such a configuration is applied to the address non-multiplex type DRAM.

FIG. 5 is a circuit diagram showing the structure of the DRAM according to the third embodiment. In FIG. 5, those parts which are the same as those corresponding parts in FIG. 4 are designated by the same reference numerals, and a description thereof will be omitted.

The structure of the DRAM of FIG. 5 is different from that of FIG. 4 in that NMOS transistors TR1 to TR5 are provided instead of the fuses F1 to F5 shown in FIG. 4, and these transistors TR1 to TR5 are respectively provided. That is, it is operated in response to the block selection signal BS.

The transistor TR1 is connected to the potential supply line VCP.
And the cell plate CP. The transistor TR2 is interposed in the potential supply line SVBL. Transistor TR3 is interposed in signal line SBLI. The transistor TR4 is interposed in the signal line SS0. Transistor TR5 is interposed in signal line SBLEQ.

The block selection signal BS is supplied to the gate electrodes of the transistors TR1 to TR5.
The block selection signal BS is generated based on the input column address.

A structure provided with such transistors TR1 to TR5 is an address non-multiplex type DRA.
The reason why it is applied only to M is as follows.

That is, in the address non-multiplex system, since the row address and the column address are input at the same time, the block selection signal B for selecting the memory array block MB to be activated at the time when the row address is input.
S can be determined. Therefore, when the main word line MWL is activated based on the row address, only the transistors TR1 to TR5 corresponding to the activated memory array block MB can be turned on to activate only the memory array block MB.

Address non-multiplex type DRA
In M, the defective memory array block MB is not selected because it is supposed to be replaced with a spare memory array block. Therefore, the transistors TR1 to TR5 corresponding to the defective memory array block MB are always off.

Therefore, since various potentials and various signals are not supplied to the defective memory array block MB, the standby current can be suppressed in the DRAM according to the third embodiment.

Fourth Embodiment Next, a fourth embodiment will be described. In the fourth embodiment, an example will be described in which each of the transistors TR3 to TR5 in the DRAM shown in FIG. 5 is replaced with a logic gate. Such a configuration is applied to the address non-multiplex type DRAM.

FIG. 6 is a circuit diagram showing the structure of the DRAM according to the fourth embodiment. In FIG. 6, parts common to those in FIG. 5 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The structure of the DRAM of FIG. 6 differs from that of FIG. 5 in the following points. That is, the AND gate AG1 is used instead of the transistors TR3 to TR5 shown in FIG.
~ AG3 are provided. Further, each of AND gates AG1 to AG3 and transistors TR1 and TR2 is operated in response to signal SE for determining whether the corresponding memory array block MB is in a defective state or not.

The AND gate AG1 is connected to the signal line MBLI.
And the signal line SBLI. AND gate AG1 receives a signal from signal line MBLI and signal SE, and outputs an output signal in response to signal SE and signal line SB.
Supply to LI.

The AND gate AG2 is connected to the signal line MS0,
It is interposed between the signal line SS0. AND gate AG2
Receives the signal from signal line MS0 and signal SE, and supplies an output signal to signal line SS0 in response to those signals. AND gate AG3 is interposed between signal line MBLEQ and signal line SBLEQ. AND gate AG
3 receives the signal from the signal line MBLEQ and the signal SE, and outputs an output signal in response to the signals SE and SBL.
Supply to EQ.

Each of transistors TR1 and TR2 receives signal SE on its gate electrode and operates in response to signal SE.

The structure including the AND gates AG1 to AG3 and the transistors TR1 and TR2 is applied to the address non-multiplex type DRAM for the following reason.

That is, in the address non-multiplex system, the memory array block to be activated can be determined when the row address and the column address are simultaneously input. Therefore, at the time of activating the main word line MWL, it is possible to determine whether the activated memory array block MB is in a defective state.

According to such a determination result, when the corresponding memory array block MB is in the defective state, the signal S
E goes to L level and the corresponding memory array block M
When B is not in a defective state, signal SE goes high.
In response, transistors TR1 and TR2 are both turned on. As a result, the potential from the potential supply line VCP is supplied to the cell plate CP, and the potential supply line MVBL
Is supplied to the potential supply line SVBL.

Further, in response to signal SE attaining the H level, each of AND gates AG1 to AG3 outputs a signal corresponding to the signal applied from the corresponding main signal line to the corresponding sub signal line. Communicate to.

On the other hand, the corresponding memory array block MB
Signal is in a defective state, the signal SE becomes L level. In response to this, both transistors TR1 and TR2 are turned off. Therefore, no potential is supplied from the potential supply line VCP to the cell plate CP, and no potential is supplied from the potential supply line MVBL to the potential supply line SVBL. Further, in response to signal SE attaining the L level, each of AND gates AG1 to AG3 provides the signal of the L level to the corresponding sub signal line.

Thus, the memory array block MB which is not in the defective state is activated, and the memory array block MB which is in the defective state is not activated. Therefore, since various potentials and various signals are not supplied to the defective memory array block MB, the standby current can be suppressed in the DRAM according to the fourth embodiment.

Fifth Embodiment Next, a fifth embodiment will be described. In the fifth embodiment, an example in which replacement can be performed in subword line units when a defect occurs in a subword line will be described.

FIG. 7 is a circuit diagram showing the structure of the DRAM according to the fifth embodiment. In FIG. 7, parts common to those in FIG. 16 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The DRAM of FIG. 7 differs from that of FIG. 16 in the following points. In the DRAM of FIG. 7, the segment drivers 61 and 62 and the address comparison circuit 6 shown in FIG.
00, the normal deactivation signal generation circuit 604 and the spare activation signal generation circuit 605 are not provided, and instead, an address comparison circuit 60, spare segment drivers 61S and 62S and normal segment drivers 61N and 62N are provided. .

Further, the main word drivers 3Ma, 3
Instead of Mb and spare main word driver 3S, main word drivers 3MA and 3MB and spare main word driver 3SA are provided, respectively.

Main word driver 3MA and 3MB
Drive the corresponding main word line in response to only the output signal of normal row decoder 30M. Spare main word driver 3SA drives spare main word line SMWL in response to only the output signal of spare row decoder 30S.

The address of the defective segment is programmed in the address comparison circuit 60. Here, the segment address means the sub word lines SWL11 to SWL.
An address that identifies each of WL22. The address comparison circuit 60 receives the segment selection address SSA input to the DRAM and receives the segment selection address SS
Compare A with the programmed segment address.

Address comparing circuit 60 sets the output signal to the first level when the addresses match, and sets the output signal to the second level when the addresses do not match. The output signal of the address comparison circuit 60 is the normal segment drivers 61N and 62N.
N and spare segment drivers 61S and 62S, respectively.

Normal segment driver 61N and spare segment driver 61S receive block selection signal BS1 of corresponding memory array block MB1. Each of normal segment driver 62N and spare segment driver 62S receives block selection signal BS2 of corresponding memory array block MB2.
When a certain memory array block is selected, the block selection signal corresponding to that block becomes H level.

Each of normal segment drivers 61N and 62N outputs an output signal L when the level of the signal received from address comparison circuit 60 is the first level and corresponding block selection signal SB1 is the H level.
To level. On the other hand, the normal segment driver 61
Each of N and 62N sets the output signal to the H level when the level of the signal received from address comparison circuit 60 is the second level and corresponding block selection signal SB1 is at the H level.

Spare segment drivers 61S and 6
Each of the 2S sets the output signal to the H level when the level of the signal received from the address comparison circuit 60 is the first level and the corresponding block selection signal is the H level. On the other hand, spare segment drivers 61S and 6S
Each of the 2S sets the output signal to the L level when the level of the signal received from the address comparison circuit 60 is the second level and the corresponding block selection signal is the H level.

The output signal of normal segment driver 61N is applied to subword drivers G11 and G21. The output signal of spare segment driver 61S is applied to spare subword driver SG1. The output signal of normal segment driver 62N is applied to subword drivers G12 and G22. The output signal of spare segment driver 62S is applied to spare subword driver SG2.

Therefore, when the same segment selection address SSA as the programmed segment address is not input to the address comparison circuit 60, all the sub word lines in the selected memory array block are rendered active. On the other hand, when the same segment selection address SSA as the programmed segment address is input to the address comparison circuit 60, the spare subword line in the selected memory array block is activated.

In operation, when the segment selection address SSA that does not match the segment address corresponding to the defective subword line is input, the normal segment driver 61N or 62N selects the regular subword line. In that case, the main word line MW
L1 or MWL2 is selectively activated based on the input row address. As a result, the regular sub word line is activated.

Spare main word line SMWL1
Are always activated by spare row decoder 30S and spare main word driver 3SA.

On the other hand, when the segment selection address SSA that matches the segment address corresponding to the defective sub-word line is input, the spare sub-word line is selected by the spare segment driver 61S or 62S. Since spare main word line SMWL is always activated, spare subword line is activated in that case.

As described above, the spare main word line SMW is
When L is always activated, the spare main word line S
It is not necessary to perform address comparison for activating MWL, and the operation speed can be increased.

Here, the spare main word line S
Although the example in which the MWL is always activated has been described, the present invention is not limited to this, and the spare row decoder 30S is programmed in advance with a row address corresponding to a defective sub-word line, and an input row address and a programmed row address are programmed. Alternatively, the spare main word line SMWL may be activated only when these addresses are compared with each other.

In the DRAM of FIG. 7, it is necessary to determine whether the normal subword line or the spare subword line is selected at the time when the row address is input.

In the case of the address non-multiplex system, since the row address and the column address are input at the same time, such a condition can be satisfied. In addition, in the case of the address multiplex method, since the column address is input after the row address is input, such a condition is satisfied only when the segment selection address SSA can be specified by the row address. You can

In the case of the address non-multiplex system, when the replacement is performed in units of sub-word lines as shown in FIG. 7, the address comparison circuit 60 needs to have the configuration shown in FIG.

FIG. 8 shows D of the address multiplex system.
It is a block diagram of an address comparison circuit in a RAM.

Referring to FIG. 8, address comparison circuit 60
Is an address comparison unit 60 corresponding to the normal segment driver 61N and the spare segment driver 61S.
a and the address comparison unit 6 corresponding to the normal segment driver 62N and the spare segment driver 62S.
0b and must be included. That is, it is necessary to compare the segment address for each memory array block.

In the case of the address multiplex system, since the block selection address is not input at the time when the row address is input, it is not possible to determine which block is activated. Therefore, the segment address is compared for each memory array block. There is a need. Therefore, each of address comparison units 60a and 60b is programmed with a segment address corresponding to a subword line in which a defect has occurred in the corresponding memory array block.

As described above, in the DRAM according to the fifth embodiment, the replacement can be performed in units of sub-word lines, so that the word line replacement efficiency can be increased.

Sixth Embodiment Next, a sixth embodiment will be described. In the sixth embodiment, in the DRAM of FIG. 7, a subword line can be replaced by a spare subword line connected to each of the main word line and the spare main word line.

FIG. 9 is a circuit diagram showing the structure of a DRAM according to the sixth embodiment. In FIG. 9, the same parts as those in FIG. 7 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The DRAM of FIG. 9 differs from that of FIG. 7 in the following points. That is, spare memory array block SMB, address comparison circuit 601 and spare segment drivers 63S and 64S are further provided.

The spare memory array block SMB is
Spare subword lines SSWL3 to SSWL5, spare bit line pair SBLP, spare memory cells MC2, ..., Spare subword drivers SG3 to SG5 are included.

In the memory array block SMB,
A spare subword line SSWL3 is connected to the main word line MWL1 via a spare subword driver SG3. The spare subword line SSWL is connected to the main word line MWL2 via the spare subword driver SG4.
4 is connected. In the spare main word line SMWL,
Spare subword line SSWL5 is connected via spare subword driver SG5.

Spare sub-word lines SSWL3 to SSWL
Spare bit line pair SBLP is arranged in the direction crossing 5. Spare memory cell MC2 is arranged at each intersection of spare sub-word lines SSWL3 to SSWL5 and spare bit line pair SBLP. Spare memory cell M
Each of C2, ... Is connected to the spare sub word line and spare bit line pair SBLP at each intersection.

The address of the defective segment is programmed in the address comparison circuit 601. The address comparison circuit 601 receives the segment selection address SSA input to the DRAM and compares the segment selection address SSA with the programmed segment address.

Address comparison circuit 601 sets the output signal to the first level when the addresses match, and sets the output signal to the second level when the addresses do not match. The output signal of address comparison circuit 601 is applied to normal segment drivers 61N and 62N and spare segment driver 63S, respectively.

Spare segment driver 63S is provided corresponding to spare subword drivers SG3 and SG4.

Spare segment driver 64S is provided corresponding to spare subword driver SG5. The spare segment driver 63S includes the address comparison circuit 6
In response to the output signal of 0, the normal segment driver 6
It operates similarly to each of 1N and 62N, and when the output signal of address comparison circuit 601 is at the first level, it sets the output signal to the H level. As a result, the spare sub-word line SSWL3 or SSWL4 can be activated when a defect occurs in the sub-word line of the memory array block MB1 or MB2.

On the other hand, the normal segment driver 61N
And 62N each further includes an address comparison circuit 601.
It also operates in response to the output signal of. That is, when the output signal of address comparison circuit 601 is at the first level, an L level signal is output, and the corresponding sub word line is rendered inactive. The spare segment driver 64S receives the output signal of the address comparison circuit 60,
It operates similarly to each of spare segment drivers 61S and 62S.

As described above, in the DRAM of FIG. 9, each of subword lines SWL11 and SWL12 can be replaced with spare subword line SSWL3.
Each of sub word lines SWL21 and SWL22 can be replaced with spare sub word line SSWL4. As an example, the sub word line SWL11 is replaced with the spare sub word line SSWL1 or SSWL3.

As described above, in the DRAM according to the sixth embodiment, replacement can be performed in units of sub-word lines, and the degree of freedom of replacement can be increased as compared with the DRAM of the fifth embodiment.

The configuration of FIG. 9 shows a DRAM of the address non-multiplex system. When such a configuration is applied to an address multiplex type DRAM, as described in the fifth embodiment, each of the address comparison circuits 60 and 601 must have an address comparison unit corresponding to each memory array block. is necessary. Further, as described above, the segment selection address needs to be specified by the row address.

Seventh Embodiment Next, a seventh embodiment will be described. In the seventh embodiment, an example in which the address comparison operation by the address comparison circuit and the data amplification operation by the sense amplifier can be performed in parallel will be described.

FIG. 10 is a circuit diagram showing the structure of the DRAM according to the seventh embodiment. In FIG. 10, the same parts as those in FIG. 9 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The DRAM of FIG. 10 differs from that of FIG. 9 in the following points. In the DRAM of FIG. 10, the spare main word line is not provided. Therefore, the components related to the spare main word line are not provided. Further, address comparison circuit 602 operates differently from the address comparison circuit shown in FIG.

Further, in FIG. 10, a plurality of sense amplifiers 51-53 and a plurality of transistor pairs T11, T1 are provided.
1 to T13, T13 and the input / output line pair IOP are shown.

The data transmitted to the bit line pair BLP1 is sensed / amplified by the sense amplifier 51 and transmitted to the input / output line pair IOP via the transistor pair T11, T11. The data transmitted to the bit line pair BLP2 is
It is sensed and amplified by the sense amplifier 52, and is transmitted to the input / output line pair IOP via the transistor pair T12 and T12.

The data transmitted to the spare bit line pair SBLP is sensed / amplified by the sense amplifier 53, and is input / output line pair IOP via the transistor pair T13 and T13.
Is transmitted to

Each of the transistors T11 to T13 has an N
It is a MOS transistor. Transistor pair T11, T
Each gate of 11 is connected to the column selection line CSL1. The gate electrodes of the transistor pair T12 and T12 are connected to the column selection line CSL2. The gate electrodes of the transistor pairs T13 and T13 are connected to the spare column selection line SCSL.

Normal segment drivers 61N, 62
In operation, each of N and spare segment driver 63S always sets the output signal to the H level. Therefore, in operation, the sub-word drivers G11 to G22
And spare subword drivers SG3 and SG4 are all activated.

The address comparison circuit 602 is programmed with the segment address corresponding to the defective sub-word line. The address comparison circuit 602 compares the input segment selection address SSA with the programmed segment address.

When the addresses do not match, the address comparison circuit 602 sets the column selection line CSL1 or CSL2 corresponding to the segment selection address to the H level. On the other hand, when the addresses match, the address comparison circuit 602 determines that the spare column selection line SC
Set SL to H level. That is, the address comparison circuit 6
02, column select lines CSL1 and CSL2 and spare column select line SCSL are selectively activated.

In the DRAM of FIG. 10 thus configured, sub word line SWL11 or SWL12 is replaced with spare sub word line SSWL3, and sub word line SWL3 is replaced.
WL21 or SWL22 is a spare sub word line SSW
Replaced with L4.

Next, the operation of the DRAM of FIG. 10 will be described. By normal segment drivers 61N and 62N and spare segment driver 63S, all of subword drivers G11 to G22 and spare subword drivers SG3 and SG4 can be activated. Further, the main word lines MWL1 and MWL2 are selectively activated.

Therefore, all the sub word lines and spare sub word lines corresponding to the activated main word lines are activated. As a result, the bit line pair BLP1,
Data is transmitted to BLP2 and spare bit line pair BLP, respectively. Then, those data are amplified by the sense amplifiers 51 to 53, respectively.

While the operation from activation of the sub-word line and spare sub-word line to amplification of data in each of sense amplifiers 51 to 53 is performed, address comparison operation is performed in address comparison circuit 602. It is done in parallel.

Immediately after the amplification operation by each of sense amplifiers 51-53 is completed, column comparison lines CSL1, CSL2 and spare column selection line SCSL are selectively activated by address comparison circuit 602, whereby , One type of amplified data is transmitted to the input / output line pair IOP.

Further, such an operation differs between the address multiplex system and the address non-multiplex system. In the case of the address non-multiplex system, the memory array block to be activated is determined at the time when the row address is input. Therefore, the bit line pair BLP1 or BLP2 and the spare bit line pair SBLP of the memory array block to be activated are determined. Data is transmitted to.

On the other hand, in the case of the address multiplex system, since the memory array block to be activated is not determined at the time when the row address is input, the bit line pair B
Spare bit line pair SB with both LP1 and BLP2
Data is transmitted to LP.

As described above, in the DRAM of FIG. 10, replacement can be performed in units of sub-word lines, so that word line replacement efficiency can be increased. Further, since the data amplifying operation by each of the sense amplifiers 51 to 53 and the address comparing operation in the address comparing circuit 602 are performed in parallel, the operation can be speeded up.

Eighth Embodiment Next, an eighth embodiment will be described. In the eighth embodiment, as a modification of the seventh embodiment, data amplified by a plurality of sense amplifiers is transmitted to a plurality of input / output line pairs,
In addition, an example in which the data can be selectively output by the multiplexer will be described.

FIG. 11 is a circuit diagram showing the structure of the DRAM according to the eighth embodiment. 11, the same parts as those in FIG. 10 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.

The DRAM of FIG. 11 differs from that of FIG. 10 in the following points. Input / output line pairs IOP1 and IOP2 and spare input / output line pair SI corresponding to bit line pair BLP1 and BLP2 and spare bit line pair SBLP, respectively.
OP is provided. Column select lines CSL1 and CSL2 and spare column select line SCSL are activated at the same time.

The address comparison circuit 603 is programmed with the segment address corresponding to the defective sub-word line. The address comparison circuit 603 compares the input segment selection address SSA with the programmed segment address, and gives information indicating the comparison result to the multiplexer MUX.

Input / output line pair I is connected to the multiplexer MUX.
OP1, IOP2 and spare input / output line pair SIOP are connected. The multiplexer MUX selectively supplies the data transmitted to the connected input / output line pair to the preamplifier PA in response to the information of the comparison result supplied from the address comparison circuit 603. Next, the operation of the DRAM of FIG. 11 will be described. Here, differences from the operation of the DRAM of FIG. 10 will be described.

By activating the sub word line and the spare sub word line corresponding to the activated main word line, the data transmitted to bit line pair BLP1, BLP2 and spare bit line pair SBLP are transmitted to sense amplifier 51. Is amplified by .about.53 and transmitted to the input / output line pair IOP1 and IOP2 and the spare input / output line pair SIOP through the corresponding transistor pair.

After activating the sub word line and the spare sub word line in this manner, input / output line pair IOP1, IO
While the operation until transmission to P2 and spare input / output line pair SIOP is performed, address comparison operation is performed in parallel in address comparison circuit 603.

Then, after the data is transmitted to each of the input / output line pairs IOP1 and IOP2 and the spare input / output line pair SIOP, the multiplexer MUX promptly changes the data.
The data transmitted to either I / O line pair IOP1 or IOP2 and spare I / O line pair IOP is applied to preamplifier PA.

Data read in such an operation is as follows:
The address multiplex method differs from the address non-multiplex method. In the case of the address non-multiplex system, the memory array block to be activated is determined when the row address is input.
Therefore, in that case, the I / O line pair IOP1 or IOP2 corresponding to the memory array block to be activated is used.
And data is transmitted to the spare input / output line pair SIOP.

On the other hand, in the case of the address multiplex system, the memory array block to be activated is not fixed at the time when the row address is input. Therefore, in that case, data is transmitted to both of the I / O line pair IOP1 and IOP2 and the spare I / O line pair SIOP.

In the DRAM of FIG. 11 as described above,
Since replacement can be performed in subword line units, word line replacement efficiency can be increased. Further, input / output line pairs IOP1 and IOP and spare input / output line pair SI
Since the operation of transmitting data to OP and the address comparison operation by address comparison circuit 603 are performed in parallel, the operation can be speeded up.

[0350]

According to the first aspect of the present invention, the cell plate potential is supplied to the cell plate of each memory array block from the cell plate potential supply line through the interruption means. Therefore, when a defect occurs in the memory array block, the supply of the cell plate potential can be interrupted by the interruption means corresponding to the memory array block.

As a result, even if there is a short circuit between the main word line and the cell plate, no current path is formed between the main word line and the cell plate potential supply line. Therefore, the current consumption during standby can be reduced.

According to the present invention of claim 2, the signal line for supplying the equalizing control signal for controlling the equalizing means provided corresponding to each memory array block is the main equalizing control signal supplying line. And a plurality of sub equalization control signal supply lines. Further, each sub-equalize control signal supply line is provided with a blocking means.

Therefore, when a defect occurs in a memory array block, the supply of the equalizing control signal to the equalizing unit corresponding to the defective memory array block is cut off by the cutoff unit corresponding to the memory array block. You can get drunk. Therefore, the current consumption during standby can be reduced.

According to the third aspect of the present invention, the signal line for supplying the switching control signal is hierarchized into the main switching control signal supply line and the plurality of sub-switching control signal supply lines. Further, a breaking means is provided on the sub-switching control signal supply line.

Therefore, when a failure occurs in the memory array block, the cutoff means corresponding to the memory array block cuts off the supply of the switching control signal to the switching means corresponding to the defective memory array block. You can get drunk. Therefore, the current consumption during standby can be reduced.

According to the fourth aspect of the present invention, the equalize potential supply line is hierarchized into a main equalize potential supply line and a plurality of sub equalize potential supply lines.
Further, each sub-equalizing potential supply line is provided with a blocking means.

Therefore, when a defect occurs in a memory array block, the supply of the equalizing potential to the equalizing unit corresponding to the defective memory array block is cut off by the cutoff unit corresponding to the memory array block. obtain.

As a result, even if there is a short circuit between the main word line or sub word line and the bit line pair, a current path does not occur between the main word line or the sub word line or the main equalizing potential supply line. . Therefore, the current consumption during standby can be reduced.

According to the present invention of claim 5, the signal line for supplying the sense amplifier activation signal is divided into the main sense amplifier activation signal supply line and the plurality of sub-sense amplifier activation signal supply lines. Has been converted. Further, a cutoff means is provided in each sub-sense amplifier activation signal supply line.

Therefore, when a defect occurs in the memory array block, the interrupting means corresponding to the memory array block sends the sense amplifier activation signal to the sense amplifier means corresponding to the defective memory array block. Supply can be cut off. Therefore, the current consumption during standby can be reduced.

According to the sixth aspect of the present invention, specifically, by configuring all or some of the plurality of breaking means by fuse elements, it is possible to reduce current consumption during standby.

According to the seventh aspect of the present invention, specifically, by configuring all or some of the plurality of breaking means by transistor elements, it is possible to reduce current consumption during standby.

According to the present invention described in claim 8, specifically, a block selection signal for selecting a plurality of memory array blocks is selected for the operation of the transistor elements forming all or a part of the plurality of cutoff means. By controlling with, it is possible to reduce the current consumption during standby.

According to the ninth aspect of the present invention, specifically, the operation of the transistor elements forming all or a part of the plurality of cutoff means is determined by whether or not the corresponding memory array block is in a defective state. It is possible to reduce the current consumption during standby by controlling with the signal indicating the determination result.

According to the tenth aspect of the present invention, specifically, by configuring all or some of the plurality of breaking means by the logic means, it is possible to reduce the current consumption during standby.

According to the eleventh aspect of the present invention, specifically, the operation of the logic means forming all or a part of the plurality of cutoff means is controlled by the signal from the corresponding signal supply line and the corresponding memory. By controlling in response to the signal indicating the determination result of whether the array block is in the defective state,
The current consumption during standby can be reduced.

According to the twelfth aspect of the present invention, in each memory array block, the corresponding normal sub-word line activating means activates the normal sub-word line connected to the normal main word line to respond. The redundant sub word line activation means activates the redundant sub word line connected to the redundant main word line.

When the normal subword line of the corresponding memory array block is defective, the redundant subword line activating means activates the redundant subword line of the corresponding memory array block instead. That is,
In each memory array block, when a defect occurs in the normal subword line, replacement is performed in subword line units. Therefore, the replacement efficiency of the word line when a defect occurs can be made high (good).

According to the thirteenth aspect of the present invention, the redundant main word line of each memory array block is always activated by the redundant main word line activation means. Then, when a defect occurs in the normal subword line of each memory array block, the redundant subword line of each memory array block is selected by the redundant subword line activating means responding to the address for selecting the normal subword line. .

Therefore, in the access when the normal sub-word line is replaced with the redundant sub-word line, the address relating to the selection of the normal sub-word line can be obtained without the need for the address comparison operation for selecting the redundant main word line. The replaced redundant subword line can be selected only by selecting the responding redundant subword line. Therefore, the access speed can be increased.

According to the fourteenth aspect of the present invention, in the address multiplex type DRAM in which the column address is input after the row address including the address for selecting the normal subword line to be activated is input, A plurality of normal subword lines and corresponding redundant subword lines are selected in relation to the input row address. Therefore, in the address multiplex type DRAM, sub-word line unit replacement can be performed in each memory array block.

According to the fifteenth aspect of the present invention, in an address non-multiplex type DRAM in which a row address and a column address are input at the same time, a plurality of normal subword lines and a plurality of normal subword lines are provided in association with the row address or the column address. Corresponding redundant sub-word lines are selected.
Therefore, address non-multiplex type DRAM
In each memory array block, sub word line units can be replaced.

According to the sixteenth aspect of the present invention, the defective normal subword line is connected to the redundant subword line in the corresponding memory array block or the normal main word line to which the normal subword line is connected. It It is replaced by a spare sub word line. Therefore, it is possible to increase the degree of freedom of replacement of the regular sub word line.

According to the seventeenth aspect of the present invention, since the defective normal subword line is replaced with the redundant subword line in units of subword lines, the replacement efficiency of the word line can be increased. Further, since the amplification operation by the sense amplifier means and the address comparison operation by the address comparison control means are performed in parallel, the operation speed can be increased.

According to the eighteenth aspect of the present invention, since the defective normal sub-word line is replaced with the redundant sub-word line in sub-word line units, the word line replacement efficiency can be increased. Further, the amplifying operation by the sense amplifier means and the address comparing operation by the address comparing means are performed in parallel. In other words, the data transmission operation of the input / output line pair and the address comparison operation are performed in parallel. Therefore, the operation can be speeded up.

According to the nineteenth aspect of the present invention, in the refresh operation, the sub word line connected to the activated main word line is activated in all the normal memory array blocks and the redundant memory array blocks. It Therefore, an appropriate refresh operation can be performed in a DRAM having a sub word line for each memory array block and a redundant memory array block.

According to the twentieth aspect of the present invention, the main word activated in all the normal memory array blocks and the redundant memory array blocks during the normal operation and the refresh operation of the address multiplex type DRAM. The sub word line connected to the line is activated. Therefore, in an address multiplexer type DRAM having a sub-word line for each memory array block and a redundant memory array block, an appropriate normal operation can be performed according to an address input method, and an appropriate refresh operation can be performed. You can also do

According to the twenty-first aspect of the present invention, in the refresh operation of the address non-multiplex type DRAM, each normal memory array block and all of the redundant memory array blocks are set as main word lines to be activated. The connected sub word line is activated.
Therefore, an appropriate refresh operation can be performed in an address non-multiplex type DRAM having a sub-word line for each memory array block and a redundant memory array block.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an address multiplex type DRAM.

FIG. 2 Address non-multiplex type DRAM
3 is a block diagram showing the overall configuration of FIG.

FIG. 3 is a block diagram showing a configuration of a DRAM according to the first embodiment.

FIG. 4 is a circuit diagram showing a configuration of a DRAM according to a second embodiment.

FIG. 5 is a circuit diagram showing a structure of a DRAM according to a third embodiment.

FIG. 6 is a circuit diagram showing a structure of a DRAM according to a fourth embodiment.

FIG. 7 is a circuit diagram showing a structure of a DRAM according to a fifth embodiment.

FIG. 8 is a block diagram of an address comparison circuit in an address multiplex type DRAM.

FIG. 9 is a circuit diagram showing a structure of a DRAM according to a sixth embodiment.

FIG. 10 is a circuit diagram showing a structure of a DRAM according to a seventh embodiment.

FIG. 11 is a circuit diagram showing a structure of a DRAM according to an eighth embodiment.

FIG. 12 Conventional DRA with split word lines
It is a circuit diagram which shows the structure of the principal part of M.

FIG. 13 is a circuit diagram showing a configuration of a decode circuit of an address multiplex type DRAM.

[FIG. 14] Address non-multiplexed DRA
It is a circuit diagram which shows the structure of the decoding circuit of M.

FIG. 15 is a circuit diagram showing a configuration of a memory cell of a DRAM.

FIG. 16 is a conventional DRAM in which word lines can be replaced.
FIG. 3 is a block diagram showing the configuration of FIG.

[Explanation of symbols]

1 memory cell, NB, MB, MB1, MB2 array block, SB spare memory array block, MW
L, MWL1, MWL2 Main word line, SMWL
Spare main word lines, SWL1 to SWL4, SWL1
1 to SWL22 sub word line, SSWL1 to SSWL5
Spare sub word line, CP cell plate, VCP
Cell plate potential supply line, MVBL main bit line equalize potential supply line, SVBL sub bit line equalize potential supply line, MBLI main bit line connection disconnection signal line, SBLI sub bit line connection disconnection signal line, MA0
Main bit line activation signal line, SS0 sub bit line activation signal line, MBLEQ main bit line equalize signal line, SBLEQ sub bit line equalize signal line, F1
~ F5 fuse, 51-53 sense amplifier, EQ
Equalize circuit, MC memory cell, MC1, MC2
Spare memory cell, BL, / BL bit line pair, BS
Block selection signal, TR1 to TR5 transistors, 6
0, 601-603 address comparison circuit, 61N, 62
N normal segment driver, 61S, 62S spare segment driver, 3MA, 3MB main word driver, 3SA spare main word driver, IO
P, IOP1, IOP2, SIOP I / O line pair.

Claims (21)

[Claims] 1. A memory cell array having a plurality of dynamic memory cells, which is divided into a plurality of memory array blocks; and a plurality of main word lines passing through the plurality of memory array blocks. Each of the memory cells includes a memory transistor and a memory capacitor, and each of the plurality of memory array blocks is connected to the plurality of memory cells in the memory array block and to the plurality of main word lines. A plurality of sub-word lines and a cell plate which is divided into a plurality of memory cells corresponding to the plurality of memory array blocks and serves as a common electrode of the memory capacitors of a plurality of memory cells in one memory array block. Including in the cell plate of each of the plurality of memory array blocks A cell plate potential supply line that supplies a cell plate potential, a cell plate of each of the plurality of memory array blocks, and a cell plate potential supply line are respectively provided between the cell plate potential supply line and the defective memory array block 2. A semiconductor memory device, further comprising: a plurality of interruption means for interrupting the supply of the cell plate potential. 2. A memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks, a plurality of main word lines passing through the plurality of memory array blocks, and a plurality of memory arrays. Each block includes a plurality of bit line pairs provided in a direction intersecting with the main word line and connected to the plurality of memory cells in the corresponding memory array block, and each of the plurality of memory array blocks. Is connected to the plurality of memory cells in the memory array block,
And a plurality of sub-word lines respectively connected to the plurality of main word lines, provided corresponding to each of the plurality of bit line pairs,
A plurality of equalizers each for equalizing the potential of the corresponding bit line pair, and a main for providing an equalize control signal for controlling the plurality of equalizers provided along the plurality of memory array blocks. The equalizing control signal supply line and the plurality of equalizing means provided corresponding to each of the plurality of memory array blocks, each of which equalizes the plurality of bit line pairs in the corresponding memory array block, A plurality of sub-equalization control signal supply lines for transmitting the equalization control signal supplied from the main equalization control signal supply line, and a plurality of sub-equalization control signal supply lines are provided corresponding to each of the sub-equalization control signal supply lines to cause a defect. The sub-equalization system corresponding to the memory array block The main equalizer and further comprising a plurality of blocking means for cutting off the supply of the equalization control signal from the rise control signal supply line, the semiconductor memory device of the signal supply line. 3. A memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks, a plurality of main word lines passing through the plurality of memory array blocks, and a plurality of memory arrays. Each block includes a plurality of bit line pairs provided in a direction intersecting with the main word line and connected to the plurality of memory cells in the corresponding memory array block, and each of the plurality of memory array blocks. Is connected to the plurality of memory cells in the memory array block,
And a plurality of sub-word lines respectively connected to the plurality of main word lines, provided corresponding to each of the plurality of bit line pairs,
Each is provided between a plurality of sense amplifier means for sensing and amplifying the potential difference of the corresponding bit line pair and between the corresponding bit line pair and the sense amplifier means, and switches the connection state between them. A plurality of switching means, a main switching control signal supply line provided along the plurality of memory array blocks for supplying a switching control signal for controlling the plurality of switching means, and each of the plurality of memory array blocks For transmitting the switching control signal supplied from the main switching control signal supply line to each of the plurality of switching means corresponding to the plurality of bit line pairs in the corresponding memory array block. And multiple sub-switching control signal supply lines for The switching control from the main switching control signal supply line to the sub switching control signal supply line provided corresponding to each of the plurality of sub switching control signal supply lines and corresponding to the defective memory array block. A semiconductor memory device further comprising a plurality of interruption means for interrupting the supply of signals. 4. A memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks, a plurality of main word lines passing through the plurality of memory array blocks, and a plurality of memory arrays. Each block includes a plurality of bit line pairs provided in a direction intersecting with the main word line and connected to the plurality of memory cells in the corresponding memory array block, and each of the plurality of memory array blocks. Is connected to the plurality of memory cells in the memory array block,
And a plurality of sub-word lines respectively connected to the plurality of main word lines, provided corresponding to each of the plurality of bit line pairs,
A plurality of equalizing means for equalizing the potentials of the corresponding bit line pairs, and an equalizing potential provided along the plurality of memory array blocks for equalizing the plurality of bit line pairs, respectively. The main equalizing potential supply line and the plurality of equalizing means provided corresponding to each of the plurality of memory array blocks, each of which equalizes the plurality of bit line pairs in the corresponding memory array block, A plurality of sub-equalization potential supply lines for transmitting the equalization potential supplied from the main equalization potential supply line, and the memory array provided corresponding to each of the plurality of sub-equalization potential supply lines and having a defect Before the sub-equalizing potential supply line corresponding to the block Main equalize the from potential supply line further comprising a plurality of blocking means for cutting off the supply of the equalizing potential, the semiconductor memory device. 5. A memory cell array having a plurality of dynamic memory cells and divided into a plurality of memory array blocks, a plurality of main word lines passing through the plurality of memory array blocks, and a plurality of memory arrays. Each block includes a plurality of bit line pairs provided in a direction intersecting with the main word line and connected to the plurality of memory cells in the corresponding memory array block, and each of the plurality of memory array blocks. Is connected to the plurality of memory cells in the memory array block,
And a plurality of sub-word lines respectively connected to the plurality of main word lines, provided corresponding to each of the plurality of bit line pairs,
A plurality of sense amplifier means for sensing and amplifying the potential difference between the corresponding bit line pairs, and a sense amplifier activation signal which is provided along the plurality of memory array blocks and activates the plurality of switching means. And a main sense amplifier activation signal supply line for supplying a plurality of bit line pairs corresponding to the plurality of bit line pairs in the corresponding memory array block. To each of the sense amplifier means, a plurality of sub-sense amplifier activation signal supply lines for transmitting the sense amplifier activation signal supplied from the main sense amplifier activation signal supply line, and a plurality of sub-sense amplifier activation lines Corresponding to the memory array block where a defect has occurred, provided corresponding to each of the activation signal supply lines That the provided sub-sense amplifier further a plurality of blocking means for cutting off the supply of the sense amplifier activation signal from the main sense amplifier activation signal supply line to the activating signal supply line, the semiconductor memory device. 6. The fuse element according to claim 1, wherein all or a part of the plurality of breaking means are fuse elements.
The semiconductor memory device described. 7. The semiconductor memory device according to claim 1, wherein all or a part of said plurality of breaking means are transistor elements. 8. The semiconductor memory device according to claim 7, wherein an operation of said transistor element is controlled by a signal for selecting each of said plurality of memory array blocks. 9. The semiconductor memory device according to claim 7, wherein the operation of each of the transistor elements is controlled by a signal indicating a result of determination as to whether or not the corresponding memory array block is in a defective state. 10. The semiconductor memory device according to claim 2, 3 or 5, wherein all or some of said plurality of interrupting means are logic means. 11. The logic means receives a signal from a corresponding signal supply line and a signal indicating a determination result as to whether or not the corresponding memory array block is in a defective state, and responds to those signals. 11. The semiconductor memory device according to claim 10, wherein the operation is controlled by the following. 12. A memory cell array having a plurality of memory cells and divided into a plurality of memory array blocks, a plurality of normal main word lines passing through the plurality of memory array blocks, and a plurality of memory array blocks. And a redundant main word line passing through each of the plurality of memory array blocks, each of the plurality of memory array blocks is connected to each of the plurality of normal main word lines and each of the plurality of normal subword lines. A plurality of normal memory cells, a redundant subword line connected to the redundant main word line and replaced with the defective normal subword line, and a redundant memory cell connected to the redundant subword line, A memory array provided corresponding to each of the plurality of memory array blocks. A plurality of normal subword line activating means for activating the plurality of normal subword lines in the lock; and a plurality of normal subword line activation means provided corresponding to each of the plurality of memory array blocks, each of which is provided in a corresponding memory array block. A semiconductor memory device further comprising: a plurality of redundant subword line activating means for activating the redundant subword lines instead of the defective normal subword lines. 13. A redundant main word line activation means for always activating the redundant main word line, wherein each of the plurality of redundant subword line selection means receives an address for selecting the normal subword line. 13. The semiconductor memory device according to claim 12, wherein the corresponding redundant subword line is activated in response to the address. 14. A column address is input after a row address including an address for selecting the normal subword line to be activated is input, and the plurality of normal subword line activating means and the plurality of redundant subword line activating means are provided. 13. The semiconductor memory device according to claim 12, wherein, in association with the row address, selects a plurality of corresponding normal subword lines and a corresponding redundant subword line. 15. A row address and a column address are simultaneously input, and the plurality of normal subword line activating means and the plurality of redundant subword line activating means are associated with each other in relation to the row address or the column address. 13. The semiconductor memory device according to claim 12, wherein a plurality of normal subword lines and the redundant subword line are selected. 16. The memory cell array further includes a redundant memory array block, wherein the redundant memory array block includes a plurality of spare subword lines respectively connected to the plurality of normal main word lines, and a plurality of spare subword lines. A plurality of spare memory cells each connected to the normal main word line to which the normal subword line is connected, instead of the normal subword line having a defect in any one of the memory array blocks. Further comprising a spare subword line selection means for activating the plurality of spare subword lines, wherein the normal subword line in each of the plurality of memory array blocks is the redundant subword line in the corresponding memory array block. Also connected to the corresponding regular main word line The replaced by a spare sub-word lines, a semiconductor memory device according to claim 12, wherein the. 17. A memory cell array having a plurality of memory cells and divided into a plurality of normal memory array blocks and a redundant memory array block, and a plurality of normal memory array blocks and a plurality of memory cells passing through the redundant memory array blocks. And a normal main word line, wherein each of the plurality of normal memory array blocks is connected to each of the plurality of normal main word lines and each of the plurality of normal subword lines. A plurality of normal memory cells, and a pair of normal bit lines provided to intersect the plurality of normal main word lines and selectively transmitting data from the plurality of normal memory cells, the redundant memory array The block includes a plurality of redundant sub-words connected to each of the regular main word lines. A line, a plurality of redundant memory cells connected to each of the plurality of redundant sub-word lines, and a plurality of normal main word lines intersecting each other, and data from the plurality of redundant memory cells are selectively transmitted. Each of the plurality of memory array blocks, each of the plurality of redundant sub-word lines being replaced with the defective normal sub-word line connected to the corresponding main word line. Of the normal bit line pair and the redundant bit line pair, each of which includes a plurality of sense amplifier means for sensing and amplifying the potential difference of the corresponding bit line pair; An input / output line pair to which each output is transmitted; and a plurality of the plurality of sense amplifier means and the input / output line pair. A plurality of switching means that are selectively turned on / off to selectively transmit the output of the sense amplifier means to the input / output line pair, and an address corresponding to the normal subword line replaced with the redundant subword line in advance. The stored address is compared with the address input to select the normal sub-word line, and when these addresses match, the output of the sense amplifier means corresponding to the redundant bit line pair is output. The plurality of switching means are controlled so as to be transmitted to the input / output line pair, and when their addresses do not match, the output of the sense amplifier means corresponding to the normal bit line pair is sent to the input / output line pair. An address comparison control means for controlling the plurality of switching means so that the plurality of sense amplifier means are provided. A semiconductor memory device in which a width operation and an address comparison operation by the address comparison control means are executed in parallel. 18. A memory cell array having a plurality of memory cells and divided into a plurality of normal memory array blocks and a redundant memory array block, and a plurality of normal memory array blocks and a plurality of memory cells passing through the redundant memory array blocks. And a normal main word line, wherein each of the plurality of normal memory array blocks is connected to each of the plurality of normal main word lines and each of the plurality of normal subword lines. A plurality of normal memory cells, and a pair of normal bit lines provided to intersect the plurality of normal main word lines and selectively transmitting data from the plurality of normal memory cells, the redundant memory array The block includes a plurality of redundant sub-words connected to each of the regular main word lines. A line, a plurality of redundant memory cells connected to each of the plurality of redundant sub-word lines, and a plurality of normal main word lines intersecting each other, and data from the plurality of redundant memory cells are selectively transmitted. Each of the plurality of memory array blocks, each of the plurality of redundant sub-word lines being replaced with the defective normal sub-word line connected to the corresponding main word line. Of the normal bit line pair and the redundant bit line pair, each of which includes a plurality of sense amplifier means for sensing and amplifying the potential difference of the corresponding bit line pair; A plurality of input / output line pairs provided corresponding to each of which the output of the sense amplifier means corresponding to each is transmitted; and the redundant sub word line. An address corresponding to the replaced normal subword line is stored in advance, and the address is compared with an address input to select the normal subword line, and an address comparison unit that outputs the comparison result, When the information of the comparison result of the address comparing means is received and the compared addresses match, the potential difference of the input / output line pair to which the output of the sense amplifier means corresponding to the redundant bit line pair is transmitted is output. If the compared addresses do not match, the output signal of the sense amplifier unit corresponding to the normal bit line is transmitted to the input / output line pair, and the multiplexer unit outputs the potential difference between the input / output line pair. A semiconductor memory device in which an amplifying operation by the sense amplifier means and an address comparing operation by the address comparing means are executed in parallel. . 19. A memory cell array having a plurality of dynamic memory cells, and a plurality of main word lines passing through the memory cell array, wherein the memory cell array has a plurality of normal memory array blocks and a defect has occurred. Each of the normal memory array block and the redundant memory array block is replaced with a redundant memory array block, and each memory array block of the redundant memory array block and the redundant memory array block is divided into the plurality of memory cells in the memory array block. A plurality of sub-word lines connected to each of the plurality of main word lines, and in all memory array blocks of the plurality of normal memory array blocks and the redundant memory array block during a refresh operation. Is activated A semiconductor memory device in which the sub-word line connected to the main word line is activated. 20. A semiconductor memory device in which a row address and a column address are sequentially input, and a memory cell is selected according to the row address and the column address, the memory having a plurality of dynamic type memory cells. An array and a plurality of main word lines that pass through the memory cell array and are selected according to the row address are provided. The memory cell array includes a plurality of normal memory array blocks and a defective normal memory array block. And a redundant memory array block that is replaced with, each memory array block of the plurality of normal memory array blocks and the redundant memory array block is connected to the plurality of memory cells in the memory array block, and , A plurality of main word lines connected to each of the plurality of main word lines The sub-word line has a sub-word line, and in normal operation and refresh operation, the sub-word line connected to the activated main word line is activated in all blocks of the plurality of normal memory array blocks and the redundant memory array block. Semiconductor memory device. 21. A semiconductor memory device in which a memory cell is selected according to a row address and a column address inputted at the same time, comprising: a memory cell array having a plurality of dynamic type memory cells; The memory cell array includes a plurality of main word lines selected according to the row address, and the memory cell array is divided into a plurality of normal memory array blocks and a redundant memory array block that replaces the defective normal memory array block. Each memory array block of the plurality of normal memory array blocks and the redundant memory array block is connected to the plurality of memory cells in the memory array block, and is connected to each of the plurality of main word lines. It has multiple sub-word lines to be connected and During Interview operation, in all the blocks of the plurality of normal memory array blocks and said redundant memory array block, the sub-word line connected to the main word line to be activated is activated, the semiconductor memory device.