JPH08111100A - Storage device - Google Patents

Abstract

PURPOSE: To obtain a storage device capable of improving the yield. CONSTITUTION: A 16 M bit DRAM 111 is constituted of four adjacent 4 M bit blocks (4 M bit DRAMs) 121 to 124. Then, circuits of above described execution patterns are biult-up in every block of 121 to 124 and the relief of defective address is individually performed in respective blocks 121 to 124. In the case where respective blocks 121 to 124 are all relievable (nondefective), blocks are isolated by solid lines α and then pads other than input/output(I/O) pads in respective blocks 121 to 124 are connected to blocks at an assembly stage. Thus, the 16 M bit DRAM 111 in which respective blocks are combined is made to be a product.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly to a semiconductor memory device (especially DRAM (Dinamic Rand).
om Access Memory)) is related to.

[0002]

2. Description of the Related Art With the increase in capacity and integration of semiconductor memory devices, defective bits (defective memory cells with defects)
It becomes difficult to manufacture a memory cell array in which no memory cell exists. In particular, when a memory developed using a new circuit technology is mass-produced, the defect level of the initial lot becomes high, resulting in a low yield. However, since there are several defective bits, it is not economical to discard the memory cell array as a defective product.

Therefore, a technique has been studied in which an appropriate number of rows or columns for spare memory cells are added in advance to a regular memory cell array and these rows are replaced with rows or columns in which defective memory cells exist. . This technique enables normal operation even when the address corresponding to the defective bit is designated from the outside, and the defective address is relieved. Generally, this technique is called "redundant circuit technique", and the spare rows and columns are called "redundant rows and columns".

FIG. 6 is a block circuit diagram showing the basic structure of a conventional DRAM having redundant columns. The DRAM is mainly composed of a matrix-shaped memory cell array 51. The memory cell array 51 is composed of memory cells 52 arranged in rows and columns. Each memory cell 52 stores 1-bit data, which is the minimum unit of storage. In the memory cell array 51, each memory cell 52 arranged in the row direction (horizontal direction in FIG. 3) is connected to the word line WL, and each memory cell 52 arranged in the column direction (vertical direction in FIG. 3) is a bit. Connected to line BL or inverted bit line bar BL. One bit line BL is provided with one inversion bit line bar BL corresponding to the bit line BL, and the bit line BL and the inversion bit line bar BL in the corresponding relationship form one bit line pair BL, bar BL. Is configured. Each bit line pair BL and bar BL is connected to each cross-coupled latch type sense amplifier (SA) 53. In each bit line pair BL and bar BL, the signal levels of the bit line BL and the inverted bit line bar BL change complementarily.

The memory cell array 51 is divided into a regular memory cell area 51a and a redundant memory cell area 51b. A pair of bit line pair BL and bar BL is assigned to the redundant memory cell area 51b. Each memory cell 52 connected to the pair of bit line pair BL and bar BL constitutes one redundant column.

Each word line WL is connected to a row decoder 54. When the row address is designated from the outside, the row address is given to the row decoder 54 via the row address buffer 55. Then, by the row decoder 54,
The word line WL corresponding to the row address is selected.

Each sense amplifier 53 is connected to the input / output line I / O and the inverted input / output line bar I / O via each transfer gate 56. The input / output line I / O and the inverted input / output line bar I / O are connected to the read amplifier (RA) 57. The read amplifier 57 is connected to the data output circuit 58 via the data bus DB and the inverted data bus bar DB. I / O line I / O and inverted I / O line bar I / O,
The levels of the data bus DB and the inverted data bus bar DB change complementarily. Then, the output circuit 58 outputs the data to the outside.

Of the transfer gates 56, each transfer gate 56 corresponding to the regular memory cell area 51a is connected to a column decoder 59 via a column selection line CSL. Each transfer gate 56 includes an input / output line I / O, an inverted input / output line bar I / O, and a sense amplifier 53.
And a pair of NMOS transistors connected between and. Each transfer gate 56 is 1
It is connected to the column decoder 59 via the column selection line CSL. Therefore, when the column selection line CSL becomes H level, the pair of NMOS transistors forming the transfer gate 56 are turned on, and the transfer gate 56 is turned on.

In order to make the description easy to understand, the sense amplifier 53 connected to the bit line pair BL and bar BL in the redundant memory cell area 51b is referred to as "sense amplifier 53b". The transfer gate 56 connected to the sense amplifier 53b is referred to as "transfer gate 56b".

The transfer gate 56b is connected to the redundant column driver 60 via the redundant column selection line RCSL.
Therefore, when the redundant column selection line RCSL becomes H level, the pair of NMOS transistors forming the transfer gate 56b are turned on, and the transfer gate 56b is turned on.

When a column address is designated from the outside, the column address is transferred from the column address buffer 61 to the column decoder 59 and the address transition detector (ATD).
62 and spare decoder 63.

The ATD 62 detects a change in the column address, detects that the column address is designated from the outside, and generates a pulse signal ATD1 of one pulse. Its pulse signal ATD1
Is output to spare decoder 63 and delay circuit 64. That is, each time the column address changes, the pulse signal
ATD1 is generated.

The delay circuit 64 delays the pulse signal ATD1 by a predetermined time to generate a pulse signal ATD2 of one pulse. The pulse signal ATD2 is output to the column decoder 59 and the redundant column driver 60.

A nonvolatile element such as a fuse element is provided in the spare decoder 63, and the column address of the defective memory cell 52 is stored by the nonvolatile element. Before the DRAM manufacturer ships the DRAM manufacturer
A defective memory cell 52 is provided in the regular memory cell region 51a.
Inspect for. If there is a defective memory cell 52, the DRAM maker stores the column address of the defective memory cell 52 in the spare decoder 63.

Spare decoder 63 is activated when pulse signal ATD1 is input, and compares the stored column address of defective memory cell 52 with the externally designated column address. The spare decoder 63 generates a redundant signal RS of either H or L level when the column addresses match. The redundant signal RS is output to the column decoder 59 and the redundant column driver 60.

That is, each time the column address changes, the spare decoder 63 causes redundancy (defective memory cell 52).
Column address is externally specified) or non-redundant (when there is no defective memory cell 52 in the normal memory cell region 51a), or the column address of the defective memory cell 52 and the externally specified column address Is different).

The column decoder 59 is activated according to the redundancy signal RS and the pulse signal ATD2 and selects a column (one set of bit line pair BL, bar BL) of the memory cell array 51 corresponding to a column address externally designated. . That is, the column decoder 59 uses the redundancy signal of either the H or L level.
When RS is input, it becomes active standby state, and then
It is activated when the pulse signal ATD2 is input. Then, when activated, the column decoder 59 selects the column selection line CSL corresponding to the column address designated from the outside, and sets the column selection line CSL to the H level. Then, the column selection line
The transfer gate 56 connected to CSL is turned on. Therefore, the column of the memory cell array 51 corresponding to the column address designated from the outside is selected via the sense amplifier 53 corresponding to the transfer gate 56. The column of the memory cell array 51 selected by the column decoder 59 is a regular memory cell region 51a.
Is within.

The redundant column driver 60 is activated according to the redundant signal RS and the pulse signal ATD2 to select a column (one set of bit line pair BL, bar BL) of the redundant memory cell area 51b. That is, the redundant column driver 60 enters the active standby state when the redundant signal RS of either the H level or the L level is input, and is activated when the pulse signal ATD2 is input thereafter. Then, the redundant column driver 60
Turns the redundant column selection line RCSL to H level when activated. Then, the transfer gate 56b connected to the redundant column selection line RCSL is turned on. Therefore,
A column of the redundant memory cell region 51b is selected via the sense amplifier 53b connected to the transfer gate 56b.

However, the level of the redundant signal RS that brings the redundant column driver 60 into the active standby state is different from that of the column decoder 59. H output from the spare decoder 63
Alternatively, in response to the redundant signal RS of either L level, only one of the column decoder 59 and the redundant column driver 60 is in the active standby state. Then, the column decoder 59 or the redundant column driver 60 in the active standby state is activated by the pulse signal ATD2.

In order to make the explanation easy to understand, it is assumed that the column decoder 59 is in the active standby state by the L level redundant signal RS, and the redundant column driver 60 is in the active standby state by the H level redundant signal RS.

Next, the read operation of the DRAM thus configured will be described. As described above, when there is a defective memory cell 52, the defective memory cell 5
The column address of 2 is stored in the spare decoder 63.

In order to read the data stored at a predetermined address of the memory cell array 51, first, its row address and column address are designated from the outside. When the row address is designated from the outside, the row address is given from the row address buffer 55 to the row decoder 54. Then, the row decoder 54 selects the word line WL corresponding to the row address. Each memory cell 52 is selected by selecting the word line WL. Then, the data stored in each memory cell 52 is transferred to the bit line BL or the inverted bit line bar BL.

Each sense amplifier 53, 53b uses a bit line pair BL, which is paired with a bit line BL to which each memory cell 52 is connected, as a reference, and a bit line pair.
BL and bar BL are sensed to amplify the data transferred to the bit line BL.

When a column address is designated from the outside, the column address is given from column address buffer 61 to column decoder 59, ATD 62 and spare decoder 63. The ATD 62 detects that the column address is designated from the outside by the change of the column address, generates the pulse signal ATD1 of 1 pulse, and outputs it to the spare decoder 63 and the delay circuit 64.

Spare decoder 63 is activated when pulse signal ATD1 is input and compares the stored column address of defective memory cell 52 with the externally designated column address. When both column addresses match, spare decoder 63 generates an H level redundant signal RS and outputs it to column decoder 59 and redundant column driver 60.

At this time, if there is no defective memory cell 52 in the normal memory cell region 51a or if the column address of the defective memory cell 52 is different from the column address designated from the outside, output from the spare decoder 63. The redundant signal RS thus set becomes L level. On the other hand, the defective memory cell 52
When the column address of is designated from the outside, the redundant signal RS output from the spare decoder 63 becomes H level.

When the redundant signal RS is at the L level, the column decoder 59 is in the active standby state and the redundant column driver 60.
Does not go into active standby. The delay circuit 64 delays the pulse signal ATD1 by a predetermined time to generate a one-pulse pulse signal ATD2 and outputs it to the column decoder 59 and the redundant column driver 60.

Since the redundant column driver 60 is not in the active standby state, it is not activated even when the pulse signal ATD2 is input. On the other hand, since the column decoder 59 is in the active standby state, it is activated when the pulse signal ATD2 is input.

When activated, the column decoder 59 selects a column selection line CSL corresponding to a column address externally designated, and sets the column selection line CSL to the H level. Then, the transfer gate 5 connected to the column selection line CSL
6 is turned on. Therefore, through the sense amplifier 53 corresponding to the transfer gate 56, the memory cell array 51 corresponding to the column address externally designated.
Column is selected. The selected memory cell array 5
The column 1 is in the regular memory cell area 51a.

As described above, by selecting the row (word line WL) and the column (bit line pair BL, bar BL) of the memory cell array 51 corresponding to the row address and the column address designated from the outside, the data is stored. One memory cell 52 corresponding to a predetermined address to be read is selected.
Only the data of the selected memory cell 52 is transferred from the sense amplifier 53 through the transfer gate 56 in the ON state to the input / output line I / O and the inverted input / output line bar.
Transferred to I / O. The data is transferred from the read amplifier 57 to the data output circuit 58 via the data bus DB and the inverted data bus bar DB, and output from the output circuit 58 to the outside.

As described above, when the redundant signal RS is at L level, the column decoder 59 is activated and the memory cells 52 in the normal memory cell area 51a corresponding to the row address and the column address designated from the outside are restored. The data is read from the selected memory cell 52.

When there is no defective memory cell 52 in the regular memory cell area 51a or when the column address of the defective memory cell 52 is different from the column address designated from the outside, the regular memory cell area 51a A normal access is performed to read the data.

Next, the case where the redundant signal RS is at the H level will be described. When the redundant signal RS is at the H level, the redundant column driver 60 is in the active standby state and the column decoder 59.
Does not go into active standby.

The delay circuit 64 uses the pulse signal as described above.
ATD2 is generated to generate column decoder 59 and redundant column driver 6
Output to 0. Since the column decoder 59 is not in the active standby state, it is not activated even when the pulse signal ATD2 is input. On the other hand, since the redundant column driver 60 is in the active standby state, it is activated when the pulse signal ATD2 is input.

When activated, the redundant column driver 60 sets the redundant column selection line RCSL to the H level. Then, the transfer gate 56b is turned on. Therefore, the column of the redundant memory cell region 51b is selected via the sense amplifier 53b connected to the transfer gate 56b.

As described above, the row (word line WL) of the memory cell array 51 corresponding to the row address designated from the outside.
Is selected. However, the column of the regular memory cell area 51a is not selected, and instead, the redundant memory cell area 51a is not selected.
Column b is selected. As a result, one memory cell 52 in the redundant memory cell area 51b is selected.

Only the data of the selected memory cell 52 is transferred from the sense amplifier 53b to the input / output line I / O and the inverted input / output line bar I / O through the transfer gate 56b in the ON state. . The data is output from the output circuit 58 to the outside, as described above.

As described above, when the redundant signal RS is at the H level, the redundant column driver 60 is activated and the redundant memory cell area 51b corresponding to the row address externally designated.
The memory cell 52 inside is selected, and data is read from the memory cell 52. That is, when the column address designated from the outside is the column address of the defective memory cell 52, the redundant memory cell area 51b is accessed and the data is read.

That is, when the column address of the defective memory cell 52 is designated from the outside, the redundant memory cell region 51b is used instead of the column of the normal memory cell region 51a.
The defective address is relieved by selecting the column.

Even in the write operation of the DRAM,
When the column address of the defective memory cell 52 is designated from the outside, the defective address is relieved in the same manner as the above read operation.

[0041]

The reason why the delay circuit 64 is provided in the above-mentioned conventional DRAM is to prevent the column decoder 59 and the redundant column driver 60 from being activated at the same time.

The read operation of the DRAM when the delay circuit 64 is omitted will be considered below. In this case, the pulse signal ATD1 from the ATD 62 is transmitted to the column decoder 5
9 and the redundant column driver 60 will be directly input. The spare decoder 63 is activated when the pulse signal ATD1 is input, and generates the redundant signal RS of either H or L level based on the column address designated from the outside. Therefore, the pulse signal ATD1 is first input to the column decoder 59 and the redundant column driver 60, and then the redundant signal based on the column address externally specified.
RS will be input.

However, since the level of the redundant signal RS output from the spare decoder 63 is only H or L, the level of the redundant signal RS is H even in the initial state where the column address is externally specified. It is considered to be either L or L.

For example, in the initial state, the redundancy signal RS is H
Suppose you are at a level. Then, in the initial state, the redundant column driver 60 is in the active standby state, and the column decoder 59 is not in the active standby state. Therefore, when the pulse signal ATD1 is output from the ATD 62, first, the redundant column driver 60 in the active standby state is activated. Then, by the spare decoder 63 activated by the pulse signal ATD1,
It is assumed that an L level redundant signal RS (a level opposite to the initial state) is generated based on a column address designated from the outside. Then, the column decoder 59 to which the pulse signal ATD1 is already input jumps over the active standby state and is activated at the time when the redundancy signal RS of L level is input. At this time, since the redundant column driver 60 is already activated, the column decoder 59 and the redundant column driver 60 are activated at the same time.

On the contrary, in the initial state, the redundant signal RS is L
Suppose you are at a level. Then, in the initial state, the column decoder 59 is in the active standby state, and the redundant column driver 60 is not in the active standby state. Therefore, when the pulse signal ATD1 is output from the ATD 62, first, the column decoder 59 in the active standby state is activated. Then, the pulse signal AT
It is assumed that the spare decoder 63 activated by D1 generates an H level redundant signal RS (a level opposite to the initial state) based on a column address externally designated. Then, the redundant column driver 60 to which the pulse signal ATD1 has already been input jumps over the active standby state and is activated at the time when the H level redundant signal RS is input. At this time, since the column decoder 59 has already been activated, the column decoder 59 and the redundant column driver 60 are activated at the same time.

As described above, when the delay circuit 64 is not provided, when the level of the redundant signal RS generated based on the column address externally specified is the opposite level to that in the initial state, the column Decoder 59 and redundant column driver 60
And are activated at the same time.

When the column decoder 59 and the redundant column driver 60 are activated at the same time, the memory cell 2 in the normal memory cell region 51a and the memory cell 52 in the redundant memory cell region 51b are doubly selected. It will be. Then
Each data stored in each of the doubly selected memory cells 52 is input / output line I / O and inverted input / output line bar I / O.
Transferred to O. However, only one data can exist in the input / output line I / O and the inverted input / output line bar I / O. Therefore, in the input / output line I / O and the inverted input / output line bar I / O, data destruction occurs in which two data are mutually destroyed. As a result, desired data is not transferred to the read amplifier 57, and the desired data is output to the output circuit 58.
Cannot be output from the outside.

Therefore, by providing the delay circuit 64, the pulse signal ATD1 is delayed by a predetermined time to generate a pulse signal ATD2, and the column decoder 59 and the redundant column driver 6 are generated.
That is, 0 and 0 are prevented from being activated at the same time.
That is, the output timing of the pulse signal ATD2 by the delay circuit 64 is set to be after the redundant signal RS based on the column address externally specified is output from the spare decoder 63. That is, the delay circuit 64 has a pulse signal corresponding to the operation time of the spare decoder 63 (the time from the activation by the pulse signal ATD1 to the generation of the redundant signal RS based on the externally designated column address).
Delays ATD2. This prevents the memory cells 52 in the regular memory cell area 51a and the memory cells 52 in the redundant memory cell area 51b from being double-selected, and the input / output line I / O and the inverted input / output line Data corruption in bar I / O can be avoided.

However, the provision of the delay circuit 64 causes a problem that the access time required for reading data is increased and the speeding up of information processing in the semiconductor device is hindered.

Further, the spare decoder 63 determines whether it is redundant or non-redundant (operation of generating a redundant signal RS).
However, there is also a problem that large power consumption is required. This is redundant or non-redundant by supplying a current to all of the nonvolatile elements provided in the spare decoder 63 which are in the ON state (not disconnected when the fuse element is used as the nonvolatile element). This is because it is determined whether it is redundant.

By the way, in the DRAM shown in FIG. 6, since only one redundant column is provided in the redundant memory cell region 51b, there are two or more columns including the defective memory cell 52 in the regular memory cell region 51a. In some cases, the defective address is not relieved for one column. Such a problem can be avoided by providing a large number of redundant columns. However, even if the number of redundant columns is increased too much, the area of the chip increases and the yield deteriorates.

In a semiconductor memory device without using a DRAM, the memory cell array is generally divided into a plurality of blocks (macro blocks). Therefore, depending on the distribution of defective memory cells, some blocks do not need to be repaired because there are no defective memory cells, and some blocks cannot be repaired because there are too many defective memory cells.

For example, the 16 Mbit DRA shown in FIG.
Consider the M100. 16Mbit DRAM1
00 is composed of four 4M bit blocks 101 to 104. Then, each block 101 to 10
The circuit of the above-described embodiment is incorporated in each block 4, and defective addresses are individually relieved in each of the blocks 101 to 104. Therefore, among the blocks 101 to 104, for example, the block 10 may be selected depending on the distribution of defective memory cells.
It is possible that defective memory cells that cannot be repaired exist only in No. 3, and all defective memory cells can be repaired in the remaining three blocks 101, 102, and 104. In such a case, since only the block 103 is defective, the entire 16 Mbit DRAM 100 is defective.

As described above, in a plurality of blocks in the semiconductor memory device, only some of the blocks cannot be repaired. Therefore, although the other blocks can be repaired, the chip becomes defective and the yield is increased. There was a problem that was worse.

The present invention has been made to solve the above problems, and an object thereof is to provide a storage device capable of improving the yield.

[0056]

The gist of the invention according to claim 1 is to obtain a predetermined storage capacity by combining an arbitrary number of adjacent macroblocks arranged on a wafer.

By doing so, a storage device having a predetermined storage capacity can be obtained by combining only relievable macroblocks, so that the yield can be improved. Further, if there is a macroblock that cannot be repaired, each macroblock can be separated and only the macroblock that can be repaired can be commercialized.

According to a second aspect of the present invention, a predetermined storage capacity is obtained by combining an arbitrary number of adjacent macroblocks arranged on the wafer, and the macroblocks to be combined are connected in advance by wiring. The point is to put it.

In this way, in addition to the action and effect of the invention described in claim 1, it is not necessary to connect between the macro blocks at the assembly stage, and the manufacturing is facilitated.
According to a third aspect of the present invention, a predetermined storage capacity is obtained by combining an arbitrary number of adjacent macro blocks arranged on a wafer, and at least a part of a pad or a peripheral circuit is provided between the combined macro blocks. The point is that they are shared.

In this way, in addition to the operation and effect of the invention described in claim 1, the area occupied on the wafer is reduced and the size is increased as compared with the case where the pad or the peripheral circuit is provided for each macro block. It can be integrated.

[0061]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described with reference to D having redundant columns.
One embodiment embodied in a RAM will be described with reference to FIGS. In the present embodiment, the same components as those in the conventional example shown in FIG. 6 are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 1 is a block circuit diagram showing the basic configuration of this embodiment. The present embodiment differs from the conventional example in the following points. [1] The column decoder 59 of the conventional example is replaced with a column decoder CD in this embodiment.

[2] The redundant column driver 60 of the conventional example is replaced with the redundant column decoder RCD in this embodiment. The redundant column decoder RCD is arranged closer to the column address buffer 61 than the column decoder CD on the semiconductor substrate (chip) on which the DRAM is formed.

[3] The column address designated from the outside is
It is applied from column address buffer 61 to column decoder CD and redundant column decoder RCD via column address bus CAB.

[4] The conventional ATD 62, the spare decoder 63, and the delay circuit 64 are omitted in this embodiment. The column decoder CD is a column (1
Column decoders CD1 to CDN (CD1, CD2, CD3) respectively provided corresponding to a pair of bit line pairs BL, BL)
... CDn, CDn + 1 ... CDN-1, CDN). The column decoders CD1 to CDN have the same internal structure, and a spare decoder 1 is provided in each column decoder CD1 to CDN.

Each spare decoder 1 is provided with a non-volatile element such as a fuse element, and the non-volatile element connects the memory cell connected to the column of the memory cell array 51 corresponding to the column decoder CD1 to CDN. It is stored whether 52 is defective or not. DRAM makers are
Before shipping the DRAM, it is inspected whether or not there is a defective memory cell 52 in the regular memory cell region 51a. If there is a defective memory cell 52, the DRAM maker always turns off the nonvolatile element of the spare decoder 1 in the column decoders CD1 to CDN corresponding to the defective memory cell 52 (non-volatile). If a fuse element is used as the conductive element, disconnect it. As a result, the column decoders CD1 to CD corresponding to the defective memory cell 52 are
N is always inactive regardless of the externally specified column address.

That is, the corresponding memory cell array 51
Column decoders CD1 to CDN (hereinafter referred to as defective column decoders CD1 to CDN) including at least one defective memory cell 52 in each column.
Is always inactive regardless of the column address specified from the outside.

On the other hand, all the memory cells 52 connected to the corresponding column of the memory cell array 51 have no defect in column decoders CD1 to CDN (hereinafter referred to as excellent column decoders CD1 to CDN).
DN) is activated when the corresponding column address is externally designated. Therefore, if a column address is designated from the outside and the column address is not the column address of the defective memory cell 52, the column of the memory cell array 51 corresponding to the excellent column decoder CD1 to CDN corresponding to the designated column address is selected. select. That is, the excellent column decoders CD1 to CD corresponding to the column address designated from the outside
DN sets the connected column selection line CSL to H level. Then, the transfer gate 56 connected to the column selection line CSL is turned on. Therefore, the column of the memory cell array 51 corresponding to the column address designated from the outside is selected via the sense amplifier 53 corresponding to the transfer gate 56. The columns of the memory cell array 51 selected by the excellent column decoders CD1 to CDN are in the regular memory cell region 51a.

The spare decoder 1 need only store whether the column decoders CD1 to CDN are defective or excellent. Therefore, only one non-volatile element needs to be provided in the spare decoder 1, and the spare decoder 6 of the conventional example that must store all column addresses.
3, the circuit scale of the spare decoder 1 becomes so small that it cannot be compared. Therefore, each column decoder CD1 to CD
Even if the spare decoder 1 is provided in DN, the circuit scale of the DRAM as a whole does not increase.

Further, the spare decoder 63, as described above, carries out an operation of judging whether the column address is redundant or non-redundant. On the other hand, in the present embodiment, A
Since the TD 62 is omitted, the change of the column address is not detected, and the spare decoder 1 does not perform the operation of determining whether it is redundant or non-redundant like the spare decoder 63. Therefore, in the present embodiment in which the spare decoder 1 is provided, there is no increase in power consumption due to the spare decoder 63 as in the conventional example.

A spare decoder 2 is provided in the redundant column decoder RCD. A nonvolatile element such as a fuse element is provided in the spare decoder 2, and the column address of the defective memory cell 52 (that is, the column address corresponding to the defective column decoders CD1 to CDN) is provided by the nonvolatile element. Remembered DRAM makers are
If there is a defective memory cell 52 in the inspection before shipment of the DRAM, the column address of the defective memory cell 52 is stored in the spare decoder 2. Spare decoder 2
Activates the redundant column decoder RCD only when the externally designated column address is the column address of the defective memory cell 52.

When the redundant column decoder RCD is activated, it sets the redundant column selection line RCSL to H level. Then, the transfer gate 56b connected to the redundant column selection line RCSL.
Is turned on. Therefore, the transfer gate 56
The column of the redundant memory cell area 51b is selected via the sense amplifier 53b connected to b.

By the way, the spare decoder 2 need only store the column address of the defective memory cell 52.
The circuit scale can be made smaller than that of the conventional spare decoder 63. Further, the spare decoder 2 does not perform the operation of determining whether it is redundant or non-redundant like the spare decoder 63. Therefore, in the present embodiment in which the spare decoder 2 is provided, there is no increase in power consumption due to the spare decoder 63 as in the conventional example.

However, since the spare decoder 2 stores the column address, the circuit scale becomes larger than that of the spare decoder 1. Therefore, the circuit scale of the redundant column decoder RCD is larger than that of the column decoder CD, and as a result, the signal processing inside the redundant column decoder RCD becomes complicated.
However, the redundant column decoder RCD is arranged closer to the column address buffer 61 than the column decoder CD on the chip. Therefore, the operating speed of the column decoder CD (the column decoder CD after the column address is specified from the outside
(Time until the column selection line CSL is set to H level)
On the other hand, the operating speed of the redundant column decoder RCD (the time from when the column address is specified from the outside until the redundant column selection line RCSL is set to the H level by the redundant column decoder RCD)
Are equal to or higher. Therefore, there is no possibility of imbalance in the read operation between the case of using the column decoder CD and the case of using the redundant column decoder RCD. It should be noted that such an imbalance in the read operation does not occur unless the scale of the memory cell array 1 becomes larger than a certain level. Therefore, when the scale of the memory cell array 1 is small, it is not always necessary to arrange the redundant column decoder RCD near the column address buffer 61 on the chip.

As described above, in this embodiment, the defective column decoders CD1 to CDN are always inactive. The excellent column decoders CD1 to CDN and the redundant column decoder RCD are activated only when the corresponding column address is designated from the outside.

Therefore, when the externally designated column address is the column address of the defective memory cell 52, the redundant column decoder RCD is activated and the column of the redundant memory cell region 51b is selected. At this time, the column decoders CD1 to C corresponding to the column address externally specified
Since DN is a defective column decoder, it is in an inactive state, and the column of the regular memory cell area 51a is not selected. Therefore, the memory cell 2 in the regular memory cell area 51a and the memory cell 52 in the redundant memory cell area 51b are not double-selected, and the input / output line I / O
Data destruction does not occur in the I / O and inverted I / O line bar I / O.

That is, when the externally designated column address is the column address of the defective memory cell 52, the redundant column decoder RCD is used instead of the defective column decoders CD1 to CDN. That is, the redundant memory cell area 51b is used instead of the regular memory cell area 51a column.
The defective address is relieved by selecting the column.

If the externally designated column address is not the column address of the defective memory cell 52, the excellent column decoders CD1 to CDN select the column of the regular memory cell area 51a. At this time, since the redundant column decoder RCD is in the inactive state, the normal memory cell region 51a and the redundant memory cell region 51b are not selected twice, and the input / output line I / O and the inversion line are not selected. No data corruption in the I / O bar I / O.

In the present embodiment, the operation of reading data from the selected memory cell area 51 is the same as that of the conventional example, and therefore its explanation is omitted. Also, DRAM
Also in the write operation, if the column address of the defective memory cell 52 is designated from the outside, the defective address is relieved in the same manner as the above read operation.

As described above, according to the present embodiment, it is possible to avoid an increase in access time, which is caused by the delay circuit 64, as in the conventional example, and it is possible to speed up information processing in the semiconductor device. . Further, according to the present embodiment, it is possible to avoid an increase in power consumption, which is caused by the spare decoder 63 as in the conventional example, and it is possible to reduce power consumption.

FIG. 2 is a circuit diagram of an embodiment embodying an arbitrary column decoder CDn among the column decoders CD1 to CDN. In this embodiment, the address groups A to
A column address bus CAB is formed by C. The address group A is composed of column addresses a1 to a4, the address group B is composed of column addresses b1 to b4, and the address group C is composed of column addresses c1 to c4. That is, in the present embodiment, 64 pairs of bit line pairs BL and BL are provided, and 64 column decoders C are provided.
D1 to CDN = 64 are provided. Each column address a1
c4 becomes L level in the inactive state and H level in the active state. In addition, each address a of each address group A to C
Only one address is activated among 1 to c4.

To each of the column decoders CD1 to CDN, one column address a1 to c4 from each address group A to C is combined and connected. In this column decoder CDn, column addresses a2, b2, c2
Are combined and connected. That is, of the column addresses designated from the outside, the column address corresponding to the column decoder CDn is represented by the combination of the column addresses a2, b2, c2.

The column decoder CDn is composed of NMOS transistors n1 to n3, PMOS transistors p1 to p4, an inverter 11 and a fuse element F1 and is connected to the high potential side power supply VCC and the ground serving as the low potential side power supply. . The spare decoder 1 is composed of NMOS transistors n1 to n3, PMOS transistors p1 to p3, and a fuse element F1. In the column decoder CDn thus constructed, the column addresses a2, b
When both 2 and c2 are activated (H level), the column decoder CDn is activated. That is, the column address a2
When b2 and c2 are all at the H level, all the NMOS transistors n1 to n3 are turned on, and the fuse element F1 and the NMOS transistor n1 are connected to the input side of the inverter 11.
The output side (column selection line CSL) of the inverter 11 is set to the H level by being pulled down to the ground side via .about.n3.

On the other hand, when at least one of the column addresses a2, b2 and c2 is inactive (L level), the column decoder CDn is inactive. That is, when at least one of the column addresses a2, b2, c2 is at the L level, the PMOS
Since any one of the transistors p1 to p3 is turned on and one of the NMOS transistors n1 to n3 is turned off, the input side of the inverter 11 has a high potential via the turned on PMOS transistors p1 to p3. It is pulled up to the side power supply VCC side, and the output side (column selection line CSL) of the inverter 11 becomes L level.

Here, if the fuse element F1 is cut,
The column selection line CSL is latched to the L level by the inverter 11 and the PMOS transistor p4, and the column decoder C
Dn remains inactive. Then, when the column addresses a2, b2, c2 corresponding to the column decoder CDn are designated from the column address bus CAB (a2, b2, c2).
Column select line CSL remains latched at the L level and the inactive state of the column decoder CDn is maintained.

By thus cutting the fuse element F1, the column decoder CDn can always be made inactive as a defective column decoder regardless of the column address designated from the outside.

FIG. 3 is a circuit diagram of an embodiment embodying the redundant column decoder RCD. Redundant column decoder RCD
Are NMOS transistors n11, n12, na1 to n
c4, inverters 12, 13 and 4-input NAND 14,
Redundancy enable fuse element FR, fuse element Fa1
To Fc4, they are connected to the high-potential-side power supply VCC and the ground serving as the low-potential-side power supply. The spare decoder 2 includes NMOS transistors n11, n12,
It comprises na1 to nc4, an inverter 12, a redundancy enable fuse element FR, and fuse elements Fa1 to Fc4. The NMOS transistors na1 to nc4 and the fuse elements Fa1 to Fc4 are provided corresponding to the column addresses a1 to c4, respectively.

Here, when the fuse element F1 is cut in the column decoder CDn shown in FIG. 2 (that is, when the defective column decoder CDn is used), the defective column decoder C is selected.
Consider the case where the redundant column decoder RCD is activated instead of Dn.

In this case, the column addresses a2, b2, c2 of the defective column decoder CDn may be stored in the spare decoder 2. Therefore, as shown in FIG. 3, the redundancy enable fuse element FR and each column address a2, b2, c2.
The fuse elements Fa1, Fb2, Fc2 corresponding to the above may be disconnected from the fuse elements Fa1-Fc4.

When the redundant enable fuse element FR is not cut, the redundant column decoder RCD can be inactivated when there is no defective memory cell 52 in the regular memory cell region 51a. That is, if the redundancy enable fuse element FR is not cut, the inverter 12
Is pulled up to the high-potential side power supply VCC side via the redundancy enable fuse element FR, and the output side of the inverter 12 (input side of the NAND 14) becomes L level. Therefore, the output side of the inverter 13 (redundant column selection line RCSL)
Goes to the L level, and the redundant column decoder RCD is kept in the inactive state.

Column address a2 of defective column decoder CDn
In order to store b2 and c2 in the spare decoder 2, first, the redundant enable fuse element FR is cut, and the fuse elements Fa1 to Fc4 except the fuse elements Fa2, Fb2 and Fc2 are cut. And DRAM
When the power is turned on, a one-shot pulse OSP is applied to the gate of the NMOS transistor n11. Then NMOS
The transistor n11 turns on, the input side of the inverter 12 is pulled down to the ground side, the output side of the inverter 12 becomes H level, and the NMOS transistor n12 turns on. As a result, the output side of the inverter 12 is latched at H level by the NMOS transistor n12, and each N
All the MOS transistors na1 to nc4 are turned on, and the redundant column decoder RCD enters the active standby state. After that, the column address a2 corresponding to the defective column decoder CDn
If b2 and c2 are specified from the column address bus CAB (a
2, b2, c2 are all H level), redundant column decoder RC
D is activated to set the redundant column selection line RCSL to H level.

As described above, on the chip,
The redundant column decoder RCD is arranged closer to the column address buffer 61 than the column decoder CD. Therefore, in the redundant column decoder RCD, the column addresses a1 to c4 from the column address bus CAB correspond to the NMOS transistors na1 to nc4, the fuse elements Fa1 to Fc4, and the NA.
Despite being transmitted to the memory cell 52 via the ND 14, it has an operating speed equal to or higher than that of each column decoder CD1 to CDN.

FIG. 4 is a circuit diagram of another embodiment embodying the redundant column decoder RCD. In FIG. 4, the same components as those of the redundant column decoder RCD shown in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted.

The redundant column decoder RCD includes NMOS transistors na1 to nc4, an inverter 13 and a NAND1.
4 and fuse circuits f1 and fa1 to fc4. The spare decoder 2 is an NMOS transistor na.
1 to nc4 and fuse circuits f1 and fa1 to fc4. Each NMOS transistor na1 to n
c4 and the fuse circuits fa1 to fc4 are respectively
It is provided corresponding to each column address a1 to c4.

FIG. 5 shows the fuse circuits f1, fa1 to fc.
4 is an internal circuit diagram of FIG. As shown in FIG. 5A, the fuse circuits f1 and fa1 to fc4 include NMOS transistors n21 and n22, an inverter 21, and a fuse element F2.
And is connected to the high-potential-side power supply VCC and the ground serving as the low-potential-side power supply. In addition, in FIG.
The fuse circuits f1 and fa1 to fc4 shown in FIG. 5A are shown as black boxes as shown in FIG. 5B.

Here, when the fuse element F1 is cut in the column decoder CDn shown in FIG. 2 (that is, when the defective column decoder CDn is used), the defective column decoder C is selected.
Consider the case where the redundant column decoder RCD is activated instead of Dn.

In this case, the column addresses a2, b2, c2 of the defective column decoder CDn may be stored in the spare decoder 2. Therefore, the fuse element F2 inside the fuse circuit f1 and each fuse element F2 inside each fuse circuit fa2, fb2, fc2 corresponding to each column address a2, b2, c2 may be cut off. In FIG. 5, the fuse circuits f1 and f for cutting the fuse element F2 are used.
A mark is attached to a2, fb2, and fc2.

When the fuse element F2 of the fuse circuit f1 is not cut, the redundant column decoder RC is used when there is no defective memory cell 52 in the normal memory cell region 51a.
D can be deactivated. That is, unless the fuse element F2 of the fuse circuit f1 is cut off, the input side of the inverter 21 is pulled up to the high potential side power source VCC side via the fuse element F2, and the output side of the inverter 21 (input side of the NAND 14) is L level. Become a level. Therefore, the output side of the inverter 13 (redundant column selection line RCSL) is L
Goes high and the redundant column decoder RCD remains inactive.

The column address a2 of the defective column decoder CDn
In order to store b2 and c2 in the spare decoder 2, first, the fuse element F2 of the fuse circuit f1 is cut and the fuse elements F2 of the fuse circuits f1, fa2, fb2 and fc2 are cut. When the DRAM is powered on, the one-shot pulse OSP is applied to the gate of each NMOS transistor n22 of each fuse circuit f1, fa1 to fc4.

Then, the fuse circuits f1, fa2, f
In b2 and fc2, each NMOS transistor n22
Turns on, the input side of each inverter 21 is pulled down to the ground side, the output side of each inverter 21 becomes H level, and each NMOS transistor n21 turns on. Therefore, the output side of each inverter 21 is latched at the H level by each NMOS transistor n21.

As a result, each fuse circuit fa2, fb
2, NMOS transistors na connected to fc2
2, nb2 and nc2 are turned on, and the redundant column decoder RCD enters the active standby state. After that, the defective column decoder C
When the column addresses a2, b2, c2 corresponding to Dn are designated from the column address bus CAB (a2, b2, c2 are all at H level), the redundant column decoder RCD is activated and the redundant column selection line RCSL is set at H level. To do.

As described above, when the defective column address CDn is stored in the spare decoder 2, the redundant column decoder RCD shown in FIG. 3 cuts ten fuse elements, whereas the redundant column decoder RCD shown in FIG. Then, it is only necessary to cut the four fuse elements F2. Therefore, FIG.
The redundant column decoder RCD shown in FIG. 4 has a larger circuit scale than the redundant column decoder RCD shown in FIG.
T required for relief of defective address during mass production of RAM
AT (Turn Around Time) can be shortened.

The above embodiment shown in FIGS. 1 to 5 may be modified as follows, and in that case, the same operation and effect can be obtained. (1) Each of the sense amplifiers 53, 53a may be of a type other than the cross couple latch type (for example, a current mirror type,
Bipolar type, single-ended type, etc.).

(2) Each transfer gate 56, 56
The NMOS transistor forming b is replaced with a PMOS transistor. In this case, the transfer gates 56 and 56b can be turned on by setting the column selection line CSL and the redundant column selection line RCSL to L level.

(3) Two or more sets of bit line pairs BL, BL are assigned to the redundant memory cell area 51b. That is,
Provide two or more redundant columns. (4) Fuse element F1, fuse elements Fa1 to Fc
4. The redundancy enable fuse element FR is replaced with another nonvolatile element (EEPROM (Electrically Erasable and Program)
rammable Read Only Memory), MNOS (Metal Nitr)
ide Oxide Semiconductor), MAOS (Metal Alumin)
a Oxide Semiconductor), MAS (Metal Alumina Se)
miconductor), FAMOS (Floating gate Avalanch)
e injection MOS), SAMOS (Stacked Gate Avala)
nche injection MOS), etc.).

(5) D having redundant rows instead of redundant columns
Applies to RAM. Also, DR with redundant columns and rows
Applies to AM. (6) SRAM (Static Random Access Memory) and R
It is applied to redundant circuit technology in OM (Read Only Memory).

By the way, in the above embodiment, since only one redundant column is provided in the redundant memory cell region 51b, when there are two or more columns including the defective memory cell 52 in the normal memory cell region 51a. Defective addresses are not relieved for one column. Such a problem can be avoided by providing a large number of redundant columns. However, even if the number of redundant columns is increased too much, the area of the chip increases and the yield deteriorates.

An embodiment in which the present invention is embodied in a DRAM will be described below with reference to FIGS. FIG. 7A shows the arrangement of the 16 Mbit DRAM 111 on the wafer 110, and FIG. 7B shows the 16 Mbit DRAM 111. The 16M-bit DRAM 111 has four 4
It is composed of M bit blocks (4 M bit DRAM, 4 M bit macro blocks) 121 to 124. The circuit of the above embodiment is incorporated in each of the blocks 121 to 124.
At 4, the defective addresses are relieved individually.

When all the blocks 121 to 124 can be repaired (non-defective products), they are separated by the solid line α and pads (not shown) other than the input / output (I / O) pads (not shown) in the blocks 121 to 124 are shown. Connected at the assembly stage. As a result, it is possible to commercialize the 16-Mbit DRAM 111 in which the blocks 121 to 124 are combined. In this case, each block 121 to 124 is set to x4.
With the configuration, the 16 Mbit DRAM 111 has a x16 configuration. In addition, in each of the blocks 121 to 124,
If the CASV pad and the WEV pad can be moved independently, it is possible to support a byte operation.

On the other hand, if any of the blocks 121 to 124 cannot be repaired, they can be separated along the dotted line β and only the repairable block can be commercialized as a 4M bit DRAM.

As shown in FIG. 8, the I / O pad 131
If the pads 132 other than the above are arranged and the pads 132 are connected in advance with the wiring (metal wiring, polysilicon wiring, etc.) M, as described above, it is not necessary to connect the pads 132 at the assembly stage. Manufacturing is easy.
Also in this case, since the wiring M is also separated by separating it by the dotted line β, only the relievable block among the blocks 121 to 124 can be commercialized as a 4M-bit DRAM.

Further, as shown in FIG. 9, the high potential side power source V
It is also conceivable to provide a circuit composed of a high resistance R connected between CC and ground and a fuse element f, and arrange the fuse element f on the dotted line β. In this case, the signals A and B are at the H level when they are separated by the solid line α to be commercialized as the 16 Mbit DRAM 111, and when the blocks 121 to 124 are commercialized as the 4 Mbit DRAM by being separated by the dotted line β. A and B become L level. Therefore,
If the DRAM specifications (refresh, operation mode, power supply voltage, etc.) are designed in advance so as to be switched by the signals A and B, the specifications can be changed between the 16 Mbit DRAM 111 and the 4 Mbit DRAM (121 to 124). .

Further, as shown in FIG. 10, two adjacent 4M bit blocks 121 and 122 form an 8M bit DRAM 151. And each block 12
Each pad 1 other than I / O pad (not shown) between 1 and 122
44 are arranged, and the respective pads 144 are connected in advance by the wiring M. Further, a peripheral circuit 143 is arranged between the blocks 121 and 122, and the peripheral circuit 143 and each block 1
21 and 122 are connected in advance by a wiring M. In this case, the difference from the DRAM shown in FIG. 8 is that each pad 144 and the peripheral circuit 14 between the two blocks 121 and 122 are different.
3 is shared. And both blocks 1
When both 21 and 122 can be repaired, the 8M-bit DRAM 151 is commercialized by disconnecting with a solid line α. If only the block 121 cannot be repaired, it is separated by the dotted line β1, and if only the block 122 cannot be repaired, it is separated by the dotted line β2, so that only one of the blocks 121 and 122 is formed as a 4M bit DRAM. Commercialize. In this way, the two blocks 121, 1
If the pads 144 and the peripheral circuit 143 are shared between the blocks 22, the area occupied on the wafer 110 is reduced and high integration is achieved as compared with the case where the pads and the peripheral circuits are provided for each of the blocks 121 and 122. be able to.

As described above, by designing each block of the semiconductor memory device to function independently as a semiconductor memory device, it is possible to reduce wasteful portions on the wafer and reduce manufacturing cost. Become. Further, since semiconductor memory devices having different capacities can be manufactured simultaneously on the same wafer,
It is possible to respond flexibly to market trends. And by designing 4M bit DRAM (121-124), 16M bit DRAM 111 and 8M bit DRA
Since a plurality of semiconductor memory devices having different capacities can be designed at the same time as the M151 can be designed, the design period can be shortened. Further, in the DRAM, it is possible to develop various products such as byte operations.

Note that FIGS. 7 and 8 show an example in which one DRAM is divided into four, and FIG. 10 shows an example in which one DRAM is divided into two, but one DRAM is divided into three or five. It may be divided into two or more. Also, 4
One 4Mbit DRAM for one 16Mbit D
Rather than configuring RAM, four 256 Mbit D
You may make it comprise one 1-Gbit DRAM by RAM. Further, in the example shown in FIG. 10, not all the pads 144 and the peripheral circuit 143 are shared between the blocks 121 and 122, but only a part of each pad 144 and the peripheral circuit 143 is shared. May be. In addition, the invention may be applied not only to DRAMs but also to semiconductor memory devices in general and to not only semiconductor memory devices but also memory devices in general.

[0116]

As described in detail above, according to the present invention, it is possible to provide a memory device capable of improving the yield.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment.

FIG. 2 is a circuit diagram of a main part of one embodiment.

FIG. 3 is a circuit diagram of a main part of one embodiment.

FIG. 4 is a circuit diagram of a main part of one embodiment.

FIG. 5 is a circuit diagram of a main part of one embodiment.

FIG. 6 is a block circuit diagram of a conventional example.

FIG. 7 is a block diagram of an embodiment.

FIG. 8 is a block diagram of an embodiment.

FIG. 9 is a block diagram of an embodiment.

FIG. 10 is a block diagram of an embodiment.

FIG. 11 is a block diagram of a conventional example.

[Explanation of symbols]

 110 ... Wafer 121-124 ... Macroblock 143 ... Peripheral circuit 144 ... Pad M ... Wiring

Claims (3)

[Claims] 1. A storage device which obtains a predetermined storage capacity by combining an arbitrary number of adjacent macroblocks arranged on a wafer. 2. A storage device in which a predetermined storage capacity is obtained by combining an arbitrary number of adjacent macroblocks arranged on a wafer, and each macroblock to be combined is connected in advance by wiring. 3. A predetermined storage capacity is obtained by combining an arbitrary number of adjacent macro blocks arranged on a wafer, and at least a part of a pad or a peripheral circuit is shared between the combined macro blocks. Storage device to put.