US5056005A - Data buffer device using first-in first-out memory and data buffer array device - Google Patents

Data buffer device using first-in first-out memory and data buffer array device Download PDF

Info

Publication number
US5056005A
US5056005A US07/337,399 US33739989A US5056005A US 5056005 A US5056005 A US 5056005A US 33739989 A US33739989 A US 33739989A US 5056005 A US5056005 A US 5056005A
Authority
US
United States
Prior art keywords
line
signal
data
chip selection
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US07/337,399
Other languages
English (en)
Inventor
Katsuyuki Kaneko
Satoshi Gokita
Koji Zaiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. reassignment MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: GOKITA, SATOSHI, KANEKO, KATSUYUKI, ZAIKI, KOJI
Application granted granted Critical
Publication of US5056005A publication Critical patent/US5056005A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Definitions

  • the present invention relates to a buffer device for data on a bus or a data buffer device, and more particularly to a data buffer device in which data is inputted and outputted with a plurality of words as a minimum unit, and a data buffer array device in which such devices are arrayed one-dimensionally or two-dimensionally.
  • a device designation signal (which is usually an address signal or device selection signal) must assure,. predetermined set-up time and hold time relative to a read strobe signal or write strobe signal.
  • the bus may be used without waste by preassigning a time in which the bus may be used for the data transfer by staggering the times for three stages, that is, send-out of the device designation signal, acknowledgement of availability of the designated device and transfer of data.
  • each device must have a relatively complex bus control unit and a waste time corresponding to several pipeline stages takes place if the designated device is not available.
  • a data buffer device has a FIFO memory which outputs a post input/output flag prior to the completion of input/output of N words, where N (N>2) is a minimum transfer unit of words on the bus.
  • N N (N>2) is a minimum transfer unit of words on the bus.
  • a chip selection input signal to the data buffer device is latched and it is held until the completion of the input/output.
  • the input/output of the FIFO memory is controlled by the latched chip selection input signal, and the output of the flag of the FIFO memory is controlled by an unlatched chip selection input signal.
  • the transfer data can be fully read or written by referring to the latched chip selection input signal, and the flag of the FIFO memory, that is, the acceptance of the next transfer may be checked by using the chip selection input signal as the next transfer destination.
  • FIG. 1 shows a block diagram of a data buffer device of the present invention
  • FIG. 2 shows a circuit diagram of a control circuit of the configuration shown in FIG. 1,
  • FIG. 3 shows waveforms for explaining an operation of the control circuit shown in FIG. 2,
  • FIG. 4 shows a configuration of a data buffer array device in which data buffer devices shown in FIG. 1 are arrayed one-dimensionally
  • FIG. 5 shows a configuration of a data buffer array device in which data buffer devices shown in FIG. 1 are arrayed two-dimensionally.
  • FIG. 1 shows a block diagram of one embodiment of the data buffer device of the present invention.
  • Numeral 1 denotes a FIFO memory which inputs and outputs 8 words as a unit.
  • the input/output of the FIFO memory is effected via a data input/output line 3 through an input/output circuit 2.
  • the FIFO memory 1 receives a strobe signal line 4, a reset signal line 5 and an input/output control signal line 6.
  • the FIFO memory 1 further has a FL flag output line 7 which indicates a full status and an EP flag output line 8 which indicates an empty status, as status signals of the FIFO memory 1.
  • Those flag signal lines output post input/output flags prior to the completion of the input/output of 8 words.
  • a logic gate 9 supplies the FL flag to an output circuit 10, and when the data is to be read, it supplies the EP flag to the output circuit 10.
  • the output circuit 10 is controlled by a chip selection input signal line 12, which is inputted to a latch 13.
  • An output of the latch 13 is connected to a chip selection output line 14.
  • a latch signal to the latch 13 is generated by a control circuit 15.
  • the FIFO memory 1 and the input/output circuit 2 are controlled by the chip selection output line 14.
  • the control circuit 15 counts the signals on the strobe signal line 4 and generates a signal to the latch 13 so that the latch 13 latches in the course of input/output of a series of 8 words and hold them until the end of the input/output.
  • the count of the counter is monitored by a gate 28.
  • a pulse is sent to a clock input of a flip-flop 29.
  • the flip-flop 29 is constructed to serve as a binary counter.
  • an output line 30 of the flip-flop 29 produces a signal which falls at a falling edge of the 0-th strobe signal and rises at a falling edge of the seventh strobe signal.
  • the signal on the chip selection input line 12 is held until the end of the eighth word data stored in the latch 13 is in synchronism with the falling edge of the strobe signal corresponding to the first word data (end of the first word data), that is, until the end of one transfer unit. Since the FIFO memory 1 and the input/output circuit 2 are controlled by the output of the latch 13, the subsequent seven words are transferred to the data buffer device which has been selected at the time of transfer of the first word data. On the other hand, since the flag output circuit 10 is controlled directly by the signal on the chip selection input line 12, the output of the flag output circuit 10 is controlled independently from the input/output of the data buffer device after the transfer of the first word data.
  • the equipment which accesses the data buffer devices may detect, the flag relating to the next transfer of the FIFO memory in the data buffer device whose data is being transferred, by holding the signal on the chip selection input line, and the flag of the FIFO memory in the data buffer device whose data is to be next transferred, by activating the chip selection input line of the data buffer device, while the equipment effects the input/output of the data.
  • FIG. 3 shows waveforms for such an operation.
  • Numerals 31-36 denote a signal on the reset signal line 31, a signal on the strobe signal line 32, a signal applied to the latch 13 from the control circuit 15, a signal on the chip selection input line 12 and a signal on the chip selection output line 14.
  • the counter in the control circuit 15 is initialized by the reset signal 31 so that it counts the subsequent input strobe signals 32.
  • the latch signal 34 reflects the status "0" of the counter.
  • the chip selection input signal 35 is latched by the latch 13 by the signal 34.
  • the chip selection signal 36 holds the chip selection input signal 35 which is present at the fall of the latch signal 34 until the count of the counter reaches "0" next time, as shown in FIG. 3. By denying the waveform 36, the chip is kept selected even if the chip selection input signal changes after the count of the counter has changed to "1".
  • FIG. 4 shows a block diagram of an array of data buffer devices in which a plurality of data buffer devices shown in FIG. 1 are arrayed.
  • Numerals 40-43 denote the data buffer devices shown in FIG. 1
  • numerals 44-59 denote data input/output line, flag output line, chip selection input line, chip selection output line, reset signal line, strobe signal line, and red/write control signal line which correspond to 3, 11, 12, 14, 5, 4 and 6 in FIG. 1.
  • the data input/output line 44 is connected to an external data bus line 51 through a bus interface circuit 50.
  • the flag output line 45 is connected to an external flag line 53 through a flag interface circuit 52.
  • the data buffer devices 40-43 are blocked in one, and a block selection input line 54 which indicates the selection/non-selection of the block and an address input line 55 which designates a data buffer device in the block are converted by a decode circuit 56 to chip selection input lines of the data buffer devices 40-43.
  • the chip selection output lines from the data buffer devices 40-43 are supplied to a logic circuit 57, which outputs a logical OR of the signals on the chip selection output signal lines to the bus interface circuit 50, which connects the data bus line 51 and the data input/output line 44 in the block in accordance with the signal from the logic circuit 57.
  • the flag interface circuit 52 connects the flag output line 45 to the external flag line 53 in accordance with the signal on the block selection input line 54 assuming that a portion enclosed by broken lines in FIG. 4 is an external interface circuit 56, the data buffer array device shown in FIG. 4 comprises the data buffer devices 40-43 shown in FIG. 1 and the external interface circuit 56.
  • the bus interface circuit 50 is controlled by the logical OR of the chip selection output signals of the data buffer devices 40-43 and the flag interface circuit 52 is controlled by the block selection input line.
  • the data transfer to the data buffer device selected by the block selection input line 54 and the address input line 55 is held by the selected data buffer device until the end of the eighth word data, and the bus interface circuit 50 effects the input/output of the data until the end of the eighth word data by the hold signal.
  • the signals on the block selection input line 54 and the address input line 55 may be changed after the end of the first word data to designate another data buffer device in the same array or other array, and may output a signal on the flag output line 11 of the designated data buffer device.
  • the equipment which accesses to the data buffer array device can detect the flag relating to the next transfer of the data buffer device whose data is being transferred, by holding the signal on the block selection input line 54 and the signal on the address input line 55, and the flag of the data buffer device which is to transfer the data next, by activating the block selection input line of the data buffer array device or changing the address input line 55 of the same data buffer array device.
  • FIG. 4 shows a configuration of a data buffer array device which has a 4 ⁇ 4 two-dimensional array in the X and Y directions.
  • Numerals 60-63 denote an X-direction data bus line (hereinafter the X-direction is simply referred to as X, and Y-direction is simply referred to as Y), an X external flag line, an X block selection input line and an X address input line, and numeral 64 denotes an X strobe signal line. Those are connected to an X external interface circuit 65.
  • the substance of the X external interface circuit is similar to the external interface circuit 56 of FIG. 4. Similarly, a Y data bus line 66, a Y external flag line 67, a Y block selection input line 68, a Y address input line 69 and a Y strobe signal line 70 are connected to a Y external interface circuit 71.
  • the Y external interface circuit is also similar to the external interface circuit 56 of FIG. 4.
  • the sixteen two-dimensionally arrayed data buffer devices are identical to the data buffer devices 40-43 of FIG. 4 and a selector 13 is connected to each of those data buffer devices.
  • a plurality of signal lines similar to those shown in FIG. 4 are connected from the X external interface circuit 65 and the Y external interface circuit 71 to the selector 73, which switches the corresponding signal lines from those two external interface circuits in order to access the data buffer device.
  • the equipment which accesses to the data buffer array device can detect the flag of the data buffer device which relates to the next data transfer while it effects the input/output of the data.
  • a two-dimensional data base array of any spread can be constructed. Such a construction is useful for a cross-bar type network and it has a wide range of applications.
  • the equipment which accesses to the data buffer array device can detect the flag of the data buffer device in the same data buffer array device relating to the next data transfer or the flag of the data buffer device in other data buffer array device, while it effects the input/output of the data for the designated data base device.
  • the data transfer and the flag detection can be pipelined and high speed data transfer is attained
  • the essence of the present invention resides in storing the chip selection signal in the data buffer device at a predetermined timing in the course of data transfer, transferring the subsequent data based on the stored signal, and controlling the output of the flag to be detected prior to the data transfer, by the chip selection signal and informing it to the external.
  • the data transfer and the detection of the flag status can be independently effected and the data can be transferred without break and with a high efficiency.
  • the chip selection input signal of the data buffer device is latched prior to the end of the input/output of N words, where N (N>2) is a minimum number of words transferred as a unit on the bus and it is held until the end of the input/output of the N-word data, and the output of the flag of the FIFO memory is controlled by the chip selection input signal present before latching so that the status of other data buffer device can be checked while the chip selection signal is held and the input/output of the data is effected.
  • N N>2
  • the output of the flag of the FIFO memory is controlled by the chip selection input signal present before latching so that the status of other data buffer device can be checked while the chip selection signal is held and the input/output of the data is effected.
  • the input/output of the data of the bus interface circuits is controlled by the logical OR of the chip selection signals from the data buffer devices, present after latching so that a hierarchical data buffer array device is constructed without sacrificing the advantages of the present invention.
  • This is advantageous in constructing a large scale cross-bar type network and can be equally used in networks through buffers.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Bus Control (AREA)
  • Memory System (AREA)
US07/337,399 1988-04-18 1989-04-13 Data buffer device using first-in first-out memory and data buffer array device Expired - Lifetime US5056005A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP63-94827 1988-04-18
JP9482788 1988-04-18
JP63-118520 1988-05-16
JP11852088 1988-05-16

Publications (1)

Publication Number Publication Date
US5056005A true US5056005A (en) 1991-10-08

Family

ID=26436070

Family Applications (1)

Application Number Title Priority Date Filing Date
US07/337,399 Expired - Lifetime US5056005A (en) 1988-04-18 1989-04-13 Data buffer device using first-in first-out memory and data buffer array device

Country Status (2)

Country Link
US (1) US5056005A (ja)
JP (1) JP2841456B2 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5177573A (en) * 1990-03-09 1993-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device
US5459413A (en) * 1994-02-04 1995-10-17 Goldstar Electron Co., Ltd. Bus interfacing circuit for a FIFO memory
US5799186A (en) * 1990-12-20 1998-08-25 Eastman Kodak Company Method and apparatus for programming a peripheral processor with a serial output memory device
US20050085357A1 (en) * 2001-12-20 2005-04-21 Ken Endelman Reformer exercise apparatus having a non-rotating spring anchor bar
US20080256267A1 (en) * 2005-04-22 2008-10-16 Renesas Technology Corp. High-speed data readable information processing device

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4110842A (en) * 1976-11-15 1978-08-29 Advanced Micro Devices, Inc. Random access memory with memory status for improved access and cycle times
US4374428A (en) * 1979-11-05 1983-02-15 Rca Corporation Expandable FIFO system
US4433394A (en) * 1980-09-19 1984-02-21 Hitachi, Ltd. First-in first-out storage and processing unit making use thereof
US4486854A (en) * 1981-10-15 1984-12-04 Codex Corporation First-in, first-out memory system
US4494190A (en) * 1982-05-12 1985-01-15 Honeywell Information Systems Inc. FIFO buffer to cache memory
US4571671A (en) * 1983-05-13 1986-02-18 International Business Machines Corporation Data processor having multiple-buffer adapter between a system channel and an input/output bus
US4692859A (en) * 1983-05-16 1987-09-08 Rca Corporation Multiple byte serial data transfer protocol
US4829475A (en) * 1985-06-20 1989-05-09 Texas Instruments Incorporated Method and apparatus for simultaneous address increment and memory write operations
US4833655A (en) * 1985-06-28 1989-05-23 Wang Laboratories, Inc. FIFO memory with decreased fall-through delay
US4839866A (en) * 1987-05-29 1989-06-13 Texas Instruments Incorporated Cascadable first-in, first-out memory
US4852065A (en) * 1984-06-02 1989-07-25 Eric Baddiley Data reorganization apparatus
US4864543A (en) * 1987-04-30 1989-09-05 Texas Instruments Incorporated First-in, first-out memory with counter address pointers for generating multiple memory status flags
US4891788A (en) * 1988-05-09 1990-01-02 Kreifels Gerard A FIFO with almost full/almost empty flag

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS638852A (ja) * 1986-06-30 1988-01-14 Toshiba Corp デ−タ転送回路

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4110842A (en) * 1976-11-15 1978-08-29 Advanced Micro Devices, Inc. Random access memory with memory status for improved access and cycle times
US4374428A (en) * 1979-11-05 1983-02-15 Rca Corporation Expandable FIFO system
US4433394A (en) * 1980-09-19 1984-02-21 Hitachi, Ltd. First-in first-out storage and processing unit making use thereof
US4486854A (en) * 1981-10-15 1984-12-04 Codex Corporation First-in, first-out memory system
US4494190A (en) * 1982-05-12 1985-01-15 Honeywell Information Systems Inc. FIFO buffer to cache memory
US4571671A (en) * 1983-05-13 1986-02-18 International Business Machines Corporation Data processor having multiple-buffer adapter between a system channel and an input/output bus
US4692859A (en) * 1983-05-16 1987-09-08 Rca Corporation Multiple byte serial data transfer protocol
US4852065A (en) * 1984-06-02 1989-07-25 Eric Baddiley Data reorganization apparatus
US4829475A (en) * 1985-06-20 1989-05-09 Texas Instruments Incorporated Method and apparatus for simultaneous address increment and memory write operations
US4833655A (en) * 1985-06-28 1989-05-23 Wang Laboratories, Inc. FIFO memory with decreased fall-through delay
US4864543A (en) * 1987-04-30 1989-09-05 Texas Instruments Incorporated First-in, first-out memory with counter address pointers for generating multiple memory status flags
US4839866A (en) * 1987-05-29 1989-06-13 Texas Instruments Incorporated Cascadable first-in, first-out memory
US4891788A (en) * 1988-05-09 1990-01-02 Kreifels Gerard A FIFO with almost full/almost empty flag

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5177573A (en) * 1990-03-09 1993-01-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device
US5799186A (en) * 1990-12-20 1998-08-25 Eastman Kodak Company Method and apparatus for programming a peripheral processor with a serial output memory device
US5459413A (en) * 1994-02-04 1995-10-17 Goldstar Electron Co., Ltd. Bus interfacing circuit for a FIFO memory
US20050085357A1 (en) * 2001-12-20 2005-04-21 Ken Endelman Reformer exercise apparatus having a non-rotating spring anchor bar
US20080256267A1 (en) * 2005-04-22 2008-10-16 Renesas Technology Corp. High-speed data readable information processing device
US7613863B2 (en) * 2005-04-22 2009-11-03 Renesas Technology Corporation High-speed data readable information processing device

Also Published As

Publication number Publication date
JP2841456B2 (ja) 1998-12-24
JPH0256048A (ja) 1990-02-26

Similar Documents

Publication Publication Date Title
US4809161A (en) Data storage device
US5079693A (en) Bidirectional FIFO buffer having reread and rewrite means
US4825411A (en) Dual-port memory with asynchronous control of serial data memory transfer
US4052699A (en) High speed real time image transformation
KR0176422B1 (ko) 페이지-인 버스트-아웃 피포 시스템
US4835675A (en) Memory unit for data tracing
US5497478A (en) Memory access system and method modifying a memory interleaving scheme so that data can be read in any sequence without inserting wait cycles
EP0401340B1 (en) Method and apparatus for handling high speed data
US4412286A (en) Tightly coupled multiple instruction multiple data computer system
US6026451A (en) System for controlling a dispatch of requested data packets by generating size signals for buffer space availability and preventing a dispatch prior to a data request granted signal asserted
JPH03238686A (ja) 状態フラグ発生方法および装置
US4604682A (en) Buffer system for interfacing an intermittently accessing data processor to an independently clocked communications system
US4879561A (en) Filter system for radar applications
EP0540665A1 (en) Routing independent circuit components
EP0395210A2 (en) Threshold detection circuits for digital storage buffers
US3755788A (en) Data recirculator
EP0484652B1 (en) First-in-first-out buffer
US4803654A (en) Circular first-in, first out buffer system for generating input and output addresses for read/write memory independently
US5898895A (en) System and method for controlling data transmission rates between circuits in different clock domains via selectable acknowledge signal timing
US5056005A (en) Data buffer device using first-in first-out memory and data buffer array device
US5987586A (en) Method and apparatus for asynchronous device communication
JP3076205B2 (ja) 先入れ先出しバッファ装置
CA2000145C (en) Data transfer controller
US5444722A (en) Memory module with address error detection
JPH01103341A (ja) アドレス検出回路

Legal Events

Date Code Title Description
AS Assignment

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:KANEKO, KATSUYUKI;GOKITA, SATOSHI;ZAIKI, KOJI;REEL/FRAME:005115/0851

Effective date: 19890508

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12