US4592010A - Memory-programmable controller - Google Patents

Memory-programmable controller Download PDF

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Publication number
US4592010A
US4592010A US06/568,107 US56810784A US4592010A US 4592010 A US4592010 A US 4592010A US 56810784 A US56810784 A US 56810784A US 4592010 A US4592010 A US 4592010A
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command
word
memory
processor
bus
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US06/568,107
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Dieter Wollscheid
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/052—Linking several PLC's
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1182—I-O isolation, optical
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/13—Plc programming
    • G05B2219/13173—Selection out of all possible programs with switch
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/14—Plc safety
    • G05B2219/14089—Display of control states on cards, by leds
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/14—Plc safety
    • G05B2219/14119—Inhibit remote control
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15001—Local remote switch control
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15005—Set switches defining control function
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15006—Set configuration from master control station
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15007—On reinsertion board, power up, program setting, configuration automatically set
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15018—Communication, serial data transmission, modem
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15052—Communication processor, link interface
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15068—SBC single board computer, UCM universal control module
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15078—Modules, construction of system
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/15—Plc structure of the system
    • G05B2219/15127—Bit and word, byte oriented instructions, boolean and arithmetic operations

Definitions

  • Memory-Programmable Controller filed as Ser. No. 568,115 on Jan. 4, 1984 in the names of Dieter Wollscheid, Peter Ninnemann, Siegfried Stoll and Waldemar Wenzel, and claiming priority of German Application No. P33 02 909.1 filed Jan. 28, 1983.
  • the present invention relates to the field of memory-programmable controllers of the type having cyclically traversed user control programs for controlling peripheral processes.
  • the present invention relates to memory-programmable controllers of the multiprocessor type having a word processor for processing operating system and word commands, a bit processor for processing binary interlinking commands, a user program memory in which the control program is stored, an operating system memory in which an operating system program is stored and a data memory wherein binary process images of the peripheral process under control are stored.
  • Memory-programmable controllers are described in detail, for instance, in Siemens Zeitschrift “Energietechnik” 1979, no. 2, pages 43 to 47 no. 4, pages 136 to 139 in European Patent No. 10170 and in U.S. Pat. Nos. 3,921,146 and 3,942,158.
  • a memory-programmable controller of the type mentioned above should preferably be able to carry out the logical interlinking of data 1-bit wide as well as more complex functions with data one word wide, such as arithmetic functions, data transfer, timing etc.
  • An essential criterion for a memory-programmable controller is that it process word and bit commands rapidly.
  • the bit processor must be able to process commands rapidly.
  • a memory programmable controller of the type having a cyclically traversed user control program for controlling a peripheral process including a word processor for processing operating system and word commands, a word processor bus coupled to the word processor, a bit processor for processing binary interlinking commands, a user program memory wherein the control program including the word commands and interlinking commands is stored, an operating system memory wherein an operating system program including the operating system commands is stored and a data memory wherein binary process images of the process are stored, the improvement comprising the bit processor including:
  • second bus means for accessing data from the data memory when the first command is being executed
  • the loading of the command and the execution of the preceding command are carried out in parallel. Due to the low complexity of the commands carried out by the bit processor and the short times for command decoding and internal command execution in connection therewith, the memory access time is the primary factor in determining the command throughput rate. For this reason, the user program memory and the data memory of the bit processor are coupled via separate bus systems.
  • the bit processor recognizes a word command, it goes into a waiting state and furnishes information characterizing the word command to the word processor.
  • the word processor controls the bit processor, and specifically in the manner of a programmable peripheral module which can be started and stopped and the command address register of which can be manipulated by the word processor. Since access to control and status registers of the bit processor must be possible even when the bit processor is loading and executing commands a third bus connection, namely, to the word processor bus, is required for the bit processor.
  • FIG. 1 is a block diagram of one embodiment of the memory-programmable controller according to the invention.
  • FIG. 2 is a more detailed block diagram of one embodiment of the bit processor of the controller of FIG. 1.
  • a user control program resides in a user program memory 5 which may be designed as a read/write memory or as a read-only memory (ROM).
  • This memory can be organized, for instance, as 2 16 ⁇ 8 bits and can be addressed via sixteen address lines and may have eight data lines as well as the required control lines for controlling reading and writing, etc.
  • the data to be processed i.e., the process images, reside in a data memory 6 which is designed as a read/write memory and is organized for instance, as 2 9 ⁇ 8 bits.
  • the controller includes a word processor 2 and a bit processor 3.
  • the word processor as a rule a standard microprocessor, has the following tasks:
  • the word processor 2 is coupled to a peripheral bus 21, to which the input and output modules 1 coupled to the controlled process are connected. Furthermore, an internal system bus 22 (word processor bus), couples the operating system memory 4 and, via data switches 8, the user program memory 5 and the data memory 6 wherein the process images are stored.
  • the bit processor 3 is also connected to the bus 22. Bit processor 3 also accesses the user program memory 5 and data memory 6 but only via dedicated buses 31 and 32 and the respective data switches 8. Data communication with the peripheral process is always via the word processor 2 which stores at the control program cycle limits the status of all input information from the process in the internal data memory 6 and transmits the output signals resulting from the logic stored in the data memory 6 to the peripheral process at the end of the cycle.
  • control program i.e., the instructions for executing the bit and word operations, are encoded in a special programming language and are stored in the user program memory 5. These instructions are executed by the bit processor 3 directly and by the word processor 2 in certain routines.
  • routines as well as other operating system routines are permanently stored in the operating system memory 4 of the word processor 2 in the language of the microprocessor used for the word processor.
  • the commands in the user program memory are as a rule executed by the bit processor itself. However, some of the commands i.e., word commands, must be transferred to the word processor for execution.
  • a binary logic command may comprise, for instance, three words of 8 bits each.
  • the bit processor 3 includes a command address register which points to a word in the user memory. To execute a command, three successive words are loaded into the bit processor. If a complete command is in the bit processor, it is either executed directly, access being made to the data memory 6 for the data on which the commands operate, or the command is transferred to the word processor 2.
  • bit processor The structure of the bit processor is shown in FIG. 2. As is evident from FIG. 2, the commands are executed internally by several means which operate in parallel.
  • the command-fetching means 11 continuously loads user program memory words according to the control commands of the command controller 15, from user program memory 5 via one data switch 8 and bus 31 into the command memory and assembly means 12. While the means 11 loads commands, the previous command is executed in the command execution means 13 independently of the loading of the new command. Means 13 accesses the data memory 6 for the data on which the command operates via the bus 32 and the data processing means 14.
  • means 12 assembles a command word from several words from the program memory 5. If such a command is assembled, it is immediately transferred to the command execution means 13. At the same time, the cycle controller 16 is triggered. The command execution means 13 then processes the command, wherein it accesses the data in the data memory 6 via the data processing means 14.
  • the data are stored in the data memory in words of 8 bits each.
  • the width corresponds as a rule to the data bus width of the word processor. It should be chosen as large as possible so as to make the transfer of data from and to the peripheral process fast enough, since, a relatively slow transmission channel is typically used for such transfer.
  • a predecoder 17 is associated with the command assembly means 12.
  • the predecoder determines whether a binary logic or interlinking command is read from memory 5. If a binary logic command is not present, but rather a word command is read, the bit processor is shut down via the start-stop controller 18.
  • the word command is not transferred directly to the word processor, but serves as the entry address for the program routine in the operating system memory 4 associated with a given word processor operation.
  • a memory controller 25 addressed by the command memory and assembly means 12 corresponding to the present word command is provided, which generates from the code of the word operation the address for a given storage cell of the associated memory 23.
  • Memory 23, which may also be located externally of the bit processor 3, is continuously interrogated by the word processor via bus 22.
  • the word processor 2 finds at the addressed storage cell of the memory 23 the entry address of the program routine in memory 4 required for the execution of the word command. It is achieved in this manner that, with a fixed command code of the word operation, the entry addresses into the associated program routines can be kept variable.
  • Memory 23 can optionally be dispensed with.
  • memory 23 is replaced by a data block within the operating system memory 4, in which the entry address is determined by means of a table lookup procedure.
  • the entry address can also be determined directly from the output data of the memory controller 25 by arithmetical and logical operations.
  • the bit processor is further coupled to the word processor bus 22 via interface 21.
  • the bit processor processes a program independently and is treated by the word processor like any other peripheral device.
  • the internal state of the bit processor can, for instance, be controlled by a control input 19, for instance, start-stop, and the internal state of the bit processor can be interrogated via a status input 20.
  • some internal registers of the bit processor such as the command address register and other binary registers, can be controlled by the word processor via interface 21, as indicated by arrow 24.

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Physics & Mathematics (AREA)
  • Programmable Controllers (AREA)
  • Circuits Of Receivers In General (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Debugging And Monitoring (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Steering Control In Accordance With Driving Conditions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
  • Devices For Executing Special Programs (AREA)
  • Electrotherapy Devices (AREA)
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US06/568,107 1983-07-01 1984-01-04 Memory-programmable controller Expired - Fee Related US4592010A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3323824 1983-07-01
DE19833323824 DE3323824A1 (de) 1983-07-01 1983-07-01 Speicherprogrammierbare steuerung

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US (1) US4592010A (de)
EP (1) EP0130269B1 (de)
JP (1) JPS6015708A (de)
AT (1) ATE34629T1 (de)
DE (2) DE3323824A1 (de)
ES (1) ES8500473A1 (de)
NO (1) NO167114B (de)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4851990A (en) * 1987-02-09 1989-07-25 Advanced Micro Devices, Inc. High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure
US5010513A (en) * 1984-02-24 1991-04-23 Canon Kabushiki Kaisha Data processing apparatus
US5202973A (en) * 1990-06-29 1993-04-13 Digital Equipment Corporation Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus
US5504930A (en) * 1991-10-24 1996-04-02 Hitachi, Ltd. Programmable controller and sequence control method
US5553297A (en) * 1989-04-24 1996-09-03 Yokogawa Electric Corporation Industrial control apparatus
US5586275A (en) * 1989-05-04 1996-12-17 Texas Instruments Incorporated Devices and systems with parallel logic unit operable on data memory locations, and methods
US5941966A (en) * 1997-05-05 1999-08-24 International Business Machines Corporation Method and apparatus using a plural level processor for controlling a data bus
FR2821456A1 (fr) * 2001-02-28 2002-08-30 St Microelectronics Sa Microprocesseur a architecture harvard ayant un espace adreassable lineaire
KR101008806B1 (ko) 2001-05-10 2011-01-14 엔엑스피 비 브이 데이터 처리 시스템 및 그 시스템을 형성하는 용기와, 휴대용 전화 및 액세스 분배 방법

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01255901A (ja) * 1988-04-06 1989-10-12 Fanuc Ltd プログラマブル・コントローラ
JPH0429204U (de) * 1990-07-02 1992-03-09
US5295059A (en) † 1992-09-09 1994-03-15 Allen-Bradley Company, Inc. Programmable controller with ladder diagram macro instructions
ES2118170T3 (es) * 1993-10-11 1998-09-16 Siemens Ag Modulo de procesamiento para un sistema de automatizacion modular.

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US3810118A (en) * 1971-04-27 1974-05-07 Allen Bradley Co Programmable matrix controller
US3921146A (en) * 1973-01-05 1975-11-18 Gen Electric Programmable data processor and controller system
US3942158A (en) * 1974-05-24 1976-03-02 Allen-Bradley Company Programmable logic controller
US4165534A (en) * 1977-04-25 1979-08-21 Allen-Bradley Company Digital control system with Boolean processor
US4175284A (en) * 1971-09-08 1979-11-20 Texas Instruments Incorporated Multi-mode process control computer with bit processing
US4180862A (en) * 1976-07-01 1979-12-25 Gulf & Western Industries, Inc. Programmable controller using microprocessor
US4245307A (en) * 1979-09-14 1981-01-13 Formation, Inc. Controller for data processing system
US4282584A (en) * 1979-05-30 1981-08-04 Allen-Bradley Company Mini-programmable controller
US4293924A (en) * 1979-05-30 1981-10-06 Allen-Bradley Company Programmable controller with high density intelligent I/O interface
US4455621A (en) * 1981-03-09 1984-06-19 Allen-Bradley Company Programmable controller with multiple functions
US4484303A (en) * 1979-06-19 1984-11-20 Gould Inc. Programmable controller
US4517657A (en) * 1981-08-04 1985-05-14 Dr. Johannes Heidenhain Gmbh Integrated bit processor/word processor control system

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US4107773A (en) * 1974-05-13 1978-08-15 Texas Instruments Incorporated Advanced array transform processor with fixed/floating point formats
CA1103364A (en) * 1977-04-25 1981-06-16 Raymond A. Grudowski Programmable controller with integral microprocessor
JPS54114687A (en) * 1978-02-27 1979-09-06 Toyoda Mach Works Ltd Sequence controller
JPS5815203B2 (ja) * 1978-07-14 1983-03-24 住友金属工業株式会社 鋼板の冷却方法およびその装置
DE3101270C2 (de) * 1981-01-16 1985-07-25 Christian Dipl.-Ing. 8000 München Nitschke Rechneranordnung zur Wortverarbeitung mit einer Einrichtung zur Funktionserweiterung

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3810118A (en) * 1971-04-27 1974-05-07 Allen Bradley Co Programmable matrix controller
US4175284A (en) * 1971-09-08 1979-11-20 Texas Instruments Incorporated Multi-mode process control computer with bit processing
US3921146A (en) * 1973-01-05 1975-11-18 Gen Electric Programmable data processor and controller system
US3942158A (en) * 1974-05-24 1976-03-02 Allen-Bradley Company Programmable logic controller
US4180862A (en) * 1976-07-01 1979-12-25 Gulf & Western Industries, Inc. Programmable controller using microprocessor
US4165534A (en) * 1977-04-25 1979-08-21 Allen-Bradley Company Digital control system with Boolean processor
US4282584A (en) * 1979-05-30 1981-08-04 Allen-Bradley Company Mini-programmable controller
US4293924A (en) * 1979-05-30 1981-10-06 Allen-Bradley Company Programmable controller with high density intelligent I/O interface
US4484303A (en) * 1979-06-19 1984-11-20 Gould Inc. Programmable controller
US4245307A (en) * 1979-09-14 1981-01-13 Formation, Inc. Controller for data processing system
US4455621A (en) * 1981-03-09 1984-06-19 Allen-Bradley Company Programmable controller with multiple functions
US4517657A (en) * 1981-08-04 1985-05-14 Dr. Johannes Heidenhain Gmbh Integrated bit processor/word processor control system

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5010513A (en) * 1984-02-24 1991-04-23 Canon Kabushiki Kaisha Data processing apparatus
US4851990A (en) * 1987-02-09 1989-07-25 Advanced Micro Devices, Inc. High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure
US5553297A (en) * 1989-04-24 1996-09-03 Yokogawa Electric Corporation Industrial control apparatus
US5586275A (en) * 1989-05-04 1996-12-17 Texas Instruments Incorporated Devices and systems with parallel logic unit operable on data memory locations, and methods
US5202973A (en) * 1990-06-29 1993-04-13 Digital Equipment Corporation Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus
US5504930A (en) * 1991-10-24 1996-04-02 Hitachi, Ltd. Programmable controller and sequence control method
US5941966A (en) * 1997-05-05 1999-08-24 International Business Machines Corporation Method and apparatus using a plural level processor for controlling a data bus
FR2821456A1 (fr) * 2001-02-28 2002-08-30 St Microelectronics Sa Microprocesseur a architecture harvard ayant un espace adreassable lineaire
WO2002069163A1 (fr) * 2001-02-28 2002-09-06 Stmicroelectronics Sa Microprocesseur a architecture harvard ayant un espace adressable lineaire
US20040073762A1 (en) * 2001-02-28 2004-04-15 Stmicroelectronics Sa Harvard architecture microprocessor having a linear addressable space
US7120760B2 (en) 2001-02-28 2006-10-10 Stmicroelectronics Sa Harvard architecture microprocessor having a linear addressable space
KR101008806B1 (ko) 2001-05-10 2011-01-14 엔엑스피 비 브이 데이터 처리 시스템 및 그 시스템을 형성하는 용기와, 휴대용 전화 및 액세스 분배 방법

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ES529244A0 (es) 1984-10-01
ES8500473A1 (es) 1984-10-01
JPS6015708A (ja) 1985-01-26
NO834728L (no) 1985-01-02
DE3323824A1 (de) 1985-01-03
NO167114B (no) 1991-06-24
ATE34629T1 (de) 1988-06-15
EP0130269A3 (en) 1985-07-31
EP0130269A2 (de) 1985-01-09
EP0130269B1 (de) 1988-05-25
DE3471534D1 (en) 1988-06-30

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