US4574307A - Line synchronizing circuit for a picture display device - Google Patents

Line synchronizing circuit for a picture display device Download PDF

Info

Publication number
US4574307A
US4574307A US06/529,893 US52989383A US4574307A US 4574307 A US4574307 A US 4574307A US 52989383 A US52989383 A US 52989383A US 4574307 A US4574307 A US 4574307A
Authority
US
United States
Prior art keywords
line synchronizing
signal
circuit
phase discriminator
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US06/529,893
Other languages
English (en)
Inventor
Antonius H. H. J. Nillesen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Philips Corp
Original Assignee
US Philips Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by US Philips Corp filed Critical US Philips Corp
Assigned to U.S. PHILIPS CORPORATION reassignment U.S. PHILIPS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: NILLESEN, ANTONIUS H. H. J.
Application granted granted Critical
Publication of US4574307A publication Critical patent/US4574307A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/06—Generation of synchronising signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
    • H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N30/00—Investigating or analysing materials by separation into components using adsorption, absorption or similar phenomena or using ion-exchange, e.g. chromatography or field flow fractionation
    • G01N30/02—Column chromatography
    • G01N30/04—Preparation or injection of sample to be analysed
    • G01N30/06—Preparation
    • G01N30/12—Preparation by evaporation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N30/00—Investigating or analysing materials by separation into components using adsorption, absorption or similar phenomena or using ion-exchange, e.g. chromatography or field flow fractionation
    • G01N30/02—Column chromatography
    • G01N30/26—Conditioning of the fluid carrier; Flow patterns
    • G01N30/28—Control of physical parameters of the fluid carrier
    • G01N30/30—Control of physical parameters of the fluid carrier of temperature

Definitions

  • the invention relates to a line synchronizing circuit for a picture display device, comprising a control loop for controlling the frequency and/or the phase of a line oscillator, having means for applying an incoming pulse-shaped line synchronizing signal and a reference signal generated by the oscillator to a phase discriminator for determining the phase difference between the signals applied thereto and having a loop filter for smoothing the phase discriminator output signal and for applying the smoothed control signal obtained to the oscillator for the control thereof, said control loop being such that during operation, in the target state thereof, the centre instant of an edge of the reference signal substantially coincides with the center instant between a leading edge and the subsequent trailing edge of a line synchronizing pulse, the line synchronizing circuit also comprising a coincidence detector for detecting a phase difference between an incoming line synchronizing pulse and an oscillator pulse which difference is less than a predetermined value and for changing over the mode of operation of the control loop.
  • Line synchronizing circuits which, as the circuit mentioned above, control at the center instant of the line synchronizing pulses, have the disadvantage that a phase error occurs at the commencement of the field period, which error is caused by the fact that the duration of the synchronizing pulses occurring during the field blanking period is, different from the duration of the line synchronizing pulses occurring during the field trace period.
  • the content of the phase discriminator output signal differs from its target value, which results in an error in the control which has not yet been corrected at the end of the field blanking period.
  • vertical lines are displayed as curved lines at the top of the picture display screen. This error can be corrected, several methods to do so are known. It is, for example, possible to render the control loop inoperative during the field blanking period. This has however the disadvantage that pull-in is delayed.
  • the invention has for its object to provide a circuit of the above-mentioned type, in which the error is prevented while a rapid pull-in of the control loop is ensured.
  • the line synchronizing circuit is characterized in that the control loop is arranged such that in its target state, after the change-over action by means of the coincidence detector, the center instant of the leading edge of an incoming line synchronizing pulse substantially coincides with the center instant between the edge of the reference signal and its first preceding edge.
  • the invention is based on the recognition that the phase error produced during the field blanking interval can be prevented from occurring if the control is not effected to the center instant but to the leading edge of the line synchronizing pulse, as in that case, the duration of the pulse is of no importance.
  • the leading edge of the line synchronizing pulse contains the information required for the control loop. Measures must indeed be taken to ensure that the trailing edge of this pulse does not influence the control, which means that the reference pulse should not be too long and consequently that the period of time in which the comparatively short pulses coincide during the pulling-in procedure is very short compared to the periods of the signals applied to the phase discriminator.
  • the invention proposes a different measure.
  • a control is effected in known manner to the center of the line synchronizing pulse, causing pull-in to be effected rapidly. Thereafter the circuit is changed-over to a control on the leading edge of the line synchronizing pulse, which control may be considered as a fine control, it not being possible that the fact that the control loop now has a poor pull-in behavior has a negative effect on the pull-in state since this state has already occurred.
  • the line synchronizing circuit according to the invention is characterized in that after change-over by means of the coincidence detector, the duration of the reference pulse formed by the edges is approximately equal to the duration of the line synchronizing pulse. Because of this measure an, otherwise small, phase shift does not occur.
  • the line synchronizing circuit in accordance with the invention is characterized in that the phase discriminator is in the form of a controllable switch which prior to change-over by means of the coincidence detector is operated by the line synchronizing signal for conveying the reference signal to the loop filter and which after the said change-over action is operated by the reference pulse for conveying the line synchronizing signal to the loop filter.
  • FIG. 1 shows waveforms produced in the circuit in accordance with the invention, prior to the change-over operation
  • FIG. 2 shows waveforms produced therein after the change-over operation
  • FIG. 3 shows a first embodiment of the circuit in accordance with the invention
  • FIG. 4 shows a second embodiment of the circuit in accordance with the invention.
  • FIG. 5 shows a third embodiment of the circuit in accordance with the invention.
  • FIG. 1a a line synchronizing pulse is shown which is applied to a phase discriminator in a phase control loop.
  • the signal level has a low value, denoted by 0, and during the remaining portion it assumes a high value, denoted by +1.
  • the phase discriminator is also supplied with a reference signal shown in FIG. 1b and coming from a line oscillator, which signal assumes a value -1 or a value +1.
  • the phase discriminator multiples these two signals by each other, FIG. 1c shows the result.
  • the signal shown in FIG. 1c is integrated by a low-pass filter to provide the control voltage (FIG. 1d) for the oscillator.
  • the control loop is arranged such that in the target state thereof, an edge of the reference signal shown in FIG. 1b is produced at the center instant of the pulse shown in FIG. 1a.
  • the waveforms shown in FIGS. 1a to d, inclusive, show the case in which the frequency of the oscillator is below the target value thereof.
  • a transition from +1 to -1 in the reference signal then occurs after the center instant.
  • the target position of this transition is indicated by means of a broken line.
  • the phase discriminator output signal has the value 0 when the pulse shown in FIG. 1a does not occur and when this pulse occurs, the output signal has first the value +1 and thereafter the value -1, the transition produced coinciding with the transition shown in FIG. 1b. From FIG.
  • the generated control voltage has a positive value V compared with its nominal value.
  • the frequency of the oscillator is increased, as a result of which the edge in FIG. 1b is advanced.
  • the deviation of the control voltage relative to the nominal value thereof becomes zero, which is the target state in which the oscillator is not readjusted and has the same frequency as the line synchronizing pulses and a fixed phase relationship therewith.
  • the waveforms shown in FIGS. 1c and d are symmetrical relative to the center instant of the pulse shown in FIG. 1a.
  • FIG. 1b does not show the position of the rising edge of the reference signal, it will be obvious that the pulse this edge forms with the falling edge must not be narrower than the synchronizing pulse. Otherwise the control voltage might depend on the position of the rising edge, which would introduce an ambiguity in the control.
  • the above-described operation of a control loop controlling to the center instant of the line synchronizing pulse and the means therefore are of a known type.
  • the line synchronizing circuit of which the control loop forms part also comprises a coincidence detector which detects in known manner that coincidence has occurred once or a predetermined number of times, i.e. the, at least partly, simultaneous occurrence of an incoming line synchronizing pulse and a short gate pulse generated by the oscillator.
  • the coincidence detector may alternatively be in the form of an auxiliary phase discriminator for determining that the difference between the position of the falling edge of the signal shown in FIG. 1b and the target position thereof is less than a predetermined value.
  • the coincidence detector By means of the coincidence detector, a number of elements of the circuit can be changed-over when there is coincidence, that is to say, in the pulled-in state of the control loop. In this way, it is accomplished that the control loop has a fast response to phase changes in the non-synchronized state and a slow and noise insensitive response in the synchronized state.
  • the synchronizing circuit is switched over in such a way by the coincidence detector, after the final state of the control loop of FIG. 1 has been obtained, that the variation shown in FIG. 2 occurs.
  • FIG. 2a also shows the line synchronizing pulse, its signal level varying between the values -1 and +1.
  • FIG. 2b shows the reference signal having a level of either 0, or +1.
  • FIG. 2 shows again the case in which the reference signal occurs too late relative to the target position thereof.
  • the period of time between the occurrence of the leading edge of the reference pulse and the occurrence of the leading edge of the synchronizing pulse is consequently shorter than the period of time between the occurrence of the last-mentioned leading edge and the occurrence of the trailing edge of the reference pulse.
  • FIG. 2c shows that the result of the multiplication of the signals shown in FIGS. 2a and b has the value +1 for a longer period of time, more specifically after the transition which corresponds to the leading edge of the synchronizing pulse, than the value -1 it has prior to this transition.
  • the resultant control voltage is posive relative to its nominal value.
  • the frequency of the oscillator is increased, as a result of which the pulse of FIG. 2b is advanced.
  • the control voltage assumes its nominal value, the frequency of the oscillator not being readjusted anymore, at the instant that the leading edge of the synchronizing pulse coincides with the center of the reference pulse. In this situation the waveforms of FIGS.
  • the duration of the reference pulse should not exceed the duration of the line synchronizing pulse. Otherwise, the trailing edge of the synchronizing pulse might occur before the end of the reference pulse, so that the generated control voltage might also depend on the position of the trailing edge.
  • the reference pulse must not be too short in view of the influence of its duration on the loop gain. It should be noted that when the target position of the control loop of FIG. 1 is reached, this position will generally be treated by the control loop of FIG. 2 as an error which needs correction. This results in the above mentioned, slight shift for the oscillator and for the signals derived therefrom.
  • control loop with reference to FIGS. 1 and 2 is always based on the ideal case of an infinite loop gain. In actual practice there will, however, always be a small phase error relative to the target value, which results in a control voltage which is not equal to the nominal value. Because of the short duration of the pulses applied to the phase discriminator compared with the line period, the pull-in behavior of the control loop of FIG. 2 is poor. On account of the fact that this loop must process small phase variations after coincidence has been detected, that is to say after the control loop shown in FIG. 1 has already been pulled in, this poor behavior is not objectionable. If so large a deviation occurs that the loop is not capable of pulling in, then the coincidence detector effects a switch to the control loop of FIG.
  • control loop of FIG. 1 must indeed have a good pull-in behavior. This is the case if the duration of the reference pulse in FIG. 1 b is not short relative to the line period.
  • the optimum pull-in behavior is obtained with a symmetrical, for example squarewave, waveform, that is to say if the rising edge of the signal of FIG. 1b occurs approximately 32 ⁇ s before the falling edge shown, as the line period has a duration of approximately 64 ⁇ s (European and American television standards).
  • FIG. 3 shows a line synchronizing circuit comprising two phase discriminators 1 and 2, to which a incoming line synchronizing signal is applied.
  • the output signals are applied via a change-over switch 3 to a loop filter 4, whose output voltage is the control voltage for a line oscillator 5.
  • the signal generated by oscillator 5 is further processed in known manner for line (horizontal) deflection in a picture display device of which the present circuit forms part.
  • Oscillator 5 also generates other line-frequency signals which are applied to phase discriminators 1 and 2 and also to a coincidence detector 6.
  • Detector 6 also receives the incoming line synchronizing pulses and operates change-over switch 3.
  • Phase discriminators 1 and 2 may be considered as multiplying stages for the input signals of these discriminators. Both discriminators are preceded by clamping circuits, not shown, for clamping the signal levels of each input signal.
  • the square-wave reference signal of FIG. 1b, which signal is preferably symmetrical, and also the line synchronizing signal of FIG. 1a are applied to phase discriminator 1.
  • the output signal of discriminator 1 is the signal shown in FIG. 1c and is applied, via change-over switch 3, to filter 4 for controlling oscillator 5 as long as this oscillator does not have the proper frequency and phase.
  • the two levels of the line synchronizing signal (FIG. 2a) applied to phase discriminator 2 have fixed values, while, the low level between the pulses of the reference signal shown in FIG. 2b is clamped on the average value of these levels. Multiplying these signals results in the signal shown in FIG. 2c, which is applied to filter 4 via change-over switch 3 as soon as coincidence between the input signals of detector 6 has been detected. Also filter 4 can be changed-over by detector 6, more specifically to a higher value of its time constant, which increases the noise insensitivity of the synchronizing circuit.
  • FIG. 4 shows a line synchronizing circuit comprising only one phase discriminator 1. Both inputs of this discriminator are preceded by a clamping circuit 7 and 8, respectively, and no change-over switch is provided between phase discriminator 1 and filter 4.
  • the clamping circuits 7 and 8 are changed-over by means of coincidence detector 6.
  • Phase discriminator 1 is in the form of a controllable switch having two terminals 9 and 10, which are interconnectable for conveying a signal to filter 4.
  • a switch 11 has four terminals 12, 13, 14 and 15, while a switch 16 has four terminals 17, 18, 19 and 20.
  • Terminal 12 is connected to an output of oscillator 5 at which a symmetrical square-wave signal is present.
  • Terminal 14 is connected to an output of oscillator 5 at which a pulse-shaped signal is present, the pulses having substantially the same duration as the incoming line synchronizing pulses.
  • Terminals 17 and 19 are connected to the input of the incoming line synchronizing pulses.
  • Terminals 13 and 20 are connected to terminal 9, while terminals 15 and 18 are interconnected, the signal on the connection formed operating switch 1.
  • coincidence detector 6 either terminals 12 and 13, on the one hand, and terminals 17 and 18, on the other hand, or terminals 14 and 15, on the one hand, and terminals 19 and 20, on the other hand, can be interconnected.
  • the first case is shown in FIG. 5 and occurs when there is no coincidence, while the second case occurs in the event of coincidence. If there is no coincidence, the square-wave signal from oscillator 5 is conveyed to filter 4 via terminals 9 and 10 during the occurrence of a line synchronizing pulse. This is the situation shown in FIG. 1. If there is coincidence, switch 1 is operated by the reference signal shown in FIG. 2b.
  • the line synchronizing signal is conveyed to filter 4 via terminals 9 and 10. This is the situation shown in FIG. 2.
  • the value 0 for the signals shown in FIGS. 1 and 2, respectively, is the result of the fact that switch 1 is open, while the input signals are high or low, respectively.
  • oscillator 5 in known manner as a sawtooth generator, for example a generator in which a capacitor is successively charged and discharged by means of current sources and/or resistors.
  • the required pulseshaped signals are derived from the generated sawtooth voltage.
  • FIG. 1e and 2e respectively, show the sawtooth. At the instant the descending portion of the sawtooth reaches a low d.c. voltage level, the ascending portion is initiated, for example by changing-over the current sources. This said level is derived from the control voltage generated by filter 4. If in response to this control this level assumes a higher value, then the period of the sawtooth generator becomes shorter and consequently the frequency becomes higher. From FIGS.
  • a gate pulse produced by the line oscillator and being somewhat wider than a line synchronizing pulse, becomes operative after changeover by means of the coincidence detector.
  • the phase discriminator is keyed by this gate pulse in the synchronized state so as to reduce the influence of noise and disturbances. If now an edge of the line synchronizing pulse disappears beyond this window, for example due to a phase shift in a pick-up device, then the phase discriminator receives information via only one edge, which considerably reduces the loop gain compared to the original value. If, for example, the gate pulse exceeds the synchronizing pulse by 1 ⁇ s then this error occurs already at a shift of 0.5 ⁇ s.
  • the reference pulse may have a duration which is equal to the duration of the synchronizing pulse, i.e. approximately 5 ⁇ s, a phase deviation relative to the nominal position of not more than half the duration of this pulse, i.e. approximately 2.5 ⁇ s, not having a negative effect on the loop gain.
  • the signals are always described as being pulse-shaped or square-wave signals. It should be noted that these shapes, at least as regards the reference signal, are not necessary.
  • the signal shown in FIG. 1b must indeed have the value 0 in the target state at the center instant of the pulse shown in FIG. 1a, that is to say the average value of the levels of this pulse, and it must have the value +1 and -1, respectively, some time prior to the center instant and the same length of time thereafter. So it must be antisymmetrical relative to the said instant.
  • a sine wave is alternatively suitable, and also a sawtooth or a triangular shape.
  • 2b may be replaced by any shape which is symmetrical relative to the center instant thereof, for example a triangular shape having the vertex at this instant, or a cosine-shape or keyed retrace pulse.
  • the active duration of the pulse must indeed satisfy the above-mentioned condition, so that the trailing edge of the line synchronizing pulse does not influence the control.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Biochemistry (AREA)
  • Pathology (AREA)
  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Immunology (AREA)
  • Analytical Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • General Health & Medical Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronizing For Television (AREA)
US06/529,893 1982-09-14 1983-09-07 Line synchronizing circuit for a picture display device Expired - Fee Related US4574307A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8203556 1982-09-14
NL8203556 1982-09-14

Publications (1)

Publication Number Publication Date
US4574307A true US4574307A (en) 1986-03-04

Family

ID=19840267

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/529,893 Expired - Fee Related US4574307A (en) 1982-09-14 1983-09-07 Line synchronizing circuit for a picture display device

Country Status (6)

Country Link
US (1) US4574307A (fr)
EP (1) EP0103928B1 (fr)
JP (1) JPS5966270A (fr)
KR (1) KR840005950A (fr)
AU (1) AU556566B2 (fr)
DE (1) DE3361717D1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4672447A (en) * 1984-09-03 1987-06-09 U.S. Philips Corporation Circuit arrangement for synchronization of a signal
US4872055A (en) * 1987-02-04 1989-10-03 U. S. Philips Corporation Line synchronizing circuit in a picture display device
US5113257A (en) * 1987-10-26 1992-05-12 U.S. Philips Corporation Line synchronising circuit
US5117290A (en) * 1989-10-18 1992-05-26 U.S. Philips Corporation Circuit arrangement in a picture display device, comprising a video signal processing circuit and a line synchronizing circuit
US5526527A (en) * 1993-10-01 1996-06-11 Pacific Communication Sciences, Inc. Method and apparatus for frequency synthesization in digital cordless telephones
US20070093226A1 (en) * 2003-10-21 2007-04-26 Siemens Aktiengesellschaft Precisely timed execution of a measurement or control action and synchronization of several such actions

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6187475A (ja) * 1984-09-17 1986-05-02 Seiko Epson Corp 水平同期回路
JPS61182385A (ja) * 1985-02-07 1986-08-15 Matsushita Electric Ind Co Ltd 信号処理装置
JPS61182386A (ja) * 1985-02-07 1986-08-15 Matsushita Electric Ind Co Ltd 信号処理装置
JPS62169585A (ja) * 1986-01-22 1987-07-25 Seiko Epson Corp 水平同期回路

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4214260A (en) * 1975-10-03 1980-07-22 U.S. Philips Corporation Circuit for the line synchronization in a television receiver having a gated auxiliary control loop

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7714033A (nl) * 1977-12-19 1979-06-21 Philips Nv Televisie-ontvanger met een lijnsynchroniseer- schakeling.
JPS5547774A (en) * 1978-09-29 1980-04-04 Sony Corp Phase synchronism circuit
JPS5546618A (en) * 1978-09-29 1980-04-01 Sony Corp Phase synchronizing circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4214260A (en) * 1975-10-03 1980-07-22 U.S. Philips Corporation Circuit for the line synchronization in a television receiver having a gated auxiliary control loop

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4672447A (en) * 1984-09-03 1987-06-09 U.S. Philips Corporation Circuit arrangement for synchronization of a signal
US4872055A (en) * 1987-02-04 1989-10-03 U. S. Philips Corporation Line synchronizing circuit in a picture display device
US5113257A (en) * 1987-10-26 1992-05-12 U.S. Philips Corporation Line synchronising circuit
US5117290A (en) * 1989-10-18 1992-05-26 U.S. Philips Corporation Circuit arrangement in a picture display device, comprising a video signal processing circuit and a line synchronizing circuit
US5526527A (en) * 1993-10-01 1996-06-11 Pacific Communication Sciences, Inc. Method and apparatus for frequency synthesization in digital cordless telephones
US20070093226A1 (en) * 2003-10-21 2007-04-26 Siemens Aktiengesellschaft Precisely timed execution of a measurement or control action and synchronization of several such actions
US7457601B2 (en) * 2003-10-21 2008-11-25 Siemens Aktiengesellschaft Precisely timed execution of a measurement or control action and synchronization of several such actions

Also Published As

Publication number Publication date
AU1902183A (en) 1984-03-22
DE3361717D1 (en) 1986-02-13
KR840005950A (ko) 1984-11-19
JPS5966270A (ja) 1984-04-14
EP0103928A1 (fr) 1984-03-28
AU556566B2 (en) 1986-11-06
EP0103928B1 (fr) 1986-01-02

Similar Documents

Publication Publication Date Title
KR100307979B1 (ko) 보조비디오데이타슬라이서
EP0070603B1 (fr) Circuit de synchronisation pour un récepteur de télévision
US4574307A (en) Line synchronizing circuit for a picture display device
US4228462A (en) Line oscillator synchronizing circuit
GB2229592A (en) Phase detectors
EP0532354A1 (fr) Circuit à verrouillage pour verrouiller un signal vidéo contenant un signal de synchronisation
KR910005094B1 (ko) 화상 표시장치용 라인동기 회로
US4461999A (en) Circuit for producing a periodic sawtooth shaped signal
EP0168089B1 (fr) Circuit de séparation d'un signal de synchronisation d'un signal vidéo entrant
US5963267A (en) Delay correction circuit
US4872055A (en) Line synchronizing circuit in a picture display device
US5404230A (en) Color burst phase correcting color signal reproducing circuit
US7777813B2 (en) Color burst automatic detection device
US5053869A (en) Digital circuit arrangement detecting synchronizing pulses
JPH0214674A (ja) 正確な同期パルス分離方法および装置
US4600944A (en) Low cost synchronizing signal separator
EP0059379B1 (fr) Circuit détecteur de bruit et récepteur de télévision comportant un tel circuit
JP3209741B2 (ja) 同期装置
US5003391A (en) Circuitry for processing a synchronizing signal
JP3353919B2 (ja) 同期パルス発生装置
KR100228664B1 (ko) 영상신호 유무판별장치
JPH0225314B2 (fr)
JP2503023Y2 (ja) 映像中間周波信号のａｇｃ回路
JPS5979686A (ja) テレビジョン信号のタイミング抽出装置
JPS6116678A (ja) フイ−ルド同期信号発生回路

Legal Events

Date Code Title Description
AS Assignment

Owner name: U.S. PHILIPS CORPORATION, 100 EAST 42ND ST., NEW

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:NILLESEN, ANTONIUS H. H. J.;REEL/FRAME:004177/0916

Effective date: 19830914

Owner name: U.S. PHILIPS CORPORATION, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NILLESEN, ANTONIUS H. H. J.;REEL/FRAME:004177/0916

Effective date: 19830914

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
FP Lapsed due to failure to pay maintenance fee

Effective date: 19940306

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362