JPS5546618A - Phase synchronizing circuit - Google Patents

Phase synchronizing circuit

Info

Publication number
JPS5546618A
JPS5546618A JP11924978A JP11924978A JPS5546618A JP S5546618 A JPS5546618 A JP S5546618A JP 11924978 A JP11924978 A JP 11924978A JP 11924978 A JP11924978 A JP 11924978A JP S5546618 A JPS5546618 A JP S5546618A
Authority
JP
Japan
Prior art keywords
phase
synchronizing circuit
phase synchronizing
plls
primary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11924978A
Other languages
Japanese (ja)
Other versions
JPS614232B2 (en
Inventor
Mitsushige Tadami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP11924978A priority Critical patent/JPS5546618A/en
Publication of JPS5546618A publication Critical patent/JPS5546618A/en
Publication of JPS614232B2 publication Critical patent/JPS614232B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Synchronizing For Television (AREA)
  • Television Signal Processing For Recording (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: To simplify a phase synchronizing circuit and also to enable it to operate definitely by combining a primary phase synchronizing circuit and secondary phase synchronizing circuit together.
CONSTITUTION: A series circuit of phase comparator 26 and LPF 27 constituting primary phase synchronizing circuit PLL and that of phase comparator 28 and LPF 29 constituting secondary PLL are connected to input terminal 25 and adder 30. Through voltage control oscillator 31 and divider 32, their outputs are led to the inputs of circuits 26 and 28 to constitute a phase synchronizing circuit. Since primary and secondary PLLs are connected in common through adder 30 except phase comparators and LPFs, demerits of two PLLs are compensated by themselves each other. Therefore, an input signal would vary in frequency or phase, follow-up characteristics by an output signal are excellent and those PLLs operate definitely without staionary phase error.
COPYRIGHT: (C)1980,JPO&Japio
JP11924978A 1978-09-29 1978-09-29 Phase synchronizing circuit Granted JPS5546618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11924978A JPS5546618A (en) 1978-09-29 1978-09-29 Phase synchronizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11924978A JPS5546618A (en) 1978-09-29 1978-09-29 Phase synchronizing circuit

Publications (2)

Publication Number Publication Date
JPS5546618A true JPS5546618A (en) 1980-04-01
JPS614232B2 JPS614232B2 (en) 1986-02-07

Family

ID=14756644

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11924978A Granted JPS5546618A (en) 1978-09-29 1978-09-29 Phase synchronizing circuit

Country Status (1)

Country Link
JP (1) JPS5546618A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5966270A (en) * 1982-09-14 1984-04-14 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Line tuning circuit for image display unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5966270A (en) * 1982-09-14 1984-04-14 エヌ・ベ−・フイリツプス・フル−イランペンフアブリケン Line tuning circuit for image display unit

Also Published As

Publication number Publication date
JPS614232B2 (en) 1986-02-07

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