US4538121A - High frequency generator with output shut-off or reduced by biasing multiplier diode - Google Patents

High frequency generator with output shut-off or reduced by biasing multiplier diode Download PDF

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US4538121A
US4538121A US06/452,922 US45292282A US4538121A US 4538121 A US4538121 A US 4538121A US 45292282 A US45292282 A US 45292282A US 4538121 A US4538121 A US 4538121A
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multiplier
signal
operatively connected
diode
output
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Yasuhiro Yano
Isamu Umino
Zenichi Ohsawa
Takayuki Ozaki
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Fujitsu Ltd
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Fujitsu Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
    • H03B19/16—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source using uncontrolled rectifying devices, e.g. rectifying diodes or Schottky diodes
    • H03B19/18—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source using uncontrolled rectifying devices, e.g. rectifying diodes or Schottky diodes and elements comprising distributed inductance and capacitance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/10—Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/20—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a harmonic phase-locked loop, i.e. a loop which can be locked to one of a number of harmonically related frequencies applied to it
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/02—Phase locked loop having lock indicating or detecting means

Definitions

  • This invention relates to a device for generating high frequency signals such as microwave or milliwave signals and particularly to a method of controlling an output of a high frequency generator, including miltiplier means, having diodes, within the output of the generator.
  • High frequency generators generators used for obtaining predetermined frequency signals by multiplying the outputs from a high frequency oscillator comprising a frequency stabilizing circuit such as Phase Lock Loop (PLL), are known.
  • the high frequency generating means is required to turn the output off for a while after the power switch is turned on, because an abnormal frequency may be generated up until the frequency stabilization reaches a steady state due to the operation of a frequency stabilizing circuit.
  • PLL Phase Lock Loop
  • the output of a high frequency generating means is turned off by the following methods: first, an ON/OFF circuit, such as diode switch using a PIN diode or coaxial relay, is inserted into the output and second, an output is turned off through suspension of operation by changing the bias of an amplifier used in the output circuit.
  • the former method has a disadvantage in that the circuit structure is complicated because an ON/OFF circuit is added and moreover signal loss therein is inevitable.
  • the latter method cannot be applied in a device not having an amplifier. In both of these methods, the output is turned off in the output frequency stage and shielding must be taken into account in order to obtain a large attenuation of the output, resulting in an increase in the device cost.
  • this invention provides a high frequency generator which is capable of attentuating and turning off the output by forming a multiplier means, connected to the output of an oscillator, having a diode and controlling the bias voltage applied to the diode.
  • FIG. 1 is a block diagram of an embodiment of a high frequency generator of the invention
  • FIG. 2 is a schematic diagram of the multiplier means 6 of FIG. 1;
  • FIG. 3 is a schematic diagram of a second embodiment of the multiplier means 6 of FIG. 1;
  • FIG. 4 is a waveform diagram of the input signal of the multiplier means and the output signal of a step recovery diode
  • FIG. 5 (a) and (b) are schematic diagrams of the bias voltage controlling means 11 of FIG. 1;
  • FIG. 6 is a graph of the bias voltage controlling characteristic of the multiplier means 6 of FIG. 1.
  • FIG. 1 is an embodiment of a high frequency generator of the invention.
  • 1 is a voltage controlled oscillator (referred to hereinafter as a VCO).
  • An output of the VCO 1 is applied to a harmonic mixer 2 and is compared with a reference frequency input signal from terminal 3.
  • An error signal output of the harmonic mixer 2 is fed back to the VCO 1 through a loop filter 4, thus forming a phase lock loop (referred to hereinafter as a PLL).
  • An output of the VCO 1 is applied to a multiplier means 6 via a circulator 5, forming an isolator, and is multiplied to provide a high frequency output to the output terminal 7.
  • a monitoring circuit 8 monitors the synchronization of the PLL depending on the output of the loop filter 4. When the detected output of the monitoring circuit becomes OFF, a bias controlling means 11 generates a specified control voltage and the voltage is applied to the multiplier means 6. Thus, the high frequency output of the multiplier means 6 becomes OFF.
  • the PLL circuit comprising the VCO 1, harmonic mixer 2 and loop filter 4, is already known.
  • the oscillation frequency f o of the VCO 1 is controlled by a signal applied thereto via the loop filter 4.
  • the error signal output of the harmonic mixer 2 passes the loop filter 4 and is fed back to the VCO 1 as a high frequency control voltage. Accordingly, control is carried out in the PLL circuit so that the error signal output from the harmonic mixer 2 is close to zero, thereby stabilizing the oscillation frequency of the VCO 1.
  • An oscillation output signal of the VCO 1 is input to the multiplier means 6 via the circulator 5.
  • the circulator 5 is provided to reduce the load effect on the multiplier means 6
  • FIG. 2 is an example of a multiplier means using a step recovery diode.
  • a resonant circuit, 62 resonates with the input signal f 0 .
  • An output of the resonant circuit 62 is supplied to the SRD 64 via a small driving inductance 63 which is equivalently formed by a lead wire.
  • a bias voltage V c is input to the SRD 64 via the decreasing connector circuit comprising a resistor 65, bypass capacitor 66 and resistor 67.
  • the SRD 64 can be alternately biased forward and reverse for each cycle of the input signal f 0 by providing an adequate bias voltage V c .
  • V c the SRD 64 is forward biased, energy is accumulated in the driving inductance 63, and when the SRD 64 is reverse biased and the static capacitance is switched from C FWD to C VR , energy accumulated in the inductance is released. Thus a narrow high frequency pulse is generated across the SRD 64.
  • FIG. 4 shows waveforms of the input signal of multiplier means and the output of the step recovery diode.
  • (a) is the waveform of signal f 0 of the input terminal 61, which is almost a sine wave having an amplitude of e 1 and period of T 1 .
  • (b) is the output waveform of the SRD 64 having the same period T 1 and is a sharp pulse.
  • the sharp pulse waveform usually contains harmonics of higher orders and the multiplier means can extract the signal of desired order from the harmonics.
  • FIG. 3 is a second circuit structure of multiplier means utilizing a step recovery diode.
  • the circuit is preferred for use in a plane circuit formed with a micro-strip line.
  • the portions given the same reference numbers as those of FIG. 2 indicate the same element.
  • an idler 70 comprising an LC series circuit having the specified resonant frequency is connected to bias supplying means.
  • the idler 70 functions as a band-reject filter (BRF) and reduces the impedance of the specific frequency near the SRD 64.
  • BRF band-reject filter
  • the idler 70 is composed of the LC circuits which respectively, resonate at the frequencies of 4 GHz and 6 GHz.
  • the high frequency signal having passed the idler 70, is input to the resonator circuit 71 in order to extract only the specified multiplied frequency signal.
  • the signal obtained from the resonator circuit 71 is output to the output terminal 72.
  • FIG. 5 is a circuit diagram of a bias voltage control circuit.
  • FIG. 5 (a) is an example a bias voltage control circuit using a transistor 111.
  • the NPN transistor 111 is in a cut-off condition when an input signal is not applied from an input terminal 112 and therefore a positive voltage is generated at the output terminal 113 from the power source V s via an resistor 114.
  • the transistor 111 becomes conductive and its collector voltage becomes approximately 0 V and therefore the output terminal 113 is set to ground potential.
  • the bias voltage of multiplier means 8 changes.
  • FIG. 5 (b ) is a bias voltage control circuit using a relay in place of a transistor.
  • the NPN transistor When there is no input at the terminal 112, the NPN transistor is in the cut-off condition, making the relay 116 inoperative. Therefore, the contact 117 closes and a positive voltage is generated at the output terminal 113 from the power source V s via the voltage dividing circuit comprising the resistors 118 and 119.
  • the transistor 115 becomes conductive, the relay 116 operates, the contact 117 opens and the terminal 113 is set to ground potential.
  • the above embodiment is an example of using a step recovery diode as the semiconductor device used in the multiplier means 6, but application is not limited in the present invention only to a step recovery diode. That is, the multiplication efficiency in the multiplier means is changed, depending on the bias voltage, by using other types of diodes.
  • FIG. 6 is a graph of the output reduction characteristic where the bias voltage of the multiplier means is changed.
  • the horizontal axis indicates the bias voltage V c
  • an output of a high frequency generator comprising generating means and multiplier means including a diode for mutiplying an output frequency of the generating means, can be kept off or the voltage reduced by suspending or suppressing the multiplying operation through the control of the bias voltage of the diode used in the multiplier means.
  • a high frequency output can be cut-off by controlling a generator using the multiplier means.
  • the circuit structure can be simplified and a sufficiently large output attenuation can be realized by suspending the operation of the multiplier means. From this point of view, the invention is very effective in keeping the output of the device off.
  • microwave generator of this invention is also capable of controlling an output signal with a control signal from an external circuit.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A high frequency generator including a frequency generator and a multiplier, the multiplier including a diode, which multiplies the output frequency of the frequency generator, and shuts off or reduces an output by suspending or suppressing the multiplying operation through the control of a bias voltage applied to the diode used in the multiplier. The system for cutting off the output by controlling the multiplier is very effective for simplifying the circuit structure and reliably turning off the output.

Description

BACKGROUND OF THE INVENTION
This invention relates to a device for generating high frequency signals such as microwave or milliwave signals and particularly to a method of controlling an output of a high frequency generator, including miltiplier means, having diodes, within the output of the generator.
High frequency generators, generators used for obtaining predetermined frequency signals by multiplying the outputs from a high frequency oscillator comprising a frequency stabilizing circuit such as Phase Lock Loop (PLL), are known. The high frequency generating means is required to turn the output off for a while after the power switch is turned on, because an abnormal frequency may be generated up until the frequency stabilization reaches a steady state due to the operation of a frequency stabilizing circuit.
The output of a high frequency generating means is turned off by the following methods: first, an ON/OFF circuit, such as diode switch using a PIN diode or coaxial relay, is inserted into the output and second, an output is turned off through suspension of operation by changing the bias of an amplifier used in the output circuit. The former method has a disadvantage in that the circuit structure is complicated because an ON/OFF circuit is added and moreover signal loss therein is inevitable. The latter method cannot be applied in a device not having an amplifier. In both of these methods, the output is turned off in the output frequency stage and shielding must be taken into account in order to obtain a large attenuation of the output, resulting in an increase in the device cost.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide means having a simple circuit structure for reliably turning off an output by controlling a bias voltage applied to a mulitplying means, included in a high frequency generating means, comprising an oscillator and a multiplier.
Therefore, this invention provides a high frequency generator which is capable of attentuating and turning off the output by forming a multiplier means, connected to the output of an oscillator, having a diode and controlling the bias voltage applied to the diode.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a block diagram of an embodiment of a high frequency generator of the invention;
FIG. 2 is a schematic diagram of the multiplier means 6 of FIG. 1;
FIG. 3 is a schematic diagram of a second embodiment of the multiplier means 6 of FIG. 1;
FIG. 4 is a waveform diagram of the input signal of the multiplier means and the output signal of a step recovery diode;
FIG. 5 (a) and (b) are schematic diagrams of the bias voltage controlling means 11 of FIG. 1; and
FIG. 6 is a graph of the bias voltage controlling characteristic of the multiplier means 6 of FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 is an embodiment of a high frequency generator of the invention. In FIG. 1, 1 is a voltage controlled oscillator (referred to hereinafter as a VCO). An output of the VCO 1 is applied to a harmonic mixer 2 and is compared with a reference frequency input signal from terminal 3. An error signal output of the harmonic mixer 2 is fed back to the VCO 1 through a loop filter 4, thus forming a phase lock loop (referred to hereinafter as a PLL). An output of the VCO 1 is applied to a multiplier means 6 via a circulator 5, forming an isolator, and is multiplied to provide a high frequency output to the output terminal 7. A monitoring circuit 8 monitors the synchronization of the PLL depending on the output of the loop filter 4. When the detected output of the monitoring circuit becomes OFF, a bias controlling means 11 generates a specified control voltage and the voltage is applied to the multiplier means 6. Thus, the high frequency output of the multiplier means 6 becomes OFF.
The PLL circuit comprising the VCO 1, harmonic mixer 2 and loop filter 4, is already known. The oscillation frequency fo of the VCO 1 is controlled by a signal applied thereto via the loop filter 4. However, since the reference frequency input signal, fR =fo /n1, having a high frequency stability and generated by a crystal oscillator etc., is applied to the terminal 3, the harmonic mixer 2 compares the phases between the harmonic fo which is n1 times the reference frequency signal and an output signal fo of the VCO 1 and generates an error signal output. The error signal output of the harmonic mixer 2 passes the loop filter 4 and is fed back to the VCO 1 as a high frequency control voltage. Accordingly, control is carried out in the PLL circuit so that the error signal output from the harmonic mixer 2 is close to zero, thereby stabilizing the oscillation frequency of the VCO 1.
An oscillation output signal of the VCO 1 is input to the multiplier means 6 via the circulator 5. The circulator 5 is provided to reduce the load effect on the multiplier means 6 When the input frequency f0 is about 2 GHz, the multiplier means 6 uses a step recovery diode (referred to hereinafter as a SRD) as a semiconductor element and is capable of obtaining the multiplication steps n2 =4, etc.
FIG. 2 is an example of a multiplier means using a step recovery diode. In the figure, 61 is an input terminal and the input signal, for example, f0 =2 GHz is input thereto. A resonant circuit, 62 resonates with the input signal f0. An output of the resonant circuit 62 is supplied to the SRD 64 via a small driving inductance 63 which is equivalently formed by a lead wire. A bias voltage Vc is input to the SRD 64 via the decreasing connector circuit comprising a resistor 65, bypass capacitor 66 and resistor 67. The SRD 64 is provided within a waveguide 68 and a multiplier signal generated by the SRD 64, for example, 4f0 =8 GHz can be extracted from the waveguide output 69.
The step recovery diode changes its equivalent capacitance depending on the bias condition. It has a very small static capacitance CVR determined by the diode characteristic under a reverse bias condition and a large static capacitance CFWD under a forward bias condition. Usually, CVR =0.5 to 5 pF and CFWD goes to infinity. In the circuit of FIG. 2, the SRD 64 can be alternately biased forward and reverse for each cycle of the input signal f0 by providing an adequate bias voltage Vc. When the SRD 64 is forward biased, energy is accumulated in the driving inductance 63, and when the SRD 64 is reverse biased and the static capacitance is switched from CFWD to CVR, energy accumulated in the inductance is released. Thus a narrow high frequency pulse is generated across the SRD 64.
FIG. 4 shows waveforms of the input signal of multiplier means and the output of the step recovery diode. In the figure, (a) is the waveform of signal f0 of the input terminal 61, which is almost a sine wave having an amplitude of e1 and period of T1. On the other hand, (b) is the output waveform of the SRD 64 having the same period T1 and is a sharp pulse. The sharp pulse waveform usually contains harmonics of higher orders and the multiplier means can extract the signal of desired order from the harmonics. In FIG. 2, the waveguide 68 equivalently forming a band-pass filter which resonates at the specified frequency band. For example, only the quadrupled harmonic 4f0 =8 GHz is selected and extracted through the output terminal 69. In the circuit of FIG. 2, when a high frequency f0 =2.0 GHz with a level of 20 dBm is input, an output of for example, a higher frequency 4f0 and a level of, about 15 dBm, is obtained with the bias voltage Vc =0.
FIG. 3 is a second circuit structure of multiplier means utilizing a step recovery diode. The circuit is preferred for use in a plane circuit formed with a micro-strip line. In FIG. 3, the portions given the same reference numbers as those of FIG. 2 indicate the same element.
In the example of the circut shown in FIG. 3, an idler 70 comprising an LC series circuit having the specified resonant frequency is connected to bias supplying means. The idler 70 functions as a band-reject filter (BRF) and reduces the impedance of the specific frequency near the SRD 64. For example, the input signal fo =2 GHz sent from the input terminal 61, is input to the SRD 64 and the harmonic signals are extracted and input to the idler 70. The idler 70 is composed of the LC circuits which respectively, resonate at the frequencies of 4 GHz and 6 GHz. The specific frequency signals are reflected and are again input to the SRD 64. Energy of the reflected signals is used for extraction of the specified multiplied frequency signal, for example 4fo =8 GHz, improving efficiency of operation.
The high frequency signal, having passed the idler 70, is input to the resonator circuit 71 in order to extract only the specified multiplied frequency signal. The resonantor circuit 71 allows, for example, only the 4fo signal=8 GHz to pass and provides the function of a band-pass filter. It functions as the waveguide 69 shown in FIG. 2. The signal obtained from the resonator circuit 71 is output to the output terminal 72.
In the high frequency generator shown in FIG. 1, the synchronization of the PLL circuit is monitored by the monitoring circuit 8. It does so by obtaining the synchronous detecting signal from a subtraction output by comparison of the control voltage and reference voltage signal utilizing, for example, that the control voltage is fed back to the VCO 1 via the loop filter 4 and is not in the specified voltage range during the synchronous condition. When a synchronous detecting signal is generated from the monitoring circuit 8, the bias control circuit 11 is controlled and thereby the bias voltage of the multiplier means is changed. FIG. 5 is a circuit diagram of a bias voltage control circuit. FIG. 5 (a) is an example a bias voltage control circuit using a transistor 111. The NPN transistor 111 is in a cut-off condition when an input signal is not applied from an input terminal 112 and therefore a positive voltage is generated at the output terminal 113 from the power source Vs via an resistor 114. When the synchronous detecting signal is applied to the terminal 112, the transistor 111 becomes conductive and its collector voltage becomes approximately 0 V and therefore the output terminal 113 is set to ground potential. Thus, the bias voltage of multiplier means 8 changes.
FIG. 5 (b ) is a bias voltage control circuit using a relay in place of a transistor. When there is no input at the terminal 112, the NPN transistor is in the cut-off condition, making the relay 116 inoperative. Therefore, the contact 117 closes and a positive voltage is generated at the output terminal 113 from the power source Vs via the voltage dividing circuit comprising the resistors 118 and 119. When the synchronous detecting signal is applied to the terminal 112, the transistor 115 becomes conductive, the relay 116 operates, the contact 117 opens and the terminal 113 is set to ground potential.
Meanwhile, an oscillation output is applied from the VCO 1 to the multiplier means 6 in addition to the bias voltage as explained previously. Therefore, when the bias voltage Vc becomes a higher level than the amplitude of oscillation output signal, the SRD 64 is in the conductive condition, switching between the static capacitances CFWD and CVR is no longer performed at the SRD 64, and the multiplication operation stops. In each circuit of FIG. 5, if a negative bias voltage output is obtained when the synchronous detecting signal is not applied and if the bias voltage level is higher than the oscillation amplitude, the SRD 64 is always in the cut-off condition. In the same way, switching between static capacitances CVR and CFWD is no longer carried out in the SRD 64 and the multiplication operation stops. The above embodiment is an example of using a step recovery diode as the semiconductor device used in the multiplier means 6, but application is not limited in the present invention only to a step recovery diode. That is, the multiplication efficiency in the multiplier means is changed, depending on the bias voltage, by using other types of diodes.
FIG. 6 is a graph of the output reduction characteristic where the bias voltage of the multiplier means is changed. The horizontal axis indicates the bias voltage Vc, while the vertical axis indicates reduction of the output of the multiplier means resulting from changes in the bias voltage Vc with reference to Vc=0 (at 0 db). The bias voltage Vc around Vc =0 changes about +0.2 V and the output voltage of the multiplier means changes slightly. In the range of +1 V or more or -2.2 V or less, it has been confirmed that the output voltage of the multiplier means is zero or very small.
According to the invention, an output of a high frequency generator comprising generating means and multiplier means including a diode for mutiplying an output frequency of the generating means, can be kept off or the voltage reduced by suspending or suppressing the multiplying operation through the control of the bias voltage of the diode used in the multiplier means.
Therefore, according to the microwave generator of the invention, a high frequency output can be cut-off by controlling a generator using the multiplier means. Thus, the circuit structure can be simplified and a sufficiently large output attenuation can be realized by suspending the operation of the multiplier means. From this point of view, the invention is very effective in keeping the output of the device off.
In addition, explained in the above embodiment is only a method of controlling a microwave output with the synchronous detecting signal sent from the PLL, but the microwave generator of this invention is also capable of controlling an output signal with a control signal from an external circuit.

Claims (8)

What is claimed is:
1. A high frequency generator comprising:
generating means for generating a high frequency signal, said generating means comprising a phase-locked loop, including:
a voltage controlled oscillator generating a first output signal and having an input terminal;
a reference signal generator, operatively connected to said voltage controlled oscillator, for providing a reference signal;
mixing means having an output terminal, operatively connected to said voltage controlled oscillator and said reference signal generator, for mixing the first output signal and the reference signal, and outputting a signal in accordance with a phase-difference between the first output signal and the reference signal; and
a loop-filter, operatively connected to said output terminal of said mixing means and said input terminal of said voltage controlled oscillator, for supplying a control signal to said voltage controlled oscillator, wherein said voltage controlled oscillator generates the first output signal in dependence upon the control signal supplied from said loop-filter;
multiplier means, operatively connected to said generating means, for receiving and multiplying the high frequency signal and outputting harmonic frequency signals, said multiplier means including:
an input terminal, operatively connected to said generating means, for receiving the high frequency signal;
a multiplier diode, operatively connected to said input terminal, for providing harmonic frequency signals of the high frequency signal; and
means, operatively connected to said multiplier diode, for supplying a bias voltage to said multiplier diode, so that the harmonic frequency signals of said multiplier means are controlled in accordance with the bias voltage supplied to said multiplier diode;
bias controlling means, operatively connected to said multiplier means, for controlling the bias voltage supplied to said multiplier diode;
output means, operatively connected to receive the harmonic frequency signals from said multiplier means, for outputting a fixed harmonic signal of the harmonic frequency signals; and
a monitoring circuit, operatively connected to said output terminal of said mixing means, for monitoring the synchronization between the reference signal and the first output signal from said voltage controlled oscillator, and for providing an alarm signal to said bias controlling means when the synchronization is not detected by said monitoring circuit.
2. A generator according to claim 1, wherein said multiplier diode is a step-recovery diode.
3. A generator according to claim 1, wherein said multiplier means further includes a wave guide operatively connected to said multiplier diode.
4. A generator according to claim 1, wherein said multiplier means further includes a resonator circuit, operatively connected to said bias voltage supplying means, for resonating at a specified frequency and outputting the fixed harmonic signal.
5. A generator according to claim 1, wherein said mixing means is a harmonic mixer circuit, and wherein said harmonic mixer circuit outputs a signal proportional to the difference between the first output signal of said voltage controlled oscillator and the reference signal.
6. A generator according to claim 1, wherein said multiplier means further comprises:
a resonator circuit, operatively connected between said input terminal of said multiplier means and said multiplier diode, for resonating at a specified frequency and supplying the specified frequency to said multiplier diode;
a driving inductance, operatively connected between said resonator circuit and said multiplier diode, for driving said multiplier diode which provides the harmonic frequency signals; and
a waveguide, operatively connected to said multiplier diode, having a specified resonant frequency and wherein said multiplier diode is mounted.
7. A generator according to claim 1, wherein said multiplier means has an output terminal and further comprises:
a first resonator circuit having an output, operatively connected between said input terminal of said multiplier means and said multiplier diode, for resonating at a specified frequency and supplying the specified frequency to said multiplier diode;
a driving inductance, operatively connected between said first resonator circuit and said multiplier diode, for driving said multiplier diode to provide the harmonic frequency signals;
an idler circuit, operatively connected to said multiplier diode, for reflecting a specified frequency signal and supplying energy to said multiplier diode; and
a second resonator circuit, operatively connected between said idler circuit and the output terminal of said multiplier means, for resonating at the specified frequency to provide the fixed harmonic signal at the output terminal.
8. A high frequency generator comprising:
generating means for generating a frequency signal, comprising a phase-locked loop, including:
a voltage controlled oscillator having a first output signal and having an input terminal;
a reference signal generator, operatively connected to said voltage controlled oscillator, for providing a reference signal;
mixing means having an output terminal, operatively connected to said voltage controlled oscillator and said reference signal generator, for mixing the first output signal and the reference signal, and outputting a signal in accordance with a phase-difference between the first output signal and the reference signal; and
a loop-filter, operatively connected to said output terminal of said mixing means and said input terminal of said voltage controlled oscillator, for supplying a control signal to said voltage controlled oscillator, wherein said voltage controlled oscillator generates the first output signal in dependence upon the control signal supplied from said loop-filter;
multiplier means, operatively connected to said generating means, for receiving and multiplying the frequency signal and providing harmonic frequency signals having a frequency higher than that of the frequency signal of the generating means, said multiplier means comprising:
an input terminal, operatively connected to said generating means, for receiving the frequency signal;
a multiplier diode, operatively connected to said input terminal, for providng harmonic frequency signals of the frequency signal; and
means, operatively connected to said multiplier diode, for supplying a bias voltage to said multiplier diode, the harmonic frequency signals of said multiplier means being controlled in accordance with the bias voltage supplied to said multiplier diode;
bias controlling means, operatively connected to said multiplier means for controlling the bias voltage supplied to said multiplier diode;
an output terminal, operatively connected to said multiplier means, for outputting a fixed harmonic signal of the harmonic frequency signals; and
a monitoring circut, operatively connected to said output terminal of said mixing means, for monitoring the synchronization between the reference signal and the first output signal from said voltage controlled oscillator, and for providing an alarm signal to said bias controlling means when synchronization between the reference signal and the first output signal is not detected by said monitoring means.
US06/452,922 1981-12-29 1982-12-27 High frequency generator with output shut-off or reduced by biasing multiplier diode Expired - Fee Related US4538121A (en)

Applications Claiming Priority (2)

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JP56-212127 1981-12-29
JP56212127A JPS58125916A (en) 1981-12-29 1981-12-29 Microwave generator

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999004282A1 (en) * 1997-07-19 1999-01-28 Robert Bosch Gmbh Device for sending and receiving radar waves, especially for a distance sensor

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63246061A (en) * 1987-04-01 1988-10-13 Matsushita Electric Works Ltd Pulse modulation transmission circuit
JPH01115249A (en) * 1987-10-29 1989-05-08 Hochiki Corp Data transmission equipment

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3307117A (en) * 1964-10-29 1967-02-28 Itt High frequency generator employing step recovery diode
US3397369A (en) * 1965-08-24 1968-08-13 Microwave Ass Harmonic generator and frequency multiplier biasing system
US3401355A (en) * 1966-10-31 1968-09-10 Ryan Aeronautical Co Step recovery diode frequency multiplier
US3671880A (en) * 1970-02-05 1972-06-20 Philips Corp Device for generating a plurality of sinusoidal oscillations in a carrier telephony system
US3697995A (en) * 1967-11-20 1972-10-10 Ryan Aeronautical Co Increased power electronically scanning integrated antenna system
DE2350626A1 (en) * 1973-10-09 1975-04-10 Kathrein Werke Kg Pilot frequency generator with frequency multiplier - produces constant amplitude signal, and has an oscillator oscillating at a pilot harmonic
US4039968A (en) * 1976-05-11 1977-08-02 Bell Telephone Laboratories, Incorporated Synchronizing circuit
US4199734A (en) * 1977-12-02 1980-04-22 Siemens Aktiengesellschaft Crystal oscillator having switchably disabled harmonic-tuned output circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4208635A (en) * 1978-08-14 1980-06-17 Scientific Micro Systems, Inc. Active filter and phase-locked loop using same
CA1111114A (en) * 1978-08-31 1981-10-20 Trevor W. Tucker Microwave frequency division by phase locked loops
JPS5939929B2 (en) * 1979-05-08 1984-09-27 三菱電機株式会社 Phase synchronization detection circuit
JPS5666906A (en) * 1979-11-02 1981-06-05 Mitsubishi Electric Corp Frequency multiplying circuit

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3307117A (en) * 1964-10-29 1967-02-28 Itt High frequency generator employing step recovery diode
US3397369A (en) * 1965-08-24 1968-08-13 Microwave Ass Harmonic generator and frequency multiplier biasing system
US3401355A (en) * 1966-10-31 1968-09-10 Ryan Aeronautical Co Step recovery diode frequency multiplier
US3697995A (en) * 1967-11-20 1972-10-10 Ryan Aeronautical Co Increased power electronically scanning integrated antenna system
US3671880A (en) * 1970-02-05 1972-06-20 Philips Corp Device for generating a plurality of sinusoidal oscillations in a carrier telephony system
DE2350626A1 (en) * 1973-10-09 1975-04-10 Kathrein Werke Kg Pilot frequency generator with frequency multiplier - produces constant amplitude signal, and has an oscillator oscillating at a pilot harmonic
US4039968A (en) * 1976-05-11 1977-08-02 Bell Telephone Laboratories, Incorporated Synchronizing circuit
US4199734A (en) * 1977-12-02 1980-04-22 Siemens Aktiengesellschaft Crystal oscillator having switchably disabled harmonic-tuned output circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Kuno, H. J. et al., "Solid State Millimeter-Wave Sources" 24-2A-EASCON 77, Arlington, Va., USA, pp. 26-28, Sep. '77.
Kuno, H. J. et al., Solid State Millimeter Wave Sources 24 2A EASCON 77, Arlington, Va., USA, pp. 26 28, Sep. 77. *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999004282A1 (en) * 1997-07-19 1999-01-28 Robert Bosch Gmbh Device for sending and receiving radar waves, especially for a distance sensor

Also Published As

Publication number Publication date
JPS58125916A (en) 1983-07-27
EP0083238B1 (en) 1988-07-27
DE3278849D1 (en) 1988-09-01
EP0083238A3 (en) 1985-05-29
EP0083238A2 (en) 1983-07-06

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