US4472788A - Shift circuit having a plurality of cascade-connected data selectors - Google Patents

Shift circuit having a plurality of cascade-connected data selectors Download PDF

Info

Publication number
US4472788A
US4472788A US06/296,859 US29685981A US4472788A US 4472788 A US4472788 A US 4472788A US 29685981 A US29685981 A US 29685981A US 4472788 A US4472788 A US 4472788A
Authority
US
United States
Prior art keywords
data
bits
register
shift
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US06/296,859
Other languages
English (en)
Inventor
Isamu Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Assigned to TOKYO SHIBAURA DENKI KABUSHIKI KAISHA 72 HORIKAWA-CHO, SAIWAI-KU, KAWASAKI-SHI, JAPAN A CORP. OF reassignment TOKYO SHIBAURA DENKI KABUSHIKI KAISHA 72 HORIKAWA-CHO, SAIWAI-KU, KAWASAKI-SHI, JAPAN A CORP. OF ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: YAMAZAKI, ISAMU
Application granted granted Critical
Publication of US4472788A publication Critical patent/US4472788A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/015—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising having at least two separately controlled shifting levels, e.g. using shifting matrices

Definitions

  • This invention relates to an improved shift circuit which shifts data at a high speed.
  • FIG. 1 is a schematic block circuit diagram of a central processing unit 2 (hereinafter called "CPU 2").
  • the CPU 2 is a single chip circuit comprising temporary registers (A, T, B, M) 4, an arithmetic logic circuit 8, a shifter 10, a microprogram ROM 12, a branch control unit 14, a status control unit 16, a common bus buffer/receiver 18, a timing generator & bus controller 22, and a special function unit 26.
  • the temporary registers 4 store data supplied through an internal bus 6.
  • the arithmetic logic unit 8 carries out arithmetic logic operations such as addition, subtraction, AND, OR with respect to data set from the temporary registers 4.
  • the shifter 10 is designed to shift the data sent from the temporary registers 4.
  • the microprogram ROM 12 stores information showing the sequence in which data are processed by the CPU 2.
  • the branch control unit 14 controls the branching of a microprogram.
  • the status control unit 16 includes flip-flop registers for storing the current status of the CPU 2 and a circuit for controlling the status of the flip-flop registers.
  • the common bus buffer/receiver 18 receives and supplies data through an external bus.
  • the timing generator & bus controller 22 controls transmission of data between the CPU 2 and a memory means or an input-output device and produces clock signals for defining the timing in which data are stored into the temporary registers 4 and general registers.
  • the special function unit 26 is used to, for example, expand a bit arrangement.
  • the shifter 10 is a conventional shift register. It shifts a 1-bit data at one cycle. Thus, to shift an m-bit data it would take m-cycle time. To shorten the time necessary for shifting data a new type of computer has been developed which has a shifter for shifting data at a high speed. Such a shifter is shown in FIG. 2.
  • FIG. 2 is a block circuit diagram of a shifter consisting of a plurality of data selectors (DS) which are cascade-connected.
  • an 8-bit data is supplied through input lines 28, a 3-bit data specifying an amount of shifting (i.e. m) is supplied through first control lines 30, and a 1-bit data specifying a "right” or “left” shift is supplied through a second control line 32. Both the 3-bit data and the 1-bit data are supplied to the data selectors DS.
  • the 8-bit data is shifted to the right by m bits and is obtained through output lines 34 at one cycle. If the 1-bit specifies "left” shift, the 8-bit data is shifted to the left by m bits and is obtained through output lines 36 at one cycle.
  • the contents of the register B are shifted to the right by m bits by the shifter, and the result is stored into the register B.
  • the leftmost m bits of the register B are therefore all 0s.
  • a logical OR operation is performed with the contents of the registers T and B, and the result of the operation is stored into the register B.
  • the above-mentioned five steps must be carried out to shift a 2n-bit data to the right by m bits. In other words, it takes a 5-cycle time to shift the data, by shifting an n-bit data at one cycle.
  • said 2n-bit data consisting of an n-bit data A and an n-bit data B are stored respectively into a register A and a register B, and another register T is used. More specifically, the following steps are carried out.
  • step 6 If m ⁇ n, the control goes to step 6. If m ⁇ n, the control goes to step 2.
  • the improvement comprises shifting means for shifting an n-bit input data by m bits (m ⁇ n) specified by the shifting amount data for producing a first output data or a second output data, where n and m are integers; data selector means for selectively outputting the first or second output data in accordance with the shift direction data; and temporary register means comprised of n bits for storing data which are not selected by said data selector means.
  • FIG. 1 is a schematic block circuit diagram of a conventional central processing unit including a shifter
  • FIG. 2 is a block diagram of a conventional shifter
  • FIG. 3 is a circuit diagram of a shift circuit, and embodiment of the present invention.
  • FIG. 4 shows a data selector used in the shift circuit shown in FIG. 3;
  • FIG. 5 is a circuit diagram of another shift circuit according to the present invention.
  • a shift circuit 38 of the present invention has a plurality of data selectors 40 (hereinafter called "DSs") which are cascade-connected in four stages.
  • An 8-bit data to be shifted is fed through a control line 42 to the DSs of the first stage.
  • Shifting amount data a binary data representing m bits by which to shift the input data, is fed through a control line 44 to the DSs of the second, third and fourth stages.
  • Shift direction data is fed through a control line 46 to the DSs of the first stage.
  • the shift direction data is logical "1"
  • the input data is shifted to the left.
  • the shift direction data is logical "0"
  • the input data is shifted to the right.
  • the shift circuit 38 further has 2n data output lines. These output lines are divided into two groups each consisting of n output lines. When the "right" operation is designated, the data output lines 48 of the first group are selected so that through them the input data may be outputted after it has been shifted to the right by m bits. When the "left" operation is designated, the data output lines 50 of the second group are selected so that through them the input data may be outputted after it has been shifted to the left by m bits.
  • each DS 40 receives data a and b both to be shifted. It also receives a select signal S and produces an output signal C. When the select signal S is logical "1", the DS 40 selects data a. When the select signal S is logical "0", it selects data b.
  • the shift circuit has two data selectors 52 and 54.
  • the data selector 52 is coupled to the output lines 48 of the first group and also to the output lines 50 of the second group.
  • the data selector 54 is coupled to the output lines 48 of the first group and also to the output lines 50 of the second group.
  • the data selectors 52 and 54 can select data which are supplied either through the output lines 48 or the output lines 50.
  • the DSs 52 and 54 are complementary and function in accordance with the input and output of an inverter 55. That is, when the DS 54 selects the output lines 48, the DS 52 selects the output lines 50. Conversely, when the DS 54 selects the output lines 50, the DS 52 selects the output lines 48.
  • the output of the DS 52 is supplied to a Q register, and the output of the DS 54 is coupled to one input terminal of an OR gate 56.
  • the Q register 58 holds the output from the DS 52 in response to a clock corresponding to one cycle of the shift circuit 38.
  • the output of the Q register 58 is fed to the other input terminal of the OR gate 56.
  • the Q register 58 can be cleared by a mechanism (not shown). As long as the Q register 58 remains clear, the input data is shifted by m bits (m ⁇ 8) and supplied through the output of the OR gate 56.
  • the shift circuit of FIG. 3 shifts n-bit data exactly in the same way and thus achieves exactly the same effects as does the shift circuit of FIG. 2. That is, it provides an m-bit shifted data (m ⁇ n) at one cycle. Unlike the circuit of FIG. 2, the shift circuit of FIG. 3 can shift a double length data at a higher speed, using the Q register 58.
  • step 1 the data A is fed through the input lines 42 from the register A (e.g. one of such general registers 24 as shown in FIG. 1).
  • the shifting amount data is fed through the control lines 44, and the logic "0" data is fed through the control line 46.
  • the DS 54 selects the output lines 48 of the first group, whereby the input data shifted to the right by m bits is supplied to the OR gate 56. Since. the Q register 58 has been cleared, the output of the OR gate 56, i.e. the shifted data A, is stored back into the register A.
  • the DS 52 selects the output lines 50 of the second group so that the data A shifted to the left by (n-m) bits is stored into the Q register 58 after the execution of step 1.
  • step 2 the data B is fed through the input lines 42 from the register B (e.g. one of the general registers 24).
  • the shifting amount data is fed through the control line 44, and the logical "0" data is fed through the control line 46.
  • the DS 54 therefore selects the output lines 48 of the first group.
  • the data A shifted to the left by (n-m) bits (thus, the right most m bits being of logic "0") is thus supplied to one input terminal of the OR gate 56 from the Q register 58. Simultaneously, to the other input terminal of the OR gate 56 there is supplied a data B shifted to the right by m bits (thus, the left most (n-m) bits being of logic "0").
  • the OR gate 56 outputs a data of which (n-m) bits are the data obtained by shifting the data B to the right by m bits and of which m bits are the data obtained by shifting the data B to the right by m bits.
  • the output of the OR gate 56 is stored into the register B, and thus completes the shifting of the double-length input data.
  • FIG. 5 shows another embodiment of the invention.
  • the shift circuit of FIG. 5 has a data selector 60 (hereinafter called "DS 60") and a double-length designation/rotation designation circuit 62.
  • the DS 60 selects either the output of a DS 54 or an n-bit data of which all bits are of logical "0".
  • the shift circuit of FIG. 5 further has a control line for supplying a shifting amount data representing m bits (n ⁇ m ⁇ 2n) by which to shift an input data.
  • the data A is shifted to the right (or the left) by m bits, and the result is stored into a register A.
  • the data B is shifted to the right (or the left) by m bits, and the result is stored into a register B.
  • the data A is rotate-shifted to the right (or the left) by m bits, and the result is stored into the register A.
  • the data B is rotate-shifted to the right (or the left) by m bits, and the result is stored into the Q register.
  • a small number of steps suffice to shift a double-length data and to rotate-shift a double-length data. Further, either data shifting operation can be effected at a higher speed than by the prior art shift circuit. If the shifting amount is smaller than the number of bits constituting the input data (that is, if m ⁇ n), a K times length data can be shifted by repeating steps 1 and 2 K times. Moreover, as mentioned above, a small number of steps suffice to rotate-shift a single-length data.
  • the data selectors which are cascade-connected are used as a shift circuit in the above-mentioned embodiments, use may be made of a shifter of a matrix type or other types.
  • the data selector stage is provided in an input stage.
  • the data selector stage may be provided in the output stage, thus achieving the same effect as in the embodiments of FIGS. 4 and 5.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Shift Register Type Memory (AREA)
US06/296,859 1980-09-09 1981-08-27 Shift circuit having a plurality of cascade-connected data selectors Expired - Fee Related US4472788A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP55-124091 1980-09-09
JP55124091A JPS5750049A (en) 1980-09-09 1980-09-09 Shifting circuit

Publications (1)

Publication Number Publication Date
US4472788A true US4472788A (en) 1984-09-18

Family

ID=14876697

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/296,859 Expired - Fee Related US4472788A (en) 1980-09-09 1981-08-27 Shift circuit having a plurality of cascade-connected data selectors

Country Status (5)

Country Link
US (1) US4472788A (fr)
EP (1) EP0047440B1 (fr)
JP (1) JPS5750049A (fr)
CA (1) CA1175154A (fr)
DE (1) DE3170846D1 (fr)

Cited By (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4583197A (en) * 1983-06-30 1986-04-15 International Business Machines Corporation Multi-stage pass transistor shifter/rotator
US4631703A (en) * 1982-04-22 1986-12-23 Tokyo Shibaura Denki Kabushiki Kaisha Shift circuit for double word length data
US4665538A (en) * 1984-07-24 1987-05-12 Nec Corporation Bidirectional barrel shift circuit
US4782457A (en) * 1986-08-18 1988-11-01 Texas Instruments Incorporated Barrel shifter using bit reversers and having automatic normalization
US4797852A (en) * 1986-02-03 1989-01-10 Intel Corporation Block shifter for graphics processor
US4831571A (en) * 1986-08-11 1989-05-16 Kabushiki Kaisha Toshiba Barrel shifter for rotating data with or without carry
US4839840A (en) * 1986-09-30 1989-06-13 Kabushiki Kaisha Toshiba Highly responsive barrel shifter
US4839839A (en) * 1986-09-26 1989-06-13 Kabushiki Kaisha Toshiba Barrel shifter including rotate operation
US4905178A (en) * 1986-09-19 1990-02-27 Performance Semiconductor Corporation Fast shifter method and structure
US4905175A (en) * 1988-12-05 1990-02-27 General Electric Company Digit-serial shifters constructed from basic cells
US4984189A (en) * 1985-04-03 1991-01-08 Nec Corporation Digital data processing circuit equipped with full bit string reverse control circuit and shifter to perform full or partial bit string reverse operation and data shift operation
US5020013A (en) * 1989-09-29 1991-05-28 Cyrix Corporation Bidirectional variable bit shifter
US5027300A (en) * 1989-12-20 1991-06-25 Bull Hn Information Systems Inc. Two level multiplexer circuit shifter apparatus
US5262971A (en) * 1990-05-15 1993-11-16 Kabushiki Kaisha Toshiba Bidirectional shifter
US5309382A (en) * 1992-10-01 1994-05-03 Silicon Graphics, Inc. Binary shifter
WO1994020900A1 (fr) * 1993-03-12 1994-09-15 Integrated Information Technology, Inc. Procede et processeurs de compression/decompression video
US5367700A (en) * 1991-01-31 1994-11-22 Sony Corporation System for multiplying digital input data in a multiplier circuit
US5379351A (en) * 1992-02-19 1995-01-03 Integrated Information Technology, Inc. Video compression/decompression processing and processors
US5379240A (en) * 1993-03-08 1995-01-03 Cyrix Corporation Shifter/rotator with preconditioned data
US5553010A (en) * 1991-03-06 1996-09-03 Fujitsu Limited Data shifting circuit capable of an original data width rotation and a double data width rotation
US5559730A (en) * 1994-02-18 1996-09-24 Matsushita Electric Industrial Co., Ltd. Shift operation unit and shift operation method
US5619722A (en) * 1994-01-18 1997-04-08 Teramar Group, Inc. Addressable communication port expander
US5627776A (en) * 1991-01-31 1997-05-06 Sony Corporation Data processing circuit
US5844825A (en) * 1996-09-03 1998-12-01 Wang; Song-Tine Bidirectional shifter circuit
US6006244A (en) * 1997-12-19 1999-12-21 Advanced Micro Devices, Inc. Circuit for shifting or rotating operands of multiple size
US6035310A (en) * 1997-12-19 2000-03-07 Advanced Micro Devices, Inc. Method and circuit for performing a shift arithmetic right operation
US6122651A (en) * 1998-04-08 2000-09-19 Advanced Micro Devices, Inc. Method and apparatus for performing overshifted rotate through carry instructions by shifting in opposite directions
US6393446B1 (en) * 1999-06-30 2002-05-21 International Business Machines Corporation 32-bit and 64-bit dual mode rotator
US6552567B1 (en) 2001-09-28 2003-04-22 Microchip Technology Incorporated Functional pathway configuration at a system/IC interface
US6552625B2 (en) 2001-06-01 2003-04-22 Microchip Technology Inc. Processor with pulse width modulation generator with fault input prioritization
US6601160B2 (en) 2001-06-01 2003-07-29 Microchip Technology Incorporated Dynamically reconfigurable data space
US6604169B2 (en) 2001-06-01 2003-08-05 Microchip Technology Incorporated Modulo addressing based on absolute offset
US6675182B1 (en) * 2000-08-25 2004-01-06 International Business Machines Corporation Method and apparatus for performing rotate operations using cascaded multiplexers
US20040014427A1 (en) * 2001-07-20 2004-01-22 Amit Gur Method and apparatus for transferring data between a source register and a destination register
US20040021483A1 (en) * 2001-09-28 2004-02-05 Brian Boles Functional pathway configuration at a system/IC interface
US6728856B2 (en) 2001-06-01 2004-04-27 Microchip Technology Incorporated Modified Harvard architecture processor having program memory space mapped to data memory space
US6934728B2 (en) 2001-06-01 2005-08-23 Microchip Technology Incorporated Euclidean distance instructions
US6937084B2 (en) 2001-06-01 2005-08-30 Microchip Technology Incorporated Processor with dual-deadtime pulse width modulation generator
US6952711B2 (en) 2001-06-01 2005-10-04 Microchip Technology Incorporated Maximally negative signed fractional number multiplication
US20050238098A1 (en) * 1992-02-19 2005-10-27 8X8, Inc. Video data processing and processor arrangements
US6975679B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Configuration fuses for setting PWM options
US6976158B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Repeat instruction with interrupt
US6985986B2 (en) 2001-06-01 2006-01-10 Microchip Technology Incorporated Variable cycle interrupt disabling
US7003543B2 (en) 2001-06-01 2006-02-21 Microchip Technology Incorporated Sticky z bit
US7007172B2 (en) 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US7020788B2 (en) 2001-06-01 2006-03-28 Microchip Technology Incorporated Reduced power option
US7467178B2 (en) 2001-06-01 2008-12-16 Microchip Technology Incorporated Dual mode arithmetic saturation processing
US7966480B2 (en) 2001-06-01 2011-06-21 Microchip Technology Incorporated Register pointer trap to prevent errors due to an invalid pointer value in a register
US20130018933A1 (en) * 2010-03-31 2013-01-17 Telefonaktiebolaget Lm Ericsson (Publ) Data Shifter and Control Method Thereof, Multiplexer, Data Sifter, and Data Sorter

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5995647A (ja) * 1982-11-24 1984-06-01 Nec Corp 可変ビツト数シフタ
JPH0736149B2 (ja) * 1984-02-10 1995-04-19 株式会社日立製作所 シフトフラグ生成回路
JPH0721757B2 (ja) * 1984-12-19 1995-03-08 株式会社日立製作所 情報処理装置
JPS62143130A (ja) * 1985-12-17 1987-06-26 Mitsubishi Electric Corp 中央処理装置
CA1265254A (fr) * 1986-02-24 1990-01-30 Thomas Ralph Woodward Mecanisme de decalage controle par un programme pour unite programmable a largeurs variables de trajet de donnees
JPS6398729A (ja) * 1986-10-15 1988-04-30 Fujitsu Ltd バレルシフタ
JPS63284636A (ja) * 1987-05-18 1988-11-21 Matsushita Electric Ind Co Ltd シフト回路
US4931970A (en) * 1989-01-13 1990-06-05 International Business Machines Corporation Apparatus for determining if there is a loss of data during a shift operation
WO1993015460A2 (fr) * 1992-01-24 1993-08-05 Digital Equipment Corporation Circuit de parite et de normalisation haute vitesse des bus de donnees pour un systeme de traitement en parallele d'un grand nombre d'instructions
EP0800133A1 (fr) * 1992-01-24 1997-10-08 Digital Equipment Corporation Circuit de parité et de normalisation haute vitesse des bus de données pour un système de traitement en parallèle d'un grand nombre d'instructions
JPH07281870A (ja) * 1994-02-18 1995-10-27 Matsushita Electric Ind Co Ltd シフト演算装置及びシフト演算方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3810115A (en) * 1973-02-05 1974-05-07 Honeywell Inf Systems Position scaler (shifter) for computer arithmetic unit
US3961750A (en) * 1974-04-05 1976-06-08 Signetics Corporation Expandable parallel binary shifter/rotator
US4122534A (en) * 1977-06-17 1978-10-24 Northern Telecom Limited Parallel bidirectional shifter
US4345316A (en) * 1978-06-29 1982-08-17 Fujitsu Limited Shift arithmetic device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3610903A (en) * 1969-01-08 1971-10-05 Burroughs Corp Electronic barrel switch for data shifting
US3781819A (en) * 1971-10-08 1973-12-25 Ibm Shift unit for variable data widths

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3810115A (en) * 1973-02-05 1974-05-07 Honeywell Inf Systems Position scaler (shifter) for computer arithmetic unit
US3961750A (en) * 1974-04-05 1976-06-08 Signetics Corporation Expandable parallel binary shifter/rotator
US4122534A (en) * 1977-06-17 1978-10-24 Northern Telecom Limited Parallel bidirectional shifter
US4345316A (en) * 1978-06-29 1982-08-17 Fujitsu Limited Shift arithmetic device

Non-Patent Citations (7)

* Cited by examiner, † Cited by third party
Title
Gersbach "Algebraic/Logical Shift Matrix" IBM Tech. Disc. Bulletin vol. 23, No. 1, Jun. 1980 pp. 120-122.
Gersbach "High-Speed Shifter Array" IBM Tech. Disclosure Bulletin vol. 21, No. 4, Sep. 1978 pp. 1379-1380.
Gersbach Algebraic/Logical Shift Matrix IBM Tech. Disc. Bulletin vol. 23, No. 1, Jun. 1980 pp. 120 122. *
Gersbach High Speed Shifter Array IBM Tech. Disclosure Bulletin vol. 21, No. 4, Sep. 1978 pp. 1379 1380. *
Houghtalen Microprocessor with External Shift Capability IBM Tech. Disc. Bulletin vol. 22, No. 7 Dec. 1979 p. 2714. *
Weinberger, "Arithmetic Shift" IBM Tech. Disclosure Bulletin vol. 19, No. 1, Jun. 1976 pp. 207-216.
Weinberger, Arithmetic Shift IBM Tech. Disclosure Bulletin vol. 19, No. 1, Jun. 1976 pp. 207 216. *

Cited By (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4631703A (en) * 1982-04-22 1986-12-23 Tokyo Shibaura Denki Kabushiki Kaisha Shift circuit for double word length data
US4583197A (en) * 1983-06-30 1986-04-15 International Business Machines Corporation Multi-stage pass transistor shifter/rotator
US4665538A (en) * 1984-07-24 1987-05-12 Nec Corporation Bidirectional barrel shift circuit
US4984189A (en) * 1985-04-03 1991-01-08 Nec Corporation Digital data processing circuit equipped with full bit string reverse control circuit and shifter to perform full or partial bit string reverse operation and data shift operation
US4797852A (en) * 1986-02-03 1989-01-10 Intel Corporation Block shifter for graphics processor
US4831571A (en) * 1986-08-11 1989-05-16 Kabushiki Kaisha Toshiba Barrel shifter for rotating data with or without carry
US4782457A (en) * 1986-08-18 1988-11-01 Texas Instruments Incorporated Barrel shifter using bit reversers and having automatic normalization
US4905178A (en) * 1986-09-19 1990-02-27 Performance Semiconductor Corporation Fast shifter method and structure
US4839839A (en) * 1986-09-26 1989-06-13 Kabushiki Kaisha Toshiba Barrel shifter including rotate operation
US4839840A (en) * 1986-09-30 1989-06-13 Kabushiki Kaisha Toshiba Highly responsive barrel shifter
US4905175A (en) * 1988-12-05 1990-02-27 General Electric Company Digit-serial shifters constructed from basic cells
US5020013A (en) * 1989-09-29 1991-05-28 Cyrix Corporation Bidirectional variable bit shifter
US5027300A (en) * 1989-12-20 1991-06-25 Bull Hn Information Systems Inc. Two level multiplexer circuit shifter apparatus
US5262971A (en) * 1990-05-15 1993-11-16 Kabushiki Kaisha Toshiba Bidirectional shifter
US5367700A (en) * 1991-01-31 1994-11-22 Sony Corporation System for multiplying digital input data in a multiplier circuit
US5627776A (en) * 1991-01-31 1997-05-06 Sony Corporation Data processing circuit
US5923578A (en) * 1991-01-31 1999-07-13 Sony Corporation Data processing circuit
US5553010A (en) * 1991-03-06 1996-09-03 Fujitsu Limited Data shifting circuit capable of an original data width rotation and a double data width rotation
US20050238098A1 (en) * 1992-02-19 2005-10-27 8X8, Inc. Video data processing and processor arrangements
US20060013316A1 (en) * 1992-02-19 2006-01-19 8X8, Inc. Video data processing and processor arrangements
US5379351A (en) * 1992-02-19 1995-01-03 Integrated Information Technology, Inc. Video compression/decompression processing and processors
US5790712A (en) * 1992-02-19 1998-08-04 8×8, Inc. Video compression/decompression processing and processors
US5309382A (en) * 1992-10-01 1994-05-03 Silicon Graphics, Inc. Binary shifter
US5379240A (en) * 1993-03-08 1995-01-03 Cyrix Corporation Shifter/rotator with preconditioned data
WO1994020900A1 (fr) * 1993-03-12 1994-09-15 Integrated Information Technology, Inc. Procede et processeurs de compression/decompression video
US5619722A (en) * 1994-01-18 1997-04-08 Teramar Group, Inc. Addressable communication port expander
US5559730A (en) * 1994-02-18 1996-09-24 Matsushita Electric Industrial Co., Ltd. Shift operation unit and shift operation method
US5844825A (en) * 1996-09-03 1998-12-01 Wang; Song-Tine Bidirectional shifter circuit
US6006244A (en) * 1997-12-19 1999-12-21 Advanced Micro Devices, Inc. Circuit for shifting or rotating operands of multiple size
US6035310A (en) * 1997-12-19 2000-03-07 Advanced Micro Devices, Inc. Method and circuit for performing a shift arithmetic right operation
US6122651A (en) * 1998-04-08 2000-09-19 Advanced Micro Devices, Inc. Method and apparatus for performing overshifted rotate through carry instructions by shifting in opposite directions
US6393446B1 (en) * 1999-06-30 2002-05-21 International Business Machines Corporation 32-bit and 64-bit dual mode rotator
US6675182B1 (en) * 2000-08-25 2004-01-06 International Business Machines Corporation Method and apparatus for performing rotate operations using cascaded multiplexers
US7003543B2 (en) 2001-06-01 2006-02-21 Microchip Technology Incorporated Sticky z bit
US6976158B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Repeat instruction with interrupt
US7966480B2 (en) 2001-06-01 2011-06-21 Microchip Technology Incorporated Register pointer trap to prevent errors due to an invalid pointer value in a register
US7467178B2 (en) 2001-06-01 2008-12-16 Microchip Technology Incorporated Dual mode arithmetic saturation processing
US6728856B2 (en) 2001-06-01 2004-04-27 Microchip Technology Incorporated Modified Harvard architecture processor having program memory space mapped to data memory space
US6934728B2 (en) 2001-06-01 2005-08-23 Microchip Technology Incorporated Euclidean distance instructions
US6937084B2 (en) 2001-06-01 2005-08-30 Microchip Technology Incorporated Processor with dual-deadtime pulse width modulation generator
US7243372B2 (en) 2001-06-01 2007-07-10 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US6952711B2 (en) 2001-06-01 2005-10-04 Microchip Technology Incorporated Maximally negative signed fractional number multiplication
US6601160B2 (en) 2001-06-01 2003-07-29 Microchip Technology Incorporated Dynamically reconfigurable data space
US6975679B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Configuration fuses for setting PWM options
US6604169B2 (en) 2001-06-01 2003-08-05 Microchip Technology Incorporated Modulo addressing based on absolute offset
US6985986B2 (en) 2001-06-01 2006-01-10 Microchip Technology Incorporated Variable cycle interrupt disabling
US6552625B2 (en) 2001-06-01 2003-04-22 Microchip Technology Inc. Processor with pulse width modulation generator with fault input prioritization
US7020788B2 (en) 2001-06-01 2006-03-28 Microchip Technology Incorporated Reduced power option
US7007172B2 (en) 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US6944755B2 (en) * 2001-07-20 2005-09-13 Freescale Semiconductor, Inc. Method and apparatus for extracting a portion of data in a source register and arranging it on one side of a destination register
US20040014427A1 (en) * 2001-07-20 2004-01-22 Amit Gur Method and apparatus for transferring data between a source register and a destination register
US6552567B1 (en) 2001-09-28 2003-04-22 Microchip Technology Incorporated Functional pathway configuration at a system/IC interface
US20040021483A1 (en) * 2001-09-28 2004-02-05 Brian Boles Functional pathway configuration at a system/IC interface
US20130018933A1 (en) * 2010-03-31 2013-01-17 Telefonaktiebolaget Lm Ericsson (Publ) Data Shifter and Control Method Thereof, Multiplexer, Data Sifter, and Data Sorter

Also Published As

Publication number Publication date
CA1175154A (fr) 1984-09-25
DE3170846D1 (en) 1985-07-11
EP0047440A1 (fr) 1982-03-17
EP0047440B1 (fr) 1985-06-05
JPS628817B2 (fr) 1987-02-25
JPS5750049A (en) 1982-03-24

Similar Documents

Publication Publication Date Title
US4472788A (en) Shift circuit having a plurality of cascade-connected data selectors
US4085447A (en) Right justified mask transfer apparatus
US4761755A (en) Data processing system and method having an improved arithmetic unit
EP0161089B1 (fr) Multiplicateur à double précision
US5477543A (en) Structure and method for shifting and reordering a plurality of data bytes
US5146577A (en) Serial data circuit with randomly-accessed registers of different bit length
US4984189A (en) Digital data processing circuit equipped with full bit string reverse control circuit and shifter to perform full or partial bit string reverse operation and data shift operation
US4745569A (en) Decimal multiplier device and method therefor
EP0127007A2 (fr) Dispositif d'interface de traitement de données
KR0177985B1 (ko) 프로세서의 벡터 데이터 조정 장치
GB2119976A (en) Shift circuit
US4128872A (en) High speed data shifter array
US5010509A (en) Accumulator for complex numbers
US5465222A (en) Barrel shifter or multiply/divide IC structure
US5192882A (en) Synchronization circuit for parallel processing
US20050256996A1 (en) Register read circuit using the remainders of modulo of a register number by the number of register sub-banks
EP0825528A2 (fr) Processeur de signaux numériques
US6317771B1 (en) Method and apparatus for performing digital division
US5912831A (en) Process and system for adding or substracting symbols in any base without converting to a common base
JP3455828B2 (ja) ビットシフト回路
US5307474A (en) Apparatus and method for processing literal operand computer instructions
JPH10312356A (ja) データ転送装置
JP2003337694A (ja) シフト回路
EP0448097A2 (fr) Circuit de décalage arithmétique
JPH07120254B2 (ja) シフタ

Legal Events

Date Code Title Description
AS Assignment

Owner name: TOKYO SHIBAURA DENKI KABUSHIKI KAISHA 72 HORIKAWA-

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:YAMAZAKI, ISAMU;REEL/FRAME:004275/0452

Effective date: 19810810

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
FP Lapsed due to failure to pay maintenance fee

Effective date: 19960918

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362