US4002851A - Telecommunication system controlled by stored program instructions - Google Patents

Telecommunication system controlled by stored program instructions Download PDF

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Publication number
US4002851A
US4002851A US05/578,734 US57873475A US4002851A US 4002851 A US4002851 A US 4002851A US 57873475 A US57873475 A US 57873475A US 4002851 A US4002851 A US 4002851A
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register
instruction
address
registers
phase
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US05/578,734
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English (en)
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Lars-Ake Evert Larsson
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Telefonaktiebolaget LM Ericsson AB
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Telefonaktiebolaget LM Ericsson AB
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/226—Microinstruction function, e.g. input/output microinstruction; diagnostic microinstruction; microinstruction format
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme

Definitions

  • the present invention relates to a SPC (Stored Program Controlled) telecommunication system in which test points, operating points and data-bus connected data storage registers are controlled by access signals which are produced in response to control instructions identified by means of instruction addresses wherein the execution of a control function consisting of a number control instructions is initiated by a start instruction address associated with the first control instruction of the control function, the start instruction address number being stored in one of the data storage registers of the telecommunication system.
  • SPC Stored Program Controlled
  • Known SPC telecommunication systems consist of an exchange and a computer.
  • the computer has a memory part and a processor.
  • the memory part comprises a program store, a data store and registers forming a transfer unit which stores the operation instructions received from the computer for transfer to the exchange and which stores state information received from the exchange for transfer to the computer respectively.
  • the processor which controls the processing of instructions stored in the program store comprises a number of data storage registers, an arithmetic unit and a control unit which includes a microinstruction generator with a microprogram store.
  • the present invention the characteristics of which appear from the claims proceeds from an arbitrary automatic exchange which is controlled by means of control organs as identifiers, code receivers, code senders and markers.
  • An object of the invention is to achieve a SPC system without use of a computer program language so that as far as possible ineffective instructions are avoided. This object is achieved by inserting in the function units of the exchange simple computer technical aid means without the need to change existing approved control principles in connection with a concentration of the control of the system by means of a computer.
  • Such computer technical means comprise data storage registers and logical arrangements controlled by time phase signals for producing access signals in order to address and activate the data storage registers which are interconnected via data-bus operating points and test points of the system.
  • FIG. 1 shows a block diagram for a SPC system according to the invention
  • FIG. 2 shows how the marker in a SPC exchange according to the invention carries out a path selection, as a control function example.
  • a telecommunication system EX is indicated by means of its operating points OP, test points TP and data storage registers REG.
  • An example of an operating point is the one end of a relay winding. If a voltage is supplied this winding end the relay is energized and this constitutes an operating step in the telecommunication system.
  • a bistable flip-flop for example, the output of which is connected to the winding end and the input of which in this case constitutes the operating point.
  • An example of a test point is a subscriber's line whose loop resistance is high or low. If bistable flip-flops are used, their output sides are applied as test points.
  • the operating state of a group selector of the telecommunication system is very advantageously indicated by means of a register R1 wherein the binary contents of each bit position of the register indicates the busy and idle state, respectively, of an associated path through the selector.
  • the installation of further registers R2 in order to, for example, transfer for further evaluation the state of the group selector to another function unit of the telecommunication system such as a marker is not difficult for a normal telecommunication expert even if he is not a data processing expert.
  • a data-bus DB is shown which interconnects all the registers other.
  • each operating point, each test point and each register can be accessed by means of an associated access signal as which is transferred to a corresponding access gate.
  • access signals are sent from an access signal generator ASG. It will be assumed that by means of the access gates a voltage + necessary for operation is supplied to the operating points, that the existing state of the accessed test point is connected to a common output 0 of the telecommunication system, and that the access signals of the registers distinguish whether the access signal controls the data reception or the data transmission by the register.
  • the control by means of a stored program is further achieved by a number of instruction registers IR and at least one instruction address register IAR with associated access gates.
  • Each instruction register includes in binary coded form a control instruction so that the control of an arbitrarily complicated system can in principle be handled with three different kinds of instructions, namely test instructions, operating instructions and transport instructions.
  • test instruction is used to access a test point TPN for the above mentioned transfer of the binary state to the common output 0.
  • a test instruction comprises the address of the test point TPN whose state will be tested.
  • An operating instruction is used to access and operate respectively, an operating point.
  • an operating instruction at least includes the address of the concerned operating point OPN.
  • they furthermore, comprise the address of a test point TPN.
  • the modification consists in that the concerned operating point remains activated until the involved test point changes to a determined binary state.
  • a transport or transfer instruction is used to transport transfer data from one register to another via the data bus DB and associated access gates.
  • a normal transport instruction includes the address of the sending and the address of the receiving register.
  • registers R2 which are accessed because of the one instruction for reception and because of the other instruction for sending data. If, however, a transport instruction addresses one of the registers R1 which store system states, this register is always only for sending data to the data bus DB. Also for the instruction registers data reception from data bus DB is impossible therefore, these registers are only read only devices.
  • a transport instruction is used which includes partly the data d which are to be transported and partly the address a for the receiving register.
  • the instruction registers IR and the instruction address register IAR with associated access gates are connected to data-bus DB.
  • the instruction registers IR and the instruction address register IAR are different from other registers of the telecommunication system because their contents are transferred not only to data-bus DB for transport to another register but, moreover, to the access signal generator ASG.
  • the instruction address register IAR is arranged only to store an instruction address i.e., a number which is associated with one of the instruction registers IAR.
  • the access signal generator ASG decodes the instruction address numbers and produces from them the access signals asi for the address parts a stored in the instruction registers.
  • the instruction address register distinguishes IAR is different from all other registers in that it is an up counter that it is provided with a stepping forward input ST whose activation causes that the stored address number be unit incremented.
  • Each instruction is processed step-by-step, the dividing up of a processing cycle into at least three time phases, a beginning-, a middle-, and an end phase is controlled by means of a phase generator PG, which sends corresponding time phase signals ⁇ 1, ⁇ 2, ⁇ 3 to the access signal generator ASG.
  • the access signal generator ASG includes a first logic unit L1 which decodes the contents of the instruction address register IAR during the beginning phases and transmits during the other time phases the access signal asi for the instruction register IR identified by means of respective instruction address number. In this manner the access signal generator ASG has to its disposal during the other time phases in respective processing cycles the address contents of the accessed instruction register.
  • the access signals as for activating the operating and test points and for connecting all the registers including the instruction registers and the instruction address register to the data-bus DB are produced by means of further logic units of the access signal generator ASG during suitable time phases. Since it is necessary to count with building up processes it is advantageous to access the registers which receive data first during the end phases. On the contrary the registers which will send data to said data-bus and the operating and test points are accessed as quick as possible.
  • the operation of the access signal generator is described more in detail in the following with help of an embodiment shown in FIG. 2.
  • the conversion of the addresses a received from the instruction registers to the access signals as for the sake of simplicity is indicated only by means of a dotted line.
  • the time phase control is indicated by means of a gate G1 activated during the beginning phases.
  • the instruction address numbers are written in an intermediate register R3 whose output is connected to an address decoder DEC1.
  • the time phase control is indicated for the instruction address register by means of a logic arrangement L3 which is activated for transferring data to data-bus DB during the middle and the end phases and for reception of data from said data-bus during the end phases.
  • the execution of a control function which consists of a number of control instructions in principle proceeds in the following manner:
  • the phase generator PG sends no time phase signals and the instruction address register IAR includes the address number for a transparent instruction, a so-called opening instruction which comprises as sender address the address of a determined register in the telecommunication system, a so-called start register SR, and as receiver address the address of the instruction address register IAR.
  • the opening instruction which comprises as sender address the address of a determined register in the telecommunication system, a so-called start register SR, and as receiver address the address of the instruction address register IAR.
  • phase generators with associated instruction registers, instruction address registers and access signal generators, if the invention is to be utilized in order to control all functions of a telecommunication system.
  • each phase generator is allotted unchangeable the processing of determined control functions which affect a limited number of operating points and test points.
  • a suitable utilization of the registers REG makes the cooperation of the phase generators possible.
  • a start register cooperating with a first phase generator is also associated with the registers cooperating with a second phase generator.
  • the second phase generator has, for example, finished a control function with a data transport to this start register, a control function is ordered, the execution of which is controlled by the first phase generator.
  • each telecommunication system irrespective of the use of data processing aids at the execution of all control functions or only a part thereof, at least one control function, the execution of which is demanded by an operation state change in the telecommunication system. If, for example, a subscriber changes the loop state of its line an instruction address number is thereby written into a start register, by means of the address number the first control instruction in the control function is accessed in order to scan all the lines.
  • An address number stored in the start register SR releases the start of the phase generator PG.
  • the above mentioned opening instruction is accessed wherein the address number stored in the start register SR is transported through the data-bus DBI to the instruction address register IAR, where the address number is written during the end phase of the first processing cycle.
  • the first control instruction of the ordered control function is accessed at the beginning of the following processing cycle. It is assumed that this first control instruction concerns the operation of an operating point which consequently according to the above description is accessed and activated by the access signal generator ASG.
  • the second control instruction in the control function initiated in this way is accessed by means of the above mentioned stepping input ST of the instruction address register IAR, which input is activated by means of an OR-gate or logic unit L2 during the middle phase in each processing cycle.
  • instruction addresses are obtained, the address numbers of the instruction addresses being unit incremented, and therewith access signals asi are obtained for sequential control instructions.
  • an increment of the address number was carried out, however, this increment was removed at the reception of the instruction address number belonging to the first control instruction during the respective end phase.
  • unit incrementing of the address number is negated when the instruction address register is accessed as a receiving register during a transport instruction.
  • a transport instruction is accessed by means of a normal address number incrementing during the middle phases so that, due to the transport instruction, the instruction address register receives, during the end phase, an instruction address number which is one unit less than the address number of the above mentioned opening instruction and which is associated with an operating instruction, a so-called stop instruction.
  • the stop instruction an operating point OP1 is accessed during the end phase the activation of which stops the phase generator PG.
  • the instruction address register IAR the address number associated with the opening instruction was obtained.
  • FIG. 2 By means of FIG. 2 and by means of the embodiment that a marker M in an automatic exchange there will be described the execution of a path selection.
  • a marker two registers R4 and R5 As parts of the marker two registers R4 and R5, a clock CL, a counter C, some gates and a shift register SHR are shown, the cooperation of which will be explained more in detail below.
  • the start register SR, the instruction address register IAR and the phase generator PG are already described with respect to FIG. 1. Instead of a central data-bus the individual connections as DB1, DB2, . . . , etc. data transports are shown in FIG. 2 because in this way, it is easier to explain the execution of the path selection control function.
  • the individual instruction registers there is provided a read only memory ROM equipped with an address decoder DEC1 and a read register RR.
  • the construction of the access signal generator ASG depends on the coding form which is chosen for the immediately accessable control instructions stored in the read only memory.
  • the instructions consist of an operator and a variable part op and va respectively.
  • the variable part includes the addresses for the registers, the test and operating points which are to be controlled and data which are to be transported to one of the registers, respectively.
  • the instructions which access the instruction address register IAR either for data reception or data sending are ineffective because they do not immediately produce proper control of the telecommunication system.
  • the operator part in such ineffective transport instructions is associated in the embodiment showed in FIG. 2 with individual operating code numbers.
  • the code numbers 4 and 5 respectively are used for the data transport from the start register SR and from the variable part of the read register RR, respectively, to the instruction address register IAR.
  • the access signal generator ASG comprises: for decoding the code number or op codes, an operator decoder DEC2 which is connected to the operator part of the read register RR; and, for decoding the addresses of the register, test- and operating points of the telecommunication system, a sending, a receiving, an operating and a test decoder DEC3 to DEC6 which, through associated activating gates, are connected to the phase generator PG, to the operator decoder and to the variable part of the read register RR.
  • the one variable half part comprising n bit positions is for the sending addresses sa, and the other likewise n positions comprising the other half is for the receiving addresses ra.
  • the insertion of the code number 5 means that the instruction address register IAR as well as the start register SR comprise 2 ⁇ n bit positions and that it is possible to execute control functions with altogether 2 2n control instructions when using a sufficiently large read only memory and therewith to control data transfers betweem 2 n registers in the telecommunication system.
  • variable parts of test instructions with the code number 3, for example the one with the address number 23 in the read only memory include only test point addresses ta, so the existing bit positions per se allow an access of 2 2n test points.
  • the variable parts of the operating instructions with the code number 2 for example the one with the address number 25 in the read only memory, are only used for the operating point addresses oa and per se there is also access possibility for 2 2n operating points.
  • FIG. 2 it is, however, possible to make the processing cycles of the operating instructions independent of the time phase singals of the phase generator PG.
  • phase generator PG with a signal extension input SEL and with such operating instructions with code number 2, for example the one with the address number 26 in the read only memory, having one variable part comprising the operating point address oa which is decoded by the operating decoder DEC5, and another variable parts comprising the address ta2 of a suitable test point TP2 which address is decoded by the test decoder DEC6, and which test point changes its binary state when the operating process is finished.
  • An activation of of the signal extension input SEL by logic unit L5 in response to the above stated conditions resulting in an extension of the time phase signal just transmitted from the phase generator until the binary state of the likewise accessed test point TP2 can change.
  • modified operating instructions include two addresses, by one access signal generator with access signals produced for only 2 n operating points and for only 2 n test points.
  • the registers R4 and R5 of the marker cooperate respectivey with an input selector group an output selector group of the selector groups SG comprising a number of similar groups and take part at the setting up of a new telephone connection. It is assumed that at both the input side and at the output side it is already been examined which paths in a group of for example 12 paths for the new connection may be switched in the selector groups without disturbing already existing connections. Between the concerned input and output selector groups, all paths in a number of path groups are defined by means of fast installed links.
  • the read outlets of said two registers are through an AND-gate arrangement G3 connected to the write inlets of the shift register SHR.
  • an AND-function is carried out so that only those positions of the shift register SR are activated which correspond to coincidentally activated positions of registers R4 and R5.
  • the bit positions are activated which belong to the links with the numbers 5 and 8.
  • the counter C which is provided with a zero input 0 for zerosetting the contents of the counter, counts the shift pulses which are fed to the shift input of the shift register SR.
  • the zero input of the counter forms an operating point OP2.
  • a first test point TP1 indicates by means of the output of an OR-gate G4 connected to the bit positions of the shift register if at least one of the bit positions is activated.
  • a second test point TP2 is formed of the bit position in the shift register to which position the contents of the other positions are shifted sequentially by the shift pulses which are produced by the clock CL and are received at the shift input.
  • an operating point OP3 i.e. the counter C and the shift register SHR, obtains shift pulses until the second test point TP2 is activated. Therefore according to the assumed example there will be 5 shift pulses.
  • the counter C holds the number of the link through which the new connection is to be switched.
  • OR-gate G6 is, via a blocking gate G7, connected to a start input on of the phase generator PG having an output w which is activated as long as the time phase signals are transmitted and which is connected to an inverting input of the blocking gate.
  • phase generator PG receives only a short start pulse and it is impossible to open a new control function before the just processed control function is finished.
  • the outputs of the operating decoder DEC2 and the operating parts of the accessed control instructions are denoted by corresponding operating code numbers 1 to 5
  • the outputs of the address decoder DEC1 are denoted by the instruction address numbers 0, 22 to 27, x and max applied in the example.
  • the contents of the instruction address register is unit incremented to 23, the code number 1 is decoded, and by means of the sending address sa stored in the variable part of the read register RR and decoded by the sending decoder DEC3 the register R4 of the marker M is activated to send the binary content value 100001001001.
  • the shift register SHR of the marker M is activated to receive the binary value 000001001000.
  • variable part of the read register i.e. the instruction address number max having binary 1 in all bit positions, is transported to the instruction address register IAR.
  • the operating point OP1 is activated.
  • step 23 If all the bit positions of the shift register SHR had been unactivated in the step 23, i.e. if no path within the examined path group had been concerned with the new circuit, the stepping input of the instruction address register would not be activated in step 33 and one obtains:
  • variable part of the read register i.e. the address number x for an instruction which opens a new, however, here not described instruction sequence, is transferred to the instruction address register.
  • control function the address of the selected link is calculated by adding the link number obtained in the counter to an address number which is associated with the link having zero as its link number.
  • the path selection includes such adding function by charging the counter, for example, from the selector groups SG, with the address to the link with the number zero, the counter at the end of the path selection containing the address to the link through which the new circuit is to be switched.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Electrotherapy Devices (AREA)
  • Circuits Of Receivers In General (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
US05/578,734 1974-06-06 1975-05-19 Telecommunication system controlled by stored program instructions Expired - Lifetime US4002851A (en)

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SE7407431A SE376354B (hu) 1974-06-06 1974-06-06

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JP (1) JPS5818836B2 (hu)
AU (1) AU497191B2 (hu)
BE (1) BE829976A (hu)
BR (1) BR7503523A (hu)
CA (1) CA1052463A (hu)
DK (1) DK138298B (hu)
EG (1) EG13379A (hu)
ES (1) ES438259A1 (hu)
FI (1) FI58418C (hu)
FR (1) FR2274190A1 (hu)
GB (1) GB1462150A (hu)
HU (1) HU171888B (hu)
IN (1) IN142560B (hu)
MY (1) MY7800103A (hu)
NL (1) NL7506750A (hu)
NO (1) NO137803C (hu)
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471526A (en) * 1994-02-28 1995-11-28 Telefonaktiebolaget L M Ericsson (Publ.) Tracing with keys and locks on a telecommunication network
US20060020413A1 (en) * 2004-07-26 2006-01-26 Septon Daven W Methods and apparatus for providing automated test equipment with a means to jump and return in a test program
CN113254079A (zh) * 2021-06-28 2021-08-13 广东省新一代通信与网络创新研究院 一种用于实现自增指令的方法及系统

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4487630A (en) * 1982-10-25 1984-12-11 Cabot Corporation Wear-resistant stainless steel
JPS6130454A (ja) * 1984-07-21 1986-02-12 Motoyasu Tanaka 自動車居住空間の環境改善方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3578918A (en) * 1968-08-08 1971-05-18 Pierre M Lucas Computer controlled switching system using flip-flops for control of repetitive operations
US3885106A (en) * 1972-09-25 1975-05-20 Tele Resources Inc Telephone exchange having permanent memory for operating instructions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3578918A (en) * 1968-08-08 1971-05-18 Pierre M Lucas Computer controlled switching system using flip-flops for control of repetitive operations
US3885106A (en) * 1972-09-25 1975-05-20 Tele Resources Inc Telephone exchange having permanent memory for operating instructions

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471526A (en) * 1994-02-28 1995-11-28 Telefonaktiebolaget L M Ericsson (Publ.) Tracing with keys and locks on a telecommunication network
US5594904A (en) * 1994-02-28 1997-01-14 Telefonaktiebolaget L M Ericsson Tracing with keys and locks
US20060020413A1 (en) * 2004-07-26 2006-01-26 Septon Daven W Methods and apparatus for providing automated test equipment with a means to jump and return in a test program
CN113254079A (zh) * 2021-06-28 2021-08-13 广东省新一代通信与网络创新研究院 一种用于实现自增指令的方法及系统
CN113254079B (zh) * 2021-06-28 2021-10-01 广东省新一代通信与网络创新研究院 一种用于实现自增指令的方法及系统

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CA1052463A (en) 1979-04-10
NL7506750A (nl) 1975-12-09
IN142560B (hu) 1977-07-30
MY7800103A (en) 1978-12-31
YU144075A (en) 1981-02-28
ES438259A1 (es) 1977-04-16
AU8168575A (en) 1976-12-02
BR7503523A (pt) 1976-05-25
EG13379A (en) 1981-03-31
YU36091B (en) 1981-11-13
BE829976A (fr) 1975-10-01
JPS518808A (en) 1976-01-24
FI58418C (fi) 1981-01-12
FR2274190A1 (fr) 1976-01-02
NO137803B (no) 1978-01-16
DK138298C (hu) 1979-01-22
FI751555A (hu) 1975-12-07
JPS5818836B2 (ja) 1983-04-14
NO137803C (no) 1978-05-10
DK252575A (hu) 1975-12-07
NO751996L (hu) 1975-12-09
FI58418B (fi) 1980-09-30
HU171888B (hu) 1978-04-28
GB1462150A (en) 1977-01-19
SE376354B (hu) 1975-05-12
AU497191B2 (en) 1978-12-07
FR2274190B1 (hu) 1979-03-23
DK138298B (da) 1978-08-07

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