US3895305A - Clamp circuits - Google Patents

Clamp circuits Download PDF

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Publication number
US3895305A
US3895305A US389712A US38971273A US3895305A US 3895305 A US3895305 A US 3895305A US 389712 A US389712 A US 389712A US 38971273 A US38971273 A US 38971273A US 3895305 A US3895305 A US 3895305A
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US
United States
Prior art keywords
signals
input
resistor
modifying
feedback path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US389712A
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English (en)
Inventor
Jr Millard D Longman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Coulter Electronics Inc
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Coulter Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Coulter Electronics Inc filed Critical Coulter Electronics Inc
Priority to US389712A priority Critical patent/US3895305A/en
Priority to SE7410363A priority patent/SE396177B/xx
Priority to JP49092441A priority patent/JPS5073548A/ja
Priority to GB35849/74A priority patent/GB1483796A/en
Priority to FR7428328A priority patent/FR2241924B1/fr
Priority to NL7410868A priority patent/NL7410868A/xx
Priority to DE19742439869 priority patent/DE2439869B2/de
Application granted granted Critical
Publication of US3895305A publication Critical patent/US3895305A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N15/00—Investigating characteristics of particles; Investigating permeability, pore-volume or surface-area of porous materials
    • G01N15/10—Investigating individual particles
    • G01N15/1031—Investigating individual particles by measuring electrical or magnetic effects
    • G01N15/12—Investigating individual particles by measuring electrical or magnetic effects by observing changes in resistance or impedance across apertures when traversed by individual particles, e.g. by using the Coulter principle
    • G01N15/131—Details
    • G01N15/132—Circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/003—Changing the DC level
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding

Definitions

  • a feedback loop enables filtering out noise of low frequencies.
  • FIG.1 A first figure.
  • the invention relates to clamp circuits, i.e., to electric clamping apparatus and methods, and may be applied. for example, to clamping of trains of pulses produced by particles passing through an electric sensing zone in apparatus for analysis of fluid suspended particles.
  • the simplest form of a clamping circuit which has been used extensively in the prior art comprises a diode associated with a resistance-capacitance network, as will next be explained.
  • a diode is placed on the output side of a coupling capacitor, and a resistor parallel to the diode. If positive pulses are used, the anode of this diode is grounded and the cathode is connected to the signal path. When a pulse arrives, it drives the cathode positive, and no current flows in the diode. During the pulse, a small amount of the charge on the coupling capacitor leaks off through the resistor. When the pulse subsides, and the input side of the capacitor goes back to the base line, the output side is about to go negative.
  • the diode conducts, and charging current flows in it and the capacitor. This action restores the original charge on the capacitor which it had before the pulse, and the low impedances of the diode when it conducts and of the driving amplifier short out the negative-going voltage.
  • the voltage at the output side of the capacitor sits with a grounded base line and puts out only positive pulses as desired.
  • means may be incorporated to balance out the forward voltage drop in the diode, or it may be included in a feedback path to avoid its effect.
  • the prior art clamp circuits could not deal adequately with pulses having a duty cycle of 50 percent or over. Duty cycle is defined as the ratio between the so-called "on" or charge period and the total period of the pulse.
  • the prior art circuits operated on the principle that charging time equals discharge time, or expressed otherwise, areas above and below the base line are approximately equal. This is due to the fact that the circuits were constructed to be symmetrical, ie. to have equal time constants for positive and negative signals.
  • the output of the semiconductor amplifiers generally have a voltage range of 13 volts.
  • the noise is generally 12 volts peak-to-peak and the pulses riding thereon are generally 1 volt.
  • the present invention therefore provides for clamping circuits being non-symmetrical and comprising filters for eliminating the low noise frequencies.
  • a clamp circuit having an amplifier and feedback path with unequal time constants for charge and dis charge periods, thereby enabling the clamping of pulses of duty cycles of 50 percent and over.
  • the clamp circuit also comprises a low pass filter for eliminating the low frequency noise.
  • FIG. I illustrates a conventional clamping circuit.
  • FIG. 2 illustrates pulses on the input side of the capacitor of FIG. I and the pulses emerging therefrom.
  • FIG. 3 illustrates pulses in a sequence different from FIG. 2.
  • FIG. 4 illustrates an output of a semiconductor ainplifier showing noise and pulses riding thereon.
  • FIG. 5 shows a schematic diagram representing the principles of the invention.
  • FIG. 6, illustrates a clamp circuit according to the in vention.
  • FIG. 7. shows another cnibodiment of the invention.
  • FIG. 8 illustrates a further embodiment of the inventive idea.
  • the clamp circuit as shown in FIG. I is a prior art diode circuit and its response to input pulses is illustrated in FIGS. 2 and 3,
  • the individual pulses as seen on the left side are pulses received at the input side of the clamp circuit successively. i.e.. the second pulse arrives after the first pulse is completed.
  • the pattern of the pulses at the output side of the circuit is shown on the right side of FIG. 2. having diminishing amplitudes in the positive portion of thearrie and an undershoot in the negative portion thereof.
  • FIG. 3. represents a situation wherein the second pulse occurs at a time prior to the time i.c.. the end ofthe first pulse. As is readily seen. the clamping ability of the circuit is reduced. and the DC. level eventually centers at zero volts.
  • FIG. 5 The basic idea of the present invention is presented in FIG. 5. in a schematic form.
  • the amplifier 21 has a low pass filter 22 in the feedback path 23.
  • the low pass filter is structured such as to have two unequal time constants. one for the positiie portion of the pulse and another for the negative portion thereof.
  • the low pass filter provides a conve nient path for the low frequency noise which is fed back to the input of the amplifier 21 and is there subtracted.
  • An amplifier 3 has a feedback path 32 which comprises in series a resistor 33, a diode 34 in parallel with a resistor 35, an integrator including an amplifier 36 with a capacitor 37 parallel thereto, and a resistor 38. Between the input terminal 40 of the circuit and the feedback loop there is provided a resistor 41.
  • a pulse is shown as it is received at the input terminal 40.
  • a pulse is illustrated as it leaves the output terminal 42 of the clamp circuit.
  • the diode 34 may be of germanium. is forward biased. having a low threshold voltage of about it] volts.
  • the integrator 36, 37 is an inverting integrator.
  • a pulse of 1 volt sent to amplifier 31 may be amplified by a factor of 10.
  • This [(3 volts pulse is fed back via resistors 33. 35 and the inverting inte grator 36. 37 through resistor 38 to the input of ampli tier 31.
  • the iii-- verting integrator 36. 37 subtracts from the input pulse. the time constant being determined by the product of capacitance 37 and the sum of resistances 33 35. as suming resistors 41 and 38 being equal and negligible.
  • tapacitor 37 discharges with a smaller time constant. the product of capacitance 37 and resistance 33. sin e the diode 34 is forward biased and resis or I is shorted, Because the discharge time constant is Shutter. the clamp circuit can now handle duty cycle pulses of greater than 50 percent.
  • FIG. 7 Another embodiment of the invention is illustrated in FIG. 7.
  • the structure of the circuit is similar to that of FIG. 6. except for the fact that the diode 34 has been removed and in lieu thereof an analog switch AS desig nated as 44 has been placed parallel to resistor 35.
  • a threshold device T with numeral 45 having a negative operating value is connected to the analog switch and the line 32.
  • the analog switch is constructed to be normally open. It is controlled by the threshold device 45.
  • the analog switch In operation, during a positive pulse. the analog switch being open. the time constant is determined by the product of capacitance 37 and resistances 35, 33. In the event of a negative pulse. the threshold device 45 causes the analog switch 44 to close. and the time constant is now the product of capacitance 37 and resistance 33 since resistor 35 is shorted.
  • FIG. 8 A further embodiment of the inventive idea is illustrated in FIG. 8.
  • the left side of the feedback path is similar to those in FIGS. (1 and 7.
  • the right side of the feedback path comprises an amplifier 51 and parallel thereto two diodes 52. 53 are arranged in series.
  • a resistor 54 is connected in parallel to the amplifier 51. and the diode 55 is coupled in paraliel to resistor 54 and amplifier 51.
  • a resistor 56 is connected to line 32.
  • a resistor 58 is connected to the output terminal of amplifier 51. the other terminal of resistor 58 being coupled via a resistor 59 to a node 60 between diodes 52, 53.
  • A. means adjacent the input terminal for receiving the pulse signals.
  • C. means at the output terminal providing a feedback path for the amplified signals
  • D. means associated with the feedback path for inverting and integrating the feedback signals.
  • F. means connected with said integrating means for modifying the time constant of the feedback path such as to produce unequal time constants for positive and negative portions of the pulses, said modifying means constructed to act in response to change of state of the input signals, and
  • said modifying means comprise a first diode and a first resistor.
  • A. means adjacent the input terminal for receiving the pulse signals
  • C. means at the output terminal providing a feedback path for the amplified signals
  • D. means associated with the feedback path for inverting and integrating the feedback signals
  • F. means connected with said integrating means for modifying the time constant of the feedback path such as to produce unequal time constants for positive and negative portions of the pulses, said modifying means constructed to act in response to change of state of the input signals.
  • said modifying means comprise a plurality of diodes and resistors.
  • the modifying means comprises A. a first inverting amplifier
  • G a fourth resistor. one terminal thereof connected to a node between the first and second diodes.
  • A. means adjacent the input terminal for receiving the pulse signals
  • C. means at the output terminal providing a feedback path for the amplified signals
  • D. means associated with the feedback path for inverting and integrating the feedback signals
  • E. means at said amplifying means for combining the input signals with the inverted feedback signals.
  • F. means connected with said integrating means for modifying the time constant of the feedback path such as to produce unequal time constants for positive and negative portions of the pulses, said modifying means constructed to act in response to change of state of the input signals, and
  • said modifying means comprising:

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Biochemistry (AREA)
  • General Health & Medical Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Immunology (AREA)
  • Pathology (AREA)
  • Manipulation Of Pulses (AREA)
  • Amplifiers (AREA)
US389712A 1973-08-20 1973-08-20 Clamp circuits Expired - Lifetime US3895305A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US389712A US3895305A (en) 1973-08-20 1973-08-20 Clamp circuits
SE7410363A SE396177B (sv) 1973-08-20 1974-08-14 Forfarande for lasning av elektriska pulssignaler samt anordning for utforande av forfarandet
JP49092441A JPS5073548A (de) 1973-08-20 1974-08-14
GB35849/74A GB1483796A (en) 1973-08-20 1974-08-14 Clamp circuits
FR7428328A FR2241924B1 (de) 1973-08-20 1974-08-14
NL7410868A NL7410868A (nl) 1973-08-20 1974-08-14 Werkwijze en inrichting voor het vastleggen van het niveau van elektrische pulssignalen.
DE19742439869 DE2439869B2 (de) 1973-08-20 1974-08-20 Schaltung, insbesondere fuer die zaehlung und bestimmung der groessenverteilung mikroskopischer teilchen, zur pegelhaltung von elektrischen impulsen, die ein niederfrequentes stoersignal ueberlagern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US389712A US3895305A (en) 1973-08-20 1973-08-20 Clamp circuits

Publications (1)

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US3895305A true US3895305A (en) 1975-07-15

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US389712A Expired - Lifetime US3895305A (en) 1973-08-20 1973-08-20 Clamp circuits

Country Status (7)

Country Link
US (1) US3895305A (de)
JP (1) JPS5073548A (de)
DE (1) DE2439869B2 (de)
FR (1) FR2241924B1 (de)
GB (1) GB1483796A (de)
NL (1) NL7410868A (de)
SE (1) SE396177B (de)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4093876A (en) * 1976-01-12 1978-06-06 Commissariat A L'energie Atomique Baseline restorer circuit
US4322811A (en) * 1979-03-16 1982-03-30 U.S. Philips Corporation Clamping circuit for an adaptive filter
US4692618A (en) * 1985-05-02 1987-09-08 Hughes Aircraft Company Detector signal conditioner
US4713558A (en) * 1982-07-09 1987-12-15 Healthdyne, Inc. Patient monitor for providing respiration and electrocardiogram signals
US4749951A (en) * 1984-06-13 1988-06-07 Mitsubishi Denki Kabushiki Kaisha Low-pass filter circuit with variable time constant
FR2622070A1 (fr) * 1987-10-14 1989-04-21 Jaeger Dispositif de mise en forme de signaux analogiques frequentiels de type point mort haut
US5239559A (en) * 1991-11-08 1993-08-24 Methode Electronics, Inc. Terminator method and apparatus
US6274989B1 (en) * 1999-01-12 2001-08-14 Walter Truskalo Dynamic damping clamper arrangement associated with s-shaping capacitor
US20040189379A1 (en) * 2000-11-27 2004-09-30 Sharp Kabushiki Kaisha Power amplification circuit and communication device using the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1571168A (en) * 1977-04-11 1980-07-09 Tektronix Inc Electronic circuit for attenuating spurious electronic signals
JPH04117834A (ja) * 1990-09-07 1992-04-17 Mitsubishi Electric Corp デジタル伝送回路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3435252A (en) * 1964-08-26 1969-03-25 Bell Telephone Labor Inc D.c. restorer
US3521177A (en) * 1966-03-02 1970-07-21 Philips Corp Circuit arrangement for correcting a television signal
US3534282A (en) * 1969-08-13 1970-10-13 American Optical Corp Spike suppression circuit
US3772604A (en) * 1972-05-12 1973-11-13 Coulter Electronics Non-rectifying clamps

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3435252A (en) * 1964-08-26 1969-03-25 Bell Telephone Labor Inc D.c. restorer
US3521177A (en) * 1966-03-02 1970-07-21 Philips Corp Circuit arrangement for correcting a television signal
US3534282A (en) * 1969-08-13 1970-10-13 American Optical Corp Spike suppression circuit
US3772604A (en) * 1972-05-12 1973-11-13 Coulter Electronics Non-rectifying clamps

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4093876A (en) * 1976-01-12 1978-06-06 Commissariat A L'energie Atomique Baseline restorer circuit
US4322811A (en) * 1979-03-16 1982-03-30 U.S. Philips Corporation Clamping circuit for an adaptive filter
US4713558A (en) * 1982-07-09 1987-12-15 Healthdyne, Inc. Patient monitor for providing respiration and electrocardiogram signals
US4749951A (en) * 1984-06-13 1988-06-07 Mitsubishi Denki Kabushiki Kaisha Low-pass filter circuit with variable time constant
US4692618A (en) * 1985-05-02 1987-09-08 Hughes Aircraft Company Detector signal conditioner
FR2622070A1 (fr) * 1987-10-14 1989-04-21 Jaeger Dispositif de mise en forme de signaux analogiques frequentiels de type point mort haut
US5239559A (en) * 1991-11-08 1993-08-24 Methode Electronics, Inc. Terminator method and apparatus
US6274989B1 (en) * 1999-01-12 2001-08-14 Walter Truskalo Dynamic damping clamper arrangement associated with s-shaping capacitor
US20040189379A1 (en) * 2000-11-27 2004-09-30 Sharp Kabushiki Kaisha Power amplification circuit and communication device using the same
US6873207B2 (en) * 2000-11-27 2005-03-29 Sharp Kabushiki Kaisha Power amplification circuit and communication device using the same
US7173487B2 (en) 2000-11-27 2007-02-06 Sharp Kabushiki Kaisha Power amplification circuit and communication device using the same

Also Published As

Publication number Publication date
DE2439869B2 (de) 1976-07-01
SE396177B (sv) 1977-09-05
GB1483796A (en) 1977-08-24
FR2241924A1 (de) 1975-03-21
NL7410868A (nl) 1975-02-24
SE7410363L (de) 1975-02-21
DE2439869A1 (de) 1975-03-13
JPS5073548A (de) 1975-06-17
FR2241924B1 (de) 1976-10-22

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