US3895305A

US3895305A - Clamp circuits

Info

Publication number: US3895305A
Application number: US389712A
Authority: US
Inventors: Jr Millard D Longman
Original assignee: Coulter Electronics Inc
Current assignee: Coulter Electronics Inc
Priority date: 1973-08-20
Filing date: 1973-08-20
Publication date: 1975-07-15
Anticipated expiration: 1992-07-15
Also published as: JPS5073548A; DE2439869A1; SE396177B; SE7410363L; GB1483796A; DE2439869B2; FR2241924B1; NL7410868A; FR2241924A1

Abstract

Apparatus for clamping electrical pulses with duty cycles over fifty percent. A feedback loop enables filtering out noise of low frequencies.

Description

United States Patent Longman, Jr.

[4 1 July 15, 1975 CLAMP CIRCUITS Millard D. Longman, Jr., North Miami Beach, Fla.

Inventor:

Assignee: Coulter Electronics, Inc., Hialeah,

Fla.

Filed: Aug. 20, 1973 Appl. N0.: 389,712

US. Cl. 328/171; 307/237; 328/162;

328/165; 328/167; 330/149 Int. Cl. "03k 5/08; H03b 3/02 Field of Search 328/162, 165, 167, 168,

[56] References Cited UNlTED STATES PATENTS 3,435,252 3/1969 Eubanks 307/237 3,521,177 7/1970 De Niet 307/237 X 3,534,282 10/1970 Day 1 328/165 X 3.772.604 11/1973 Hogg et a1 307/235 R Primary Examiner-John Zazworsky Attorney, Agent, or Firm-Silverman & Cass, Ltd.

[57] ABSTRACT Apparatus for clamping electrical pulses with duty cycles over fifty percent. A feedback loop enables filtering out noise of low frequencies.

5 Claims, 8 Drawing Figures PATENTEDJUL I 5 ms 3; 895. 305

FIG.1

L I \70 VW PRIORART 1=|G.2 NPUT I I OUTPUT J T i i Has lNPUT mm OUTPUT LOW PASS FILTER FIG. 7

CLAMP CIRCUITS BACKGROUND OF THE INVENTION The invention relates to clamp circuits, i.e., to electric clamping apparatus and methods, and may be applied. for example, to clamping of trains of pulses produced by particles passing through an electric sensing zone in apparatus for analysis of fluid suspended particles.

The basic principle of such analysis is referred to as the Coultcr principle and is described in US. Pat. No. 2,656,508. According to this principle, the passage of microscopic particles suspended in a conducting liquid through an aperture, having dimensions which approximate those of the particle, causes a change in the impedance of the electrical path through the liquid effectively contained in the aperture, if the material of the particle and the liquid have different conductivities.

Studies have shown that the magnitude of this change is proportional to the volume of the particle where the cross-sectional area of the particle is much smaller than the cross-sectional area of the aperture and the particle is small enough to be completely contained in the sensing zone thus formed.

Under proper conditions electric signals are gener ated, the respective amplitudes of which, generally, are linear functions of the volumes of the respective particles passing through the aperture.

In the U.S. Pat. application of Walter R. Hogg, et al., Ser. No. 252,794 for Non-Rectifying Clamps, now US. Pat. No. 3,772,604, apparatus and methods were dis closed for clamping signals comprising a DC. level and pulses thereon, with the aim of eliminating the DC. level.

The simplest form of a clamping circuit which has been used extensively in the prior art comprises a diode associated with a resistance-capacitance network, as will next be explained.

Normally, in order to clamp 21 pulse train so as to force the base line to be at ground or at any desirable D.C. level, a diode is placed on the output side ofa coupling capacitor, and a resistor parallel to the diode. If positive pulses are used, the anode of this diode is grounded and the cathode is connected to the signal path. When a pulse arrives, it drives the cathode positive, and no current flows in the diode. During the pulse, a small amount of the charge on the coupling capacitor leaks off through the resistor. When the pulse subsides, and the input side of the capacitor goes back to the base line, the output side is about to go negative. As soon as it does, the diode conducts, and charging current flows in it and the capacitor. This action restores the original charge on the capacitor which it had before the pulse, and the low impedances of the diode when it conducts and of the driving amplifier short out the negative-going voltage. Thus, the voltage at the output side of the capacitor sits with a grounded base line and puts out only positive pulses as desired. In addition, means may be incorporated to balance out the forward voltage drop in the diode, or it may be included in a feedback path to avoid its effect.

This conventional method is adequate where the pulses are of a nature such that there is a large signalto-noise ratio, but when the noise is not small compared to the pulses, the clamp circuit acts like a halfwave rectifier, and rectifies the noise so that the quiescent level, which may be called the base line, sits at a positive voltage somewhat less than the peak value of the noise.

In order to avoid this result the above noted patent application Ser. No. 252,794 provides for apparatus comprising an amplifier having a feedback path which is constructed such as to conduct the DC. level and the noise filtered from the amplifier output to the amplifier input via a linear. non-rectifying, path for subtraction.

The clamp circuits used in the prior art have generally been operating with good results. However, it has been found that they were incapable of overcoming certain shortcomings as will be explained hereinafter.

The prior art clamp circuits could not deal adequately with pulses having a duty cycle of 50 percent or over. Duty cycle is defined as the ratio between the so-called "on" or charge period and the total period of the pulse. The prior art circuits operated on the principle that charging time equals discharge time, or expressed otherwise, areas above and below the base line are approximately equal. This is due to the fact that the circuits were constructed to be symmetrical, ie. to have equal time constants for positive and negative signals.

As a consequence, when pulses were received by the clamp circuit. having a duty cycle of 50 percent or greater the circuit operation became indistinct and vague, since the discharge of the capacitor utilized in the circuit did not fully occur when the second pulse arrived.

Another shortcoming in the prior art clamp circuits stems from the limitations on dynamic range. In the prior art the circuits were utilized with tube amplifiers, The output of the amplifiers generally took the form of the high frequency pulses riding upon low frequency noise. The low frequency signal would have a peak-topeak amplitude of volts and the pulses riding thereon generally had a maximum amplitude of [0 volts. The dynamic range of the tube amplifiers had to be at least volts to avoid clipping off the pulse information riding upon the low frequency noise.

The output of the semiconductor amplifiers generally have a voltage range of 13 volts. The noise is generally 12 volts peak-to-peak and the pulses riding thereon are generally 1 volt.

Therefore, while in the past, vacuum tubes provided an input circuit with an adequate dynamic range, the situation is now different since with solid state devices the dynamic range has been reduced.

The present invention therefore provides for clamping circuits being non-symmetrical and comprising filters for eliminating the low noise frequencies.

SUMMARY OF THE INVENTION A clamp circuit having an amplifier and feedback path with unequal time constants for charge and dis charge periods, thereby enabling the clamping of pulses of duty cycles of 50 percent and over. The clamp circuit, also comprises a low pass filter for eliminating the low frequency noise.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I, illustrates a conventional clamping circuit.

FIG. 2, illustrates pulses on the input side of the capacitor of FIG. I and the pulses emerging therefrom.

FIG. 3, illustrates pulses in a sequence different from FIG. 2.

FIG. 4, illustrates an output of a semiconductor ainplifier showing noise and pulses riding thereon.

FIG. 5, shows a schematic diagram representing the principles of the invention.

FIG. 6, illustrates a clamp circuit according to the in vention.

FIG. 7. shows another cnibodiment of the invention.

FIG. 8, illustrates a further embodiment of the inventive idea.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The clamp circuit as shown in FIG. I, is a prior art diode circuit and its response to input pulses is illustrated in FIGS. 2 and 3, In FIG. 2, the individual pulses as seen on the left side are pulses received at the input side of the clamp circuit successively. i.e.. the second pulse arrives after the first pulse is completed. The pattern of the pulses at the output side of the circuit is shown on the right side of FIG. 2. having diminishing amplitudes in the positive portion of the puise and an undershoot in the negative portion thereof.

FIG. 3. represents a situation wherein the second pulse occurs at a time prior to the time i.c.. the end ofthe first pulse. As is readily seen. the clamping ability of the circuit is reduced. and the DC. level eventually centers at zero volts.

The basic idea of the present invention is presented in FIG. 5. in a schematic form.

The amplifier 21 has a low pass filter 22 in the feedback path 23. The low pass filter is structured such as to have two unequal time constants. one for the positiie portion of the pulse and another for the negative portion thereof. The low pass filter provides a conve nient path for the low frequency noise which is fed back to the input of the amplifier 21 and is there subtracted.

An embodiment ofthe inventive idea is illustrated in FIG. 6. An amplifier 3] has a feedback path 32 which comprises in series a resistor 33, a diode 34 in parallel with a resistor 35, an integrator including an amplifier 36 with a capacitor 37 parallel thereto, and a resistor 38. Between the input terminal 40 of the circuit and the feedback loop there is provided a resistor 41.

On the left side of FIG. 6. a pulse is shown as it is received at the input terminal 40. On the right side, a pulse is illustrated as it leaves the output terminal 42 of the clamp circuit.

The diode 34 may be of germanium. is forward biased. having a low threshold voltage of about it] volts. The

integrator

36, 37 is an inverting integrator.

In operation, a pulse of 1 volt sent to amplifier 31 may be amplified by a factor of 10. This [(3 volts pulse is fed back via resistors 33. 35 and the inverting inte grator 36. 37 through resistor 38 to the input of ampli tier 31. During the positive portion of the pulse. the iii-- verting integrator 36. 37 subtracts from the input pulse. the time constant being determined by the product of capacitance 37 and the sum of resistances 33 35. as suming resistors 41 and 38 being equal and negligible. Once the pulse at the output of amplifier 31 is gone. tapacitor 37 discharges with a smaller time constant. the product of capacitance 37 and resistance 33. sin e the diode 34 is forward biased and resis or I is shorted, Because the discharge time constant is Shutter. the clamp circuit can now handle duty cycle pulses of greater than 50 percent.

l he gain of the integrator has been chosen to be very large at I').(. and decreasing with frequency. The feed back path gives a phase in\ersion of ITII. 'I heietore. since the pulses generally haie their energy at abo\e l\'('. the high frequency pulses are attenuated in the feedback path and. do not subtract from the input of the amplifier 3] It may be noted that the clamp circuit of FIG 6, was built and tested with the following figures:

capacitor 17 13 pl resistor 35 I h 1 resistor I? 11 K. diode 34 IN IUI The undershoot duration n was apprtmimately 2U us. almost regardless of pulse width.

Another embodiment of the invention is illustrated in FIG. 7. The structure of the circuit is similar to that of FIG. 6. except for the fact that the diode 34 has been removed and in lieu thereof an analog switch AS desig nated as 44 has been placed parallel to resistor 35. A threshold device T with numeral 45 having a negative operating value is connected to the analog switch and the line 32. The analog switch is constructed to be normally open. It is controlled by the threshold device 45.

In operation, during a positive pulse. the analog switch being open. the time constant is determined by the product of capacitance 37 and

resistances

35, 33. In the event of a negative pulse. the threshold device 45 causes the analog switch 44 to close. and the time constant is now the product of capacitance 37 and resistance 33 since resistor 35 is shorted.

A further embodiment of the inventive idea is illustrated in FIG. 8. In this circuit the left side of the feedback path is similar to those in FIGS. (1 and 7. The right side of the feedback path comprises an amplifier 51 and parallel thereto two diodes 52. 53 are arranged in series. Furthermore. a resistor 54 is connected in parallel to the amplifier 51. and the diode 55 is coupled in paraliel to resistor 54 and amplifier 51. At the input side of amplifier 51 a resistor 56 is connected to line 32. A resistor 58 is connected to the output terminal of amplifier 51. the other terminal of resistor 58 being coupled via a resistor 59 to a node 60 between

diodes

52, 53.

In operation when the output 42 is positive. point P or 57 is negative. diode 52 is reverse biased and there is no signal to resistor 59. The charging path for capacitor 37 is through resistor 58 via diode 55.

When the output 42 is negative. the diode S2 is for" ward biased and the capacitor 37 charges through rcsis tors 58. 59. Having the diode S2 in the feedback loop gives the circuit a sharper turn-on. turn-off characteris' tic. The resistor 56 is 2.2 Is, resistor 54 is 22 K.

it will be appreciated that while the basic idea of the invention has been set forth in connection with the tilfl;

grant in FIG. 5. the three embodiments illustrated in FIG, 6 to 8 shovi elements and values as appiicd for ohtaining the objectives of the invention. i.c.. a clamp cir cuit with unequai time constants for positive and negative pulses as well as a favorable feedback path for ion rn-quencies of noise.

I; believed that the foregoing adequately will en 'i it thost; skilled in the art to appreciate and practice this ltltctlIiOll and. if necessary. make modifications which wiil fall within the scope of the invention as do tilted by the accompanying claims.

What it is desired to secure by Letters Patent of the United States is:

1. Apparatus for clamping electric pulse signals which are superimposed upon low noise frequencies. the signals having duty cycle pulses of greater than 50 percent, said apparatus having input and output terminals comprising:

A. means adjacent the input terminal for receiving the pulse signals.

B. means connected to said receiving means for amplifying the signals,

C. means at the output terminal providing a feedback path for the amplified signals,

D. means associated with the feedback path for inverting and integrating the feedback signals.

E. means at said amplifying means for combining the input signals with the inverted feedback signals,

F. means connected with said integrating means for modifying the time constant of the feedback path such as to produce unequal time constants for positive and negative portions of the pulses, said modifying means constructed to act in response to change of state of the input signals, and

G. wherein said modifying means comprise a first diode and a first resistor.

2. Apparatus as set forth in claim 1, in which the feedback path comprises A. a second resistor at the input side of the modifying means, and

B. a third resistor at the output side of the inverting and integrating means, wherein the apparatus includes a fourth resistor connected to the input terminal thereof.

3. Apparatus for clamping electric pulse signals which are superimposed upon low noise frequencies, the signals having duty cycle pulses of greater than 50 percent, said apparatus having input and output terminals comprising:

A. means adjacent the input terminal for receiving the pulse signals,

B. means connected to said receiving means for amplifying the signals.

D. means associated with the feedback path for inverting and integrating the feedback signals,

F. means connected with said integrating means for modifying the time constant of the feedback path such as to produce unequal time constants for positive and negative portions of the pulses, said modifying means constructed to act in response to change of state of the input signals. and

G. wherein said modifying means comprise a plurality of diodes and resistors.

4. Apparatus as set forth in claim 3, in which the modifying means comprises A. a first inverting amplifier,

B. a first resistor connected to the input side of the first inverting amplifier,

C. a second resistor connected to the output side of the first inverting amplifier.

D. a third resistor parallel to the first inverting ampli- E. a first diode parallel to the first inverting amplifier.

F. a second diode and a third diode in series. both last diodes connected in parallel to the first inverting amplifier, and

G. a fourth resistor. one terminal thereof connected to a node between the first and second diodes. the

other terminal of the fourth resistor connected to the input of a second inverting amplifier.

5. Apparatus for clamping electric pulse signals which are superimposed upon low noise frequencies. the signals having duty cycle pulses of greater than 50 percent, said apparatus having input and output terminals comprising:

A. means adjacent the input terminal for receiving the pulse signals,

B. means connected to said receiving means for amplifying the signals.

E. means at said amplifying means for combining the input signals with the inverted feedback signals.

G. said modifying means comprising:

a. analog switch means and threshold means having negative characteristic value for controlling said switch means,

b. a first resistor in parallel connection with the analog switch means, and

c. a second resistor in parallel connection with the threshold means.

Claims

1. Apparatus for clamping electric pulse signals which are superimposed upon low noise frequencies, the signals having duty cycle pulses of greater than 50 percent, said apparatus having input and output terminals comprising: A. means adjacent the input terminal for receiving the pulse signals, B. means connected to said receiving means for amplifying the signals, C. means at the output terminal providing a feedback path for the amplified signals, D. means associated with the feedback path for inverting and integrating the feedback signals, E. means at said amplifying means for combining the input signals with the inverted feedback signals, F. means connected with said integrating means for modifying the time constant of the feedback path such as to produce unequal time constants for positive and negative portions of the pulses, said modifying means constructed to act in response to change of state of the input signals, and G. wherein said modifying means comprise a first diode and a first resistor.

2. Apparatus as set forth in claim 1, in which the feedback path comprises A. a second resistor at the input side of the modifying means, and B. a third resistor at the output side of the inverting and integrating means, wherein the apparatus includes a fourth resistor connected to the input terminal thereof.

3. Apparatus for clamping electric pulse signals which are superimposed upon low noise frequencies, the signals having duty cycle pulses of greater than 50 percent, said apparatus having input and output terminals comprising: A. means adjacent the input terminal for receiving the pulse signals, B. means connected to said receiving means for amplifying the signals, C. means at the output terminal providing a feedback path for the amplified signals, D. means associated with the feedback path for inverting and integrating the feedback signals, E. means at said amplifying means for combining the input signals with the inverted feedback signals, F. means connected with said integrating means for modifying the time constant of the feedback path such as to produce unequal time constants for positive and negative portions of the pulses, said modifying means constructed to act in response to change of state of the input signals, and G. wherein said modifying means comprise a plurality of diodes and resistors.

4. Apparatus as set forth in claim 3, in which the modifying means comprises A. a first inverting amplifier, B. a first resistor connected to the input side of the first inverting amplifier, C. a second resistor connected to the output side of the first inverting amplifier, D. a third resistor parallel to the first inverting amplifier, E. a first diode parallel to the first inverting amplifier, F. a second diode and a third diode in series, both last diodes connected in parallel to the first inverting amplifier, and G. a fourth resistor, one terminal thereof connected to a node between the first and second diodes, the other terminal of the fourth resistor connected to the input of a second inverting amplifier.

5. Apparatus for clamping electric pulse signals which are superimposed upon low noise frequencies, the signals having duty cycle pulses of greater than 50 percent, said apparatus having input and output terminals comprising: A. means adjacent the input terminal for receiving the pulse signals, B. means connected to said receiving means for amplifying the signals, C. means at the output terminal providing a feedback path for the amplified signals, D. means associated with the feedback path for inverting and integrating the feedback signals, E. means at said amplifying means for combining the input signals with the inverted feedback signals, F. means connected with said integrating means for modifying the time constant of the feedback path such as to produce unequal time constants for positive and negative portions of the pulses, said modifying means constructed to act in response to change of state of the input signals, and G. said modifying means comprising: a. analog switch means and threshold means having negative characteristic value for controlling said switch means, b. a first resistor in parallel connection with the analog switch means, and c. a second resistor in parallel connection with the threshold means.