US3876982A - Code programming device - Google Patents

Code programming device Download PDF

Info

Publication number
US3876982A
US3876982A US392872A US39287273A US3876982A US 3876982 A US3876982 A US 3876982A US 392872 A US392872 A US 392872A US 39287273 A US39287273 A US 39287273A US 3876982 A US3876982 A US 3876982A
Authority
US
United States
Prior art keywords
code
signal
coupled
connection terminals
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US392872A
Other languages
English (en)
Inventor
Albertus Marinus Morrien
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Philips Corp
Original Assignee
US Philips Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by US Philips Corp filed Critical US Philips Corp
Application granted granted Critical
Publication of US3876982A publication Critical patent/US3876982A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/02—Terminal devices
    • H04W88/022—Selective call receivers
    • H04W88/025—Selective call decoders
    • H04W88/026—Selective call decoders using digital address codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • l68, 348, l68 R, 147 R, 164 each code conductor with its own sub-code.
  • the inte- R; 328/37, 39, 42 grated circuit is coupled to the coding matrix so as to receive a code signal programmed in the coding ma- [56] References Cited trix.
  • the invention relates to a code programming device. comprising a circuit which is provided with an envelope and a coding matrix to which the circuit is coupled so as to supply this circuit with a code signal programmed by means of the coding matrix.
  • Devices of this kind in which the code signals are ad dress codes are used inter alia in receivers of selective paging systems.
  • the envelope is provided with a number of connection terminals. corresponding to the number of bits of the address code. for applying a specific address code to the circuit.
  • the coding matrix comprises a conductor which carries a high voltage and a conductor which carries a low voltage. the connection terminals being connected to these conductors in accordance with the address code to be programmed.
  • connection terminals of an envelope of a circuit however. is limited. This implies that the number of connection terminals which can be made available for programming address codes in the described manner for selective paging systems comprising very many subscribers is too small.
  • the invention has for its object to provide a completely novel concept for the programming of code signals. in which the required number of connection terminals of the envelope of the circuit is small with respect to the number of bits of the code signals.
  • the device according to the invention is characterized in that the coding matrix comprises code conductors and a code generator which is connected thereto in order to supply each code conductor with its own sub-code.
  • a sub-code is to be understood to mean a signal which forms a part of a code signal to be programmed.
  • the code generator is arranged within the envelope ofthe circuit. This offers the advantage that no separate envelope is required for the code generator, whilst the number of connection terminals of the common envelope which must be available for generating a code signal is minimum.
  • French Patent Specification No. 2.019.375 describes a circuit where the bits of a code signal are successively applied to a code comparison device. However. by means of this circuit no code signal can be programmed but a given code signal can only be stored.
  • FIGS. 1,3 and 5 show different embodiments of a programming device according to the invention.
  • FIGS. 2, 4 and 6 show signals which can appear in the programming devices shown in the FIGS. 1, 3 and 5, respectively.
  • the programming device shown in FIG. 1 is used inter alia in a receiver of a selective paging system.
  • a code comparison device in a receiver of this kind a received code signal is compared with a specific code signal present in the receiver.
  • code signals are referred to as address codes.
  • they are uniformly constructed in integrated form. For putting a receiver of this kind into operation in a selective paging system. It must be possible to adjust an address code for the relevant receiver in a simple manner. To this end. the receivers are provided with a coding matrix 1. In known receivers.
  • this matrix is composed of a first conductor 2 which is connected, via a connection terminal 8-1 of the envelope 10, to a voltage source (not shown in the drawing) for supplying this conductor 2 with a low voltage signal. denoted by the logic symbol O. and a second conductor 5 which is also connected to the voltage source, via a connection terminal 8-4, for supplying this conductor with a high voltage signal which is denoted by the logic symbol I.
  • the specific address code is applied to the integrated code comparison device. not shown in the figure. by connecting each of the connection terminals 6 of the envelope 10 of the integrated code comparison device to one of the two conductors 2, 5 in accordance with the address code to be programmed. A separate connection terminal 6 must then be available on the envelope for each bit of the address code.
  • the address codes are composed of a correspondingly large number of bits. This implies that an insufficient quantity of connection terminals 6 for applying these long address codes are available on the envelope.
  • the coding matrix 1 is provided with code conductors 3 and 4, and a code generator 7 is provided which is connected to the code conductors 3 and 4, via connection terminals 8-2 and 8-3, in order to supply each of these code conductors 3, 4 with its own sub-code.
  • This code generator 7 comprises a bistable element which is provided with a trigger input T. a signal output 0 and an inverted signal output 2. Ifa voltage changing from high to low appears on the trigger input T. the bistable element is switched over from the set state to the reset state or vice versa. the set state being characterized in that signal output 0 carries a high voltage signal I and the inverted signal output Q carries a low voltage signal 0, and vice versa for the reset state.
  • the trigger input T of the bistable element 7 is connected. via connection terminal 9, to a clock pulse input 11 which receives the clock pulse signal shown in FIG. 2a.
  • the bistable element 7 divides this pulse series by two and supplies the signal output Q and the inverted signal output 6 with the signals shown in FIGS. 20 and 2d, the said signals representing sub-codes of the code signal to be programmed. Together with the voltage signals on the conductors 2 and 5, four codes having a length of two bits are obtained. i.e.. 0.0; l. O; 0. l and l. I. respectively. for the conductors 2 to 5.
  • each address code can be applied to an input terminal 11' of an integrated code comparison device (not shown in the figure).
  • a contact pyramid 12 comprising control inputs 13 is provided. and also a control signal generator l4 which is connected to the inverted signal output Q of code generator 7 and which is connected to the control inputs 13-1 to 13-16.
  • the contact pyramid 12 is composed of identical two-position switches 15 to 21, two-position switch 21 being shown in detail.
  • the two-position switch comprises two AND-gates 23 and 24, a signal input 26, 27 and a control input 13-5, 13-6 being connected to the inputs of each AND- gate.
  • the AND-gates being connected to input terminal 11' via an OR-gate 25. lfa high signal is applied to control input 13-5, the signal on input 26 will be applied to input terminal 11' via AND-gate 23 and OR-gate 25. Similarly, if the control signal on control input 13-6 is high. the signal on input 27 will be applied to input terminal 11' via AND-gate 24 and OR-gate 25.
  • the control signals are generated in the control signal generator 14.
  • This generator comprises three cascade-connected bistable elements 28, 29 and 30 which are identical to bistable element 7. By means of these elements 28, 29 and 30, control signals are obtained by successive two-division of the pulse series which is supplied by code generator 7 and which is shown in FIG. 2d, the control signal supplied by the signal outputs Q of the elements 28, 29 and 30 being shown in the FIGS. 2f. 2g and 2h.
  • connection terminal 6-1, 6-2; 6-3, 6-4; 6-5, 6-6; and 6-7, 6-8 are connected in pairs to the inputs of the two-position switches 15, 16, 17 and 18, which also receive the control signals supplied by element 28.
  • the outputs of the switches are connected to the inputs of the two-position switches 19 and 20, which also receive the control signals supplied by element 29.
  • the outputs of these switches are connected to the signal inputs 26 and 27, the control signals generated by element 30 being applied to the control terminals 13-5 and 13-6.
  • connection terminal 6-1 is connected to input terminal 11' during this period.
  • connection terminal 6-2 is connected to input terminal 11 during this period.
  • connection terminals 6-3, 6-4, 6-5, 6-6, 6-7 and 6-8 are successively connected to the input terminal 11.
  • the two-bit sub-codes are each time applied to input terminal 11.
  • an address code comprising sixteen bits is applied to the input terminal 11' by means of eight connection terminals 6-1 to 6-8, whilst only two additional connection terminals 8-3 and 8-4 are required to enable application of the codes to the code conductors 3 and 4.
  • FIG. 3 One embodiment in which sub-codes having a length of three bits are used is illustrated in FIG. 3.
  • the code programming device shown in FIG. 3 differs from that shown in FIG. 1 in that the coding matrix comprises, in addition to the voltage conductors 32 and 39, six code conductors 33 to 37, in that the code generator 43 is constructed as a three-divider. in that the contact pyramid is realized by means of three-position switches 44, 45, 46 and 47, and in that the control signal generator comprises three-dividers 48 and 49.
  • the three-dividers comprise two series-connected bistable elements 50 and 51 which are provided with a signal input A in addition to a trigger input T, a signal output Q, and an inverted signal output Q.
  • the bistable element is set or reset, in accordance with the signal value applied to the signal input s.
  • the trigger inputs T of these elements 50 and 51 are connected, via terminal 43-6 and connection terminal 39a, to a clock input 52 which receives the clock pulse signal which is shown in FIG. 4a.
  • the signal shown in FIG. 4c is applied to code conductor 33 via terminal 43-0, inverter 54 and connection terminal 42-2.
  • the other signals generated by the three-divider 43, shown in the FIGS. 4d to 4h, are applied to the code conductors 34 to 37 via terminals 43-1 to 43-5 and connection terminals 42-3 to 42-7.
  • the voltage conductors 32 and 39 receive their voltages, shown in the FIGS. 4b and 4k, in a manner not shown via the connection terminals 42-1 and 42-8.
  • the three-position switches 44 to 47 comprise, as is shown in detail for three-position switch 47, three AND-gates 55, 56, 57 which are connected, via an OR- gate 58, to an input terminal 59 of a code comparison device not shown. Connected to inputs of each AND- gate 55, 56 and 57 are a signal input 60, 61 and 62 and a control signal input 49-1, 49-2, 49-4. Depending on whether or not a control signal applied to an AND-gate is high, the signal input connected to the relevant AND-gate is connected to the input terminal 59.
  • the three-divider 48 derives the signals which are shown in the FIGS. 4m, 4n and 4p from the signal which is supplied by code generator 43 via terminal 43-7 and which is shown in FIG. 4g, the said signals being applied to the three-position switches 44, 45 and 46 via the terminals 48-1, 48-2 and 48-4.
  • the three-divider 49 derives the signals shown in the FIGS. 4: 4r and 4s from the signal supplied via terminal 48-7 and shown in FIG. 4p, the derived signals being applied to the terminals 49-1, 49-2 and 49-4.
  • connection terminals 41-1, 41-2, 41-3; 41-4, 41-5, 41-6; and 41-7, 41-8 and 41-9 are connected in groups of three to the signal inputs of the three-position switches 44, 45 and 46, whilst the outputs of these switches are connected to the signal inputs 60, 61 and 62.
  • connection terminal 41-1 is connected to the input terminal 59 between the instants 1,, and 1,. connection terminal 41-2 being connected thereto between I, and 1 etc. Consequently, the connection terminals 41-1 to 41-9 are thus successively connected to the input terminal 49. each time during one cycle time of the sub-codes.
  • any desired address code can be adjusted.
  • the address code shown in FIG. 4t is adjusted by way of the connections shown in the matrix 31, the said address code having a length of twenty-seven bits.
  • the number of connection terminals required for this address code so as to apply this address code to input terminal 59 amounts to nine, whilst six additional connection terminals 42-2 to 42-7 are required for applying the sub-codes to the coding matrix 31.
  • the code generator 60 is accommodated outside the envelope 61.
  • the subcodes have a length of two bits. so that a'coding matrix 62 suffices which contains, in addition the voltage conductors 63 and 66, the code conductors 64 and 65.
  • the voltage conductors 63 and 66 are connected to the terminals 67 and 68 of a voltage source not shown and carry the signals shown in FIGS. 6a and 6d.
  • the code generator 60 is a clock pulse generator which applies the sub-code shown in FIG. 6b to code conductor 64 and which applies the inverted sub-code shown in FIG. 6c to code conductor 65.
  • the envelope 61 is provided with connection terminals 70-1 to 70-5.
  • each connection terminal 70-1, 70-2, 70-3, 70-4 is connected to signal inputs s of two storage elements 71, 72; 73, 74; 75, 76 and 77, 78 which are constructed as bistable elements.
  • the input terminals 69-1 to 69-8 are connected to the signal outputs Q of these elements.
  • the code generator 60 applies, on the one side, the pulse sequence shown in FIG.
  • connection terminals 70-1 to 704 The operation will be described in detail with reference to a specific address code which is determined by the connections established between the connection terminals 70-1 to 704 and the conductors 63 to 66.
  • the signal values on the conductors 63 to 66 are successively low, high and high.
  • connection terminals 70-1 to 70-4 to the signal inputs s of the bistable elements 71, 72, 73, 74, 75, 76 and 77, 78.
  • the negative voltage variation (FIG. 6e) produced by the delay element 79 at the instant I adjusts the odd storage elements 71, 72, 73 and 77 to the reset state. the reset state, the set state and the set state. successively. in accordance with the signal values present on their input terminals.
  • the signal values of the code conductors 64 and and hence the signal values on the signal inputs s of the storage elements 73, 74 and 75, 76 change from low to high (FIG. 6b) and from high to low (FIG. 6c), respectively.
  • the positive voltage variation (FIG. 6e) produced by the delay element 79 at the instant I adjusts the even storage elements 72, 74, 76 and 78 to the reset state. the set state, the reset state and the set state, respectively, via inverter 82. in accordance with the signal values present on their signal inputs s.
  • the storage elements 71 to 78 apply an address code to the input terminals 69-1 to 69-8 which has the bit values 0.0.0, 1.1. 0, 1,1. respectively.
  • the number of input terminals required for writing the above eight-bit address code amounts to one connection terminal for the control signal and four connection terminals for the eight bits.
  • the even storage elements 72, 74, 76 can be dispensed with, and that if the code comparison device is adapted to compare the address code with a received code signal partly at the instants I 1 1 etc. and partly at the instants t t t etc., all storage elements 71 to 78 can be dispensed with.
  • the control sig nals supplied by delay unit 79 and/or inverter 82 are then used for controlling the code comparison device.
  • a device comprising code-matrix means for generating a fixed code signal comprising a plurality of code conductors.
  • a code generator means having an input means for receiving locally generated identical clock pulses and an output means coupled to said conductors for supplying to each of said conductors a subcode respectively, and a circuit means coupled to said matrix means for receiving from said matrix means said code signal.
  • a device as claimed in claim 1. further comprising connection terminal means coupled to the code matrix for receiving the sub-codes.
  • the circuit means comprising one code signal output terminal means for providing the code signal in series.
  • a switching device provided with a control input. said switching device being coupled between the connection terminals and the code signal output terminal. the code generator being coupled to the control input. said switching device comprising means for coupling the connection terminals successively to the code signal output terminal under the control of a signal supplied by the code generator.
  • circuit means comprises a plurality of output terminals which correspond to the number of bits of the code signal, and further comprising connection terminals means coupled to the coding matrix for receiving the subcodes.
  • storage elements provided with a plurality of control inputs which corresponds to the number of bits of the sub-code. said elements being coupled to each connection terminal. the said storage elements being coupled to the output terminals and comprising means for supplying the output terminals simultaneously with the bits of the sub-codes which are successively applied to the connection terminals, and a control signal generator coupled to said control inputs.
  • a device as claimed in claim 1 further comprising a receiver of a selective paging system.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
US392872A 1972-09-21 1973-08-30 Code programming device Expired - Lifetime US3876982A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7212750.A NL159515B (nl) 1972-09-21 1972-09-21 Binaire pulspatroongenerator.

Publications (1)

Publication Number Publication Date
US3876982A true US3876982A (en) 1975-04-08

Family

ID=19816980

Family Applications (1)

Application Number Title Priority Date Filing Date
US392872A Expired - Lifetime US3876982A (en) 1972-09-21 1973-08-30 Code programming device

Country Status (5)

Country Link
US (1) US3876982A (ro)
JP (1) JPS5441161B2 (ro)
FR (1) FR2205226A5 (ro)
GB (1) GB1446948A (ro)
NL (1) NL159515B (ro)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3925764A (en) * 1973-10-16 1975-12-09 Licentia Gmbh Memory device
US4244032A (en) * 1977-12-16 1981-01-06 Oliver Douglas E Apparatus for programming a PROM by propagating data words from an address bus to the PROM data terminals
US4663545A (en) * 1984-11-15 1987-05-05 Motorola, Inc. High speed state machine

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2838035B1 (fr) 2002-04-05 2006-11-03 Binsse Marie Laure Traux Tablette de support de produits, et meuble la comportant

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2864557A (en) * 1954-12-13 1958-12-16 Gen Electric Number converter
US3171098A (en) * 1961-02-08 1965-02-23 Motorola Inc Binary selective calling system
US3252142A (en) * 1962-09-10 1966-05-17 Codamite Corp Code receiver responsive to plural binary sub-group
US3309670A (en) * 1963-05-29 1967-03-14 Bell Telephone Labor Inc Selective signaling receiver
US3659154A (en) * 1970-01-05 1972-04-25 Steven G Finn Electronic lock and alarm system
US3686659A (en) * 1970-01-05 1972-08-22 Dasy Int Sa Electronic locking device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2864557A (en) * 1954-12-13 1958-12-16 Gen Electric Number converter
US3171098A (en) * 1961-02-08 1965-02-23 Motorola Inc Binary selective calling system
US3252142A (en) * 1962-09-10 1966-05-17 Codamite Corp Code receiver responsive to plural binary sub-group
US3309670A (en) * 1963-05-29 1967-03-14 Bell Telephone Labor Inc Selective signaling receiver
US3659154A (en) * 1970-01-05 1972-04-25 Steven G Finn Electronic lock and alarm system
US3686659A (en) * 1970-01-05 1972-08-22 Dasy Int Sa Electronic locking device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3925764A (en) * 1973-10-16 1975-12-09 Licentia Gmbh Memory device
US4244032A (en) * 1977-12-16 1981-01-06 Oliver Douglas E Apparatus for programming a PROM by propagating data words from an address bus to the PROM data terminals
US4663545A (en) * 1984-11-15 1987-05-05 Motorola, Inc. High speed state machine

Also Published As

Publication number Publication date
DE2344148B2 (de) 1976-06-10
DE2344148A1 (de) 1974-03-28
GB1446948A (en) 1976-08-18
NL7212750A (ro) 1974-03-25
JPS5441161B2 (ro) 1979-12-07
NL159515B (nl) 1979-02-15
JPS4971801A (ro) 1974-07-11
FR2205226A5 (ro) 1974-05-24

Similar Documents

Publication Publication Date Title
US3470542A (en) Modular system design
US6665769B2 (en) Method and apparatus for dynamically masking an N-bit memory array having individually programmable cells
JPH04293144A (ja) コンピュータシステム
US3961138A (en) Asynchronous bit-serial data receiver
GB2076189A (en) Multiprocessor computer system for executing a recursive algorithm
US4114138A (en) Selective calling circuit
KR840001731A (ko) 순차적인 워어드가 정열된 어드레스 지정장치
US3876982A (en) Code programming device
US3911218A (en) Time division information transmitting and receiving systems
US3624292A (en) Communication system including an answer-back message generator and keyboard
US4229802A (en) Digital adding device
US3798617A (en) Permanent storage memory and means for addressing
JP2001229688A (ja) メモリアプリケーション用のハイブリッドデータｉ／ｏ
JPS643413B2 (ro)
US4961159A (en) Cellular automaton for generating random data
US3993980A (en) System for hard wiring information into integrated circuit elements
US3201519A (en) Automatic telephone exchanges having a subscriber's memory
JPS60121588A (ja) デイジタル符号検出回路
US4791552A (en) Apparatus and method for addressing semiconductor arrays in a main memory unit on consecutive system clock cycles
US5274220A (en) Data carrier
US4061884A (en) Arrangement for controlling thyristor networks
CA1091779A (en) Input grouping arrangement for data gathering
JPS5847461Y2 (ja) ワ−ド連結用デイジタル出力器
US3192480A (en) Compatibility circuit for accommodating machines of different memory storage capacities employing pentode as gated-amplifier
SU1020989A1 (ru) Программируема логическа матрица