US3875562A - Electronic selector having a number of inlets and an equal number of outlets for exchange of analog or digital signals - Google Patents

Electronic selector having a number of inlets and an equal number of outlets for exchange of analog or digital signals Download PDF

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Publication number
US3875562A
US3875562A US359311A US35931173A US3875562A US 3875562 A US3875562 A US 3875562A US 359311 A US359311 A US 359311A US 35931173 A US35931173 A US 35931173A US 3875562 A US3875562 A US 3875562A
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Prior art keywords
shift
shift register
pulse
selector
input
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US359311A
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English (en)
Inventor
Goran Anders Henrik Hemdal
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Telefonaktiebolaget LM Ericsson AB
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Telefonaktiebolaget LM Ericsson AB
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Definitions

  • I972 Sweden 7056/72 Cally and sequentially activates the first stages, 80 that each PAM or PCM unit of information appearing on I52] US.
  • CI- 340/166, 340/168 SR an inlet is stored in the first stage.
  • the selector also 1 1] Int. Cl.
  • H04 3/00 contains a selector outlet control unit which n dep rr 8] Field of Search 340/166 R, I47 C, 168 SR; dence on a marker, cyclically activates a predeter- 179 3 233 1505 mined one of the second stages, so that the informa tion stored in the first stage is transferred to the prede- [56] References Cit d termined second stage and thereby to the desired out- UNITED STATES PATENTS M of the selector- 3694580 M972 Inosc .r 340/!66 X 6 Claims, 2 Drawing Figures SHIFT 0 sum REG. REG 0;
  • the present invention relates to an electronic selector having a number of inlets and an preferably equal number of outlets for the exchange or switching of analog or digital signals such as pulse amplitude modulated (PAM) or pulse code modulated (PCM) signals.
  • PAM pulse amplitude modulated
  • PCM pulse code modulated
  • the electronic selectors are more and more being used instead of utilizing mechanical switching elements.
  • the electronic utilize devices such as transistors. flip-flop circuits, gate circuits and integrated design of these devices because of the still more increasing need of high-speed selectors.
  • the present invention relates to a selector of the kind in which a shift register known per se for analog or digital signals is used.
  • the object of the present invention is an electronic selector, which can transfer analog as well as digital signals from a number of inlets to an equal number of outlets without blocking, by means of inexpensive, simple and highspeed switching elements.
  • FIG. 1 shows a circuit diagram for an electronic selector according to the present invention
  • FIG. 2 shows a timing diagram for certain control pulses which are supplied to the selector according to FIG. 1.
  • the selector according to FIG. 1 has a number of n inlets lI-ln and an equal number of outlets l-0n. It is now assumed that a number of pulse amplitude modulated time division multiplex signals are to be transferred by the selector from each of the inlets ll-In to a predetermined one of the outlets 01-0".
  • the signals have been sampled in a manner known per se so that they consist of voltage pulses whose amplitudes correspond to the instaneous amplitude of the signal in the sampling time. These voltage pulses are fed consecutively to the inlets ll-ln.
  • Each of the inlets Il-ln is connected to a corresponding outlet (II-0n through an analog shift register consisting of two stages BII, B21, B12, B22 and soon.
  • the analog shift registcr comprising stages Bll and B12 connect inlet I1 to outlet 01.
  • the junction points between the first and the second stages are connected together to a common connection point 0.
  • shift pulses are to be delivered to the shift register stages, so that a signal supplied to one of the inlets ll-ln can be transferred to a specific outlet 01-011.
  • the first shift register stages 811 to Bln are connected via the opening control gates GII-Gln, respectively, to an inlet control unit comprising a decoder AVKI and a binary counter BR.
  • the counter BR is stepped forward by clock pulses on its inlet X.
  • the outlet signals from the counter are fed from the decoder AVKI to the opening control gates GIl-Gln.
  • the opening state of of the gates is controlled by clock pulses on a common inlet Y.
  • the clock pulses on the inlet X are shown in FIG. 2, line a. These pulses step the counter BR forward and consequently the decoder AVKI, as is indicated on line d. On line b the clock pulses on the inlet Y are indicated. Within the time interval between two clock pulses on the inlet X, which step the binary counter BR, a clock pulse according to FIG. 2, line I), should appear. Such clock pulse as an opening pulse is fed to the gates GIl-Gln, so that shift pulses could be delivered from the decoder AVKl to the first stage in the respective analog shift register. Within the same interval, when the clock pulses ac cording to FIG. 2, line b, have ceased, also clock pulses according to FIG.
  • the decoder AVK] consists. for example, of a binary-to-decimal converter, the activation of a certain binary state of the outlets l-m of the binary counter BR causing an outlet conductor of the decoder having the corresponding decimal order number 1-11 to be selected and activated.
  • the number of outlets from the binary counter BR is assumed to be equal to m and the number of outlets of the decoder AVKl is assumed to be equal to the number of inlets and outlets of the selector. For each clock signal fed to the inlet X the outlets of the counter BR thus are activated.
  • counter BR is a binary counter which counts modulo 2'.
  • the outlet conductors l-n of the decoder AVKI are selected and for each opening control pulse at the inlet Y, one of the gates GIl-Gln will transfer a shift pulse through to associated first shift register stage Bil-Bln, If an analog shift register of such a known type is used, in which for the stepping of a unit of information two pulses with opposite polarity must be fed simultaneously to the shift register stages, the shift pulse can be fed directly as well as via an inverting circuit.
  • an outlet control unit which controls the shift register stages 821-8212.
  • This unit contains registers llRl-llRn. each of which is associated with one of the inlets.
  • Each register stores in the form ofa binary word the address of which of the shift register stages B21- 82): is to receive the unit of information to be transferred within a decoder period during which such information has been received by to the first stage in the analog shift registers.
  • the recording of the addresses in the registers ORI-()Rn takes place in a manner known per se from a marker M.
  • Each of the addresses in the registers ORI-0R are fed via one of the sets of AND- gate GI I-Glm. G2l-G2m, GnI-Gnm to the m inlets of a decoder AVKZ. Decoder AVKZ is similar to the decoder AVKl and converts the binary words representing the addresses at the inlets l-m to a decimal number, so that one of its outlets l-n will be activated.
  • One inlet of each of the opening gates is connected to the outlets of the decoder AVKZ and the other inlet of the opening gates is connected to a common inlet Z. Open pulses according to FIG. 2.
  • line I. are fed common in Z the analog information from the first shift reg ister stages is shifted to desired selector outlet after the information has been stored in the first shift register stage and within one and the same decoder period.
  • each of the inlets ll-ln in the selector is selected consecutively.
  • the transfer ofthe value. which will thereby be stored in the respective shift register stages Bl l-Bla and which represents a sampled value of a pulse amplitude modulated signal (or a digital value of a pulse code modulated signal). occurs by means of the analog shift registers between the inlets and the outlets of whose selector. the registers operate according to the principle of the known analog shift register.
  • the operation of the selector can briefly be summed up as follows.
  • the incoming pulses at the inlet X step the counter BR forward and the pulses at the inlets Y and Z open the gates Gll-Gln and the gates G01- Glln. respectively. within the same decoder period as it has been described above.
  • Starting from the zero position ofthe counter BR. first the outlet 1 of the decoder AYKI is selected and. after that, the outlets 2. n.
  • a shift pulse to the stage Bll will appear when the inlet Y is activated and the analog information appearing on the inlet II is stored in the stage Bll.
  • the binary information then at the gates GI l-Glm is fed to the decoder AVKZ.
  • the gate G02 is opened and a shift pulse is delivered to the stage B22.
  • the described selector operates not only for pulse amplitude modulated signals (PAM) but also for pulse code modulated signals (PCM
  • PCM pulse code modulated signals
  • all the bits in the PCM code can be transferred in series across one single selector or there could be connected in parallel so many selectors as there are bits in a PCM word. for example 8, and transfer will be in parallel.
  • the size of the selector is limited by the used maximal shift frequency and by the selected sampling frequency in the pulse code modulation.
  • An electronic selector for transferring information represented by a given parameter of information pulse signal from one of a plurality of inputs to one of a plurality of outputs comprising: a first plurality of stages, each of said stages temporarily storing a pulse signal and shift register having an information signal input, an information signal output and a shift pulse input; means for connecting the information signal input of each of said shift register stages to one of the inputs of the selector.
  • a common channel means for com necting the information signal output of all of said shift register stages to said common first control channel; means for transmitting first shift pulses having a first phase to the shift pulse input of each of the first plural ity of shift register stages in sequence whereby each said stage accepts and stores the information pulse signal then present at its information signal input; a second plurality of shift register stages for temporarily storing a pulse signal, each having an information signal input. an information signal output and a shift pulse input; means for connecting each of the information signal inputs of said shift register stages ofsaid second plurality to said common channel; means for connecting the information signal output of each of said shift register stages of said second plurality to one of the outputs of the selector.
  • a second control means operating in synchronism with said first means. for transmitting second shift pulses having a second phase delayed from said first phase to each of the shift register stages of said second plurality in a given sequence whereby the shift register stage receiving a second shift pulse accepts and stores the pulse signal for the shift register stage of said first plurality which received the first shift pulse immediately preceding said second shift pulse.
  • each of said shift register stages is an analog shift register stage.
  • said second control means includes aa register means for storing infor mation for selecting each of the shift registers of said second plurality.
  • read out means activated by each of said first shift pulses for extracting the information from said register means for selecting a particular shift register stage of said second plurality, and means con nected to said read out means for transferring the second shift pulse to said particular shift register stage of said second plurality.
  • said first control means comprises a clock pulse source. a modulo-n clock pulse counter where n equals the number of shift register stages in said first plurality.
  • first decoder means connected to said counter for converting the count being stored in said modulo-n counter to a signal on one of a plurality offirst lines.
  • a source of said first shift pulses. a plurality of two-input AND-gates. each of said AND-gates having a first input connected to said source of said first shift pulses and a second input connected to a different one of said first lines.
  • register means is a plurality of registers each storing an address word indicating one of the shift register stages of said second plurality.
  • second decoder means having a plurality of inputs for converting an address word present at the inputs to a signal on one of a plurality of second lines, means connected to each of said first lines for connecting a different one of said registers to said second decoder means. the particular register so connected being dependent on which of said first lines transmits a signal.
  • each of the AND-gates of said second plurality having a first input connected to said source of said second shift pulses and a second input connected to a different one of said second lines.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Electronic Switches (AREA)
  • Analogue/Digital Conversion (AREA)
  • Logic Circuits (AREA)
  • Control Of Transmission Device (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
US359311A 1972-05-30 1973-05-11 Electronic selector having a number of inlets and an equal number of outlets for exchange of analog or digital signals Expired - Lifetime US3875562A (en)

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SE07056/72A SE354765B (es) 1972-05-30 1972-05-30

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US3875562A true US3875562A (en) 1975-04-01

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US (1) US3875562A (es)
JP (1) JPS4957707A (es)
BE (1) BE800300A (es)
CA (1) CA1002640A (es)
DE (1) DE2326933B2 (es)
ES (1) ES415333A1 (es)
FR (1) FR2186797B1 (es)
GB (1) GB1428805A (es)
IT (1) IT988742B (es)
NL (1) NL7307192A (es)
SE (1) SE354765B (es)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3694580A (en) * 1971-07-28 1972-09-26 Bell Telephone Labor Inc Time division switching system
US3708626A (en) * 1969-10-27 1973-01-02 Siemens Ag Switching center for pcm-{11 time multiplex telephone network

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3708626A (en) * 1969-10-27 1973-01-02 Siemens Ag Switching center for pcm-{11 time multiplex telephone network
US3694580A (en) * 1971-07-28 1972-09-26 Bell Telephone Labor Inc Time division switching system

Also Published As

Publication number Publication date
BE800300A (fr) 1973-09-17
FR2186797A1 (es) 1974-01-11
AU5555273A (en) 1974-11-14
SE354765B (es) 1973-03-19
CA1002640A (en) 1976-12-28
DE2326933A1 (de) 1973-12-13
GB1428805A (en) 1976-03-17
NL7307192A (es) 1973-12-04
DE2326933B2 (de) 1976-07-29
JPS4957707A (es) 1974-06-05
ES415333A1 (es) 1976-02-01
FR2186797B1 (es) 1980-03-07
IT988742B (it) 1975-04-30

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