US3852951A - Electronic correction - Google Patents

Electronic correction Download PDF

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Publication number
US3852951A
US3852951A US00378627A US37862773A US3852951A US 3852951 A US3852951 A US 3852951A US 00378627 A US00378627 A US 00378627A US 37862773 A US37862773 A US 37862773A US 3852951 A US3852951 A US 3852951A
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United States
Prior art keywords
sequence
time
switch
piece
bistable
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Expired - Lifetime
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US00378627A
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English (en)
Inventor
P Sauthier
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SSIH Management Services SA
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SSIH Management Services SA
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G5/00—Setting, i.e. correcting or changing, the time-indication
    • G04G5/02—Setting, i.e. correcting or changing, the time-indication by temporarily changing the number of pulses per unit time, e.g. quick-feed method

Definitions

  • the advantage of the present invention from the viewpointat least of the user is that both addition and subtraction of seconds to or from the display may be effected by a single control switch which may take the form of a push-button for example.
  • a single control switch which may take the form of a push-button for example.
  • add seconds the user pushes the button once for each second he desires to add.
  • subtract seconds the user pushes the button and holds it depressed whereupon initially a second is added and thereafter further transmission of signals from the time standard to the display are blocked so that the user may subtract as many seconds from the indication of the display as circumstances warrant.
  • the invention provides a time-piece in which a time standard supplies signals of a predetermined frequency to a first sequence of bistable devices arranged and adapted to provide output signals ofa desired frequency to a display arrangement in which at least seconds are displayed, wherein means are provided to set the seconds display through the supplying of additional output signals or the withholding of output signals, said means including a complement output terminal on at leastone of the bistable devices in the first sequence, a bistable storage device arranged to be manually switchable to a first stable state and to be automatically restored to a second stable state by signals obtained from the complement Output terminal, a display control toggle having an input arrangement which logically combines said output signals from the first sequence of bistable devices with signals from the bistable storage device, a delaycircuit having a controllable disabling switch and receiving an input from a predetermined bistable device in the first sequence in order to provide an output adapted to block signal transmission from at least one bistable device in the first sequence and a manually operable switch coupled to the bistable storage device and the delay circuit
  • FIG. 1 represents a schematic lay-out of the logic of ing of the present invention
  • FIG. 2 is a timing diagram relating to the transmission of signals in the circuit of FIG. 1,
  • FIG. 3 represents a simplified variant of the version of the invention shown in FIG. 1,
  • FIG. 4 is a timing diagram relating to FIG. 3,
  • FIG. 5 shows a typical circuit which might be used for the bistable devices in the counter sequences.
  • the basic arrangement is similar to that of FIG. 1 of my above mentioned earlier patent application in so far as the addition of seconds is concerned.
  • the present invention shows one of the more difficult arrangements in which a stepping motor is used to drive the display and the stepping motor requires successive drive pulses of opposite polarity.
  • the stepping motor is arranged in a conventional manner to drive time indicating hands. It will be however obvious that the principle of the correction control as taught by the present patent application is equally applicable to a less complex situation which may be provided by other displays.
  • the motor control circuit must provide a change of direction of the current in the winding at each step.
  • the operation to be carried out acts on the logic.
  • Such delay should be greater than the time necessary for theaddition ofa second by a normal actuation of the switch, but as short as possible and in any event shorter than 1 second. A reasonable delay would seem to be from A to /2 a second.
  • delay T may be effected by analogue methods (integration of a current in a capacitor) or digital methods (counters).
  • analogue methods integration of a current in a capacitor
  • digital methods counters
  • stage 11 as shown for purposes of illustration in FIG. 1 is clamped and this suspends the counting action of stages further down the chain and thus suppresses current pulses in the motor.
  • This arrangement may however present a disadvantage should one wish to effect a simple subtraction of seconds.
  • resetting the last five stages will bring about a change of state of the last stage 16 should it be in its odd stateO which will have as an effect the addition of a 2nd secnd at the end of T
  • This second addition is not foreseeable and for this reason causes greater difficulty since it is necessary to observe and count the added seconds" in order to calculate the subtraction time which might thus be n l or n 2 in order to subtract n-seconds.
  • Such a difficulty will practically never appear when only one of the stages is clamped on condition that such stage be at a relatively high frequency.
  • stage 9 in this particular arrangement would receive signals at a frequency of 128 Hz from the preceding part of the divider and stages 17 and 18 are set and reset alternately each second in order to control complementary transistor pairs 8;; S S S which in turn deliver pulses of alternatingdirection to the motor winding M.
  • Push-button P may be followed by an integrator stage I which is intended to suppress the electrical effect of the mechanical irregularities (bounces) of the pushbutton.
  • One actuation of push-button P will change the output state 6 of bistable storage device 19 from one to zero. This change .will have no effect on stage 16 since the type of circuit employed reacts only to positive-going pulses and it is only upon the arrival of a complement output from stage 12 that stage 19 thereafter produces a one-output to change the state of toggle 16 and subsequently add I second to the display. This part of the circuit will be seen to be practically identicalwith that shown in my earlier patent application.
  • the output signal from the push-button P following the integration stage I is also passed across an inverter N and it will be seen that normally the output from N will be a positive signal which serves to saturate transistor T and thereby disable the secondary sequence of dividers 20, 21, 22 and 23.
  • the output from inverter N will block transistor T, and stages 20, 21, 22 and 23 will no longer be inhibited. These stages will thus commence to count signals received from stage 10.
  • the leading edge of the the signalYfrom the complement output of stage 12 will have changed the state of bistable storage device 19 thereby, as previously explained, bringing about addition of I second to the display.
  • stages 20, 21, 22 and 23 will be reset to zero and the main divider (stages 9 to 18 as shown) will not be affected. Should however the push-button be actuated longer than T transistor T will saturate at the end of the delay period T and will remain saturated until the push-button P is released. When such release is effected it will cause a positive output from N thereby resetting stage 24 to zero and blocking stages 20, 21, 22 and 23. As long as T remains saturated stage 11 will be clamped. When stage 24 is reset, transistor T is switched off and stage 11 resumes its normal function.
  • stage 11 In integrated circuit technology such as complementary MOS it is possible to implant logical gates and in such instances the inhibition of stage 11 may be replaced by an AND-gate between stage 10 and stage 11 which will be enabled or disabled according to the state of stage 24, transistor T in this case being eliminated.
  • resistor R and transistor T may be used to clamp the last five stages of the divider circuit through actuation of, for example, the crown of the time-piece.
  • FIG. 2 The timing of the various switching changes for this version of the correction circuit is as illustrated in FIG. 2 in which the symbols Q represent outputs from the bistable stages. Accordingly. 6 represents complement outputs, P represents the actuation of the push-button P and I represents motor impulses. The dotted representations are those which would occur in the normal state of operation, i.e., in the event that the pushbutton was not actuated.
  • FIG. 3 shows a simplified version of the invention which has actually been reduced to practice. Reference numbers relating to similar elements are the same in both FIGS. 1 and 3. For a further simplification of the drawing transistors are not shown as such, but it will be understood for example that the switches S and S would comprise transistors according to the chosen integration technique. Elements not essential to the understanding of the logic have been omitted and the motor circuits are simply shown as a block M.
  • FIG. 1 and FIG. 3 The principal difference between FIG. 1 and FIG. 3 lies in the fact that only two dividers 20 and 21 are shown in the secondary sequence 21. These are provided with a self-latching circuit S the effect of which is to eliminate the need for the memory stage 24 of FIG. 1.
  • switch S is closed at the end of the delay period T and will remain closed until the push-button P is released.
  • P When P is released it will cause a positive output from N hereby clamping stages 19 and 20 and thus opening switch S This permits stage 13 to resume its normal function.
  • FIG. 4 I Timing of the circuit as shown in FIG. 3 is illustrated in FIG. 4 in which the suppressed motor pulses are shown by means of dotted outlines.
  • FIG. 5 shows how part of the logic of FIG. 3 might be actually realized and it will be appreciated from the nature of the bistable stages why it is that setting of the switch S will result in clamping bistable stage 13.
  • Time-piece in which a time standard supplies signals of a predetermined frequency to a first sequence of bistable devices arranged and adapted to provide output signals of a desired frequency to a display arrangement in which at least seconds are displayed, wherein means are provided to set the seconds display through the supplying of additional output signals or the withholding of output signals, said means including a complement output terminal on at least one of the bistable devices in the first sequence, a bistable storage device arranged to be manually switchable to a first stable state and to be automatically restored to'a second stable state by signals obtained from the complement output terminal, a display control toggle having an input arrangement which logically combines said output signals from the first sequence of bistable devices with signals from the bistable storage device, a delay circuit having a controllable disabling switch and receiving an input from a predetermined bistable device in the first sequence in order to provide an output adapted to block signal transmission from at least one bistable device in the first sequence; and a manually operable switch coupled to the bistable storage device and the delay circuit disabling switch, whereby
  • Time-piece as set forth in claim 1 wherein a further manually operated switch is provided arranged and adapted to clamp a predetermined number of bistable devices in the first sequence immediately preceding the display control toggle thereby to facilitate exact setting of the phase of output signals to the display arrangement.
  • Time-piece as set forth in claim 1 wherein the display arrangement comprises a stepping motor arranged to drive time indicating hands.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electromechanical Clocks (AREA)
  • Electric Clocks (AREA)
  • Control Of Stepping Motors (AREA)
US00378627A 1972-07-12 1973-07-12 Electronic correction Expired - Lifetime US3852951A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3257772A GB1399024A (en) 1972-07-12 1972-07-12 Electronic correction circuit in a timepiece

Publications (1)

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US3852951A true US3852951A (en) 1974-12-10

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US00378627A Expired - Lifetime US3852951A (en) 1972-07-12 1973-07-12 Electronic correction

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US (1) US3852951A (enrdf_load_html_response)
JP (1) JPS5441353B2 (enrdf_load_html_response)
CH (2) CH594931B (enrdf_load_html_response)
DE (1) DE2336328C2 (enrdf_load_html_response)
GB (1) GB1399024A (enrdf_load_html_response)

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3906256A (en) * 1974-03-09 1975-09-16 Tokyo Shibaura Electric Co Drive pulse generator for use in electronic analog display clock apparatus
US3988597A (en) * 1975-01-31 1976-10-26 Tokyo Shibaura Electric Co., Ltd. Time correction circuits for electronic timepieces
US4020626A (en) * 1974-05-14 1977-05-03 Kabushiki Kaisha Daini Seikosha Electronic timepiece
US4043111A (en) * 1974-10-18 1977-08-23 Hitachi, Ltd. Indicated time-correcting device of digital display timepiece
US4059955A (en) * 1975-11-12 1977-11-29 Intersil, Inc. One button digital watch and method of setting the display
US4068462A (en) * 1976-05-17 1978-01-17 Fairchild Camera And Instrument Corporation Frequency adjustment circuit
US4083176A (en) * 1975-04-03 1978-04-11 Kabushiki Kaisha Daini Seikosha Time correcting system for electronic timepiece
US4092820A (en) * 1975-03-25 1978-06-06 Citizen Watch Company Limited Electronic timepiece
US4092822A (en) * 1974-12-11 1978-06-06 Ebauches Sa Control device for an electronic wrist-watch
US4133169A (en) * 1974-08-30 1979-01-09 Ebauches S.A. Electronic circuit for a quartz crystal watch
US4141208A (en) * 1976-01-19 1979-02-27 Hughes Aircraft Company Digitally tuned timepiece
US4150536A (en) * 1976-01-28 1979-04-24 Citizen Watch Company Limited Electronic timepiece
US4176515A (en) * 1976-10-09 1979-12-04 Quarz-Zeit Ag Electronic clock, particularly a quartz clock
US4185453A (en) * 1976-10-25 1980-01-29 Societe Suisse Pour L'industrie Horlogere Management Services S.A. Time setting and correcting circuit for electronic timepieces
US4209970A (en) * 1975-03-25 1980-07-01 Citizen Watch Co., Ltd. Electronic timepiece
US4232384A (en) * 1976-02-23 1980-11-04 Societe Suisse Pour L'industrie Horlogere Management Services S.A. Timesetting arrangement for electrical timepieces
US4254494A (en) * 1975-01-31 1981-03-03 Sharp Kabushiki Kaisha Accuracy correction in an electronic timepiece
US4255802A (en) * 1977-11-29 1981-03-10 Citizen Watch Company Limited Electronic timepiece
US4261048A (en) * 1975-12-25 1981-04-07 Citizen Watch Company Limited Analog quartz timepiece
US20040100873A1 (en) * 2002-11-26 2004-05-27 Samsung Electronics Co., Ltd. Apparatus and method for adjusting time in a terminal with built-in analog watch

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3622681A1 (de) * 1986-07-05 1988-01-21 Diehl Gmbh & Co Elektronische uhr mit einer digitalanzeige
US5015564A (en) * 1988-12-23 1991-05-14 Eastman Kodak Company Stabilizatin of precipitated dispersions of hydrophobic couplers, surfactants and polymers
US5087554A (en) * 1990-06-27 1992-02-11 Eastman Kodak Company Stabilization of precipitated dispersions of hydrophobic couplers

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3672155A (en) * 1970-05-06 1972-06-27 Hamilton Watch Co Solid state watch
US3765163A (en) * 1972-03-17 1973-10-16 Uranus Electronics Electronic timepiece

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4857678A (enrdf_load_html_response) * 1971-11-18 1973-08-13

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3672155A (en) * 1970-05-06 1972-06-27 Hamilton Watch Co Solid state watch
US3765163A (en) * 1972-03-17 1973-10-16 Uranus Electronics Electronic timepiece

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3906256A (en) * 1974-03-09 1975-09-16 Tokyo Shibaura Electric Co Drive pulse generator for use in electronic analog display clock apparatus
US4020626A (en) * 1974-05-14 1977-05-03 Kabushiki Kaisha Daini Seikosha Electronic timepiece
US4133169A (en) * 1974-08-30 1979-01-09 Ebauches S.A. Electronic circuit for a quartz crystal watch
US4043111A (en) * 1974-10-18 1977-08-23 Hitachi, Ltd. Indicated time-correcting device of digital display timepiece
US4092822A (en) * 1974-12-11 1978-06-06 Ebauches Sa Control device for an electronic wrist-watch
US4254494A (en) * 1975-01-31 1981-03-03 Sharp Kabushiki Kaisha Accuracy correction in an electronic timepiece
US3988597A (en) * 1975-01-31 1976-10-26 Tokyo Shibaura Electric Co., Ltd. Time correction circuits for electronic timepieces
US4092820A (en) * 1975-03-25 1978-06-06 Citizen Watch Company Limited Electronic timepiece
US4209970A (en) * 1975-03-25 1980-07-01 Citizen Watch Co., Ltd. Electronic timepiece
US4083176A (en) * 1975-04-03 1978-04-11 Kabushiki Kaisha Daini Seikosha Time correcting system for electronic timepiece
US4059955A (en) * 1975-11-12 1977-11-29 Intersil, Inc. One button digital watch and method of setting the display
US4261048A (en) * 1975-12-25 1981-04-07 Citizen Watch Company Limited Analog quartz timepiece
US4141208A (en) * 1976-01-19 1979-02-27 Hughes Aircraft Company Digitally tuned timepiece
US4150536A (en) * 1976-01-28 1979-04-24 Citizen Watch Company Limited Electronic timepiece
US4232384A (en) * 1976-02-23 1980-11-04 Societe Suisse Pour L'industrie Horlogere Management Services S.A. Timesetting arrangement for electrical timepieces
US4068462A (en) * 1976-05-17 1978-01-17 Fairchild Camera And Instrument Corporation Frequency adjustment circuit
US4176515A (en) * 1976-10-09 1979-12-04 Quarz-Zeit Ag Electronic clock, particularly a quartz clock
US4185453A (en) * 1976-10-25 1980-01-29 Societe Suisse Pour L'industrie Horlogere Management Services S.A. Time setting and correcting circuit for electronic timepieces
US4255802A (en) * 1977-11-29 1981-03-10 Citizen Watch Company Limited Electronic timepiece
US20040100873A1 (en) * 2002-11-26 2004-05-27 Samsung Electronics Co., Ltd. Apparatus and method for adjusting time in a terminal with built-in analog watch
EP1424612A3 (en) * 2002-11-26 2007-11-07 Samsung Electronics Co., Ltd. Apparatus and method for adjusting time in a terminal with built-in analog watch

Also Published As

Publication number Publication date
DE2336328A1 (de) 1974-01-31
GB1399024A (en) 1975-06-25
JPS4953874A (enrdf_load_html_response) 1974-05-25
CH1001573A4 (enrdf_load_html_response) 1977-04-29
DE2336328C2 (de) 1982-06-24
JPS5441353B2 (enrdf_load_html_response) 1979-12-07
CH594931B (de) 1978-01-31

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