US3846757A

US3846757A - Equal probability selection circuit

Info

Publication number: US3846757A
Application number: US00387195A
Authority: US
Inventors: D Friedman
Original assignee: Individual
Current assignee: Individual
Priority date: 1972-11-29
Filing date: 1973-08-09
Publication date: 1974-11-05
Anticipated expiration: 1991-11-05
Also published as: AU6130773A; GB1436364A; JPS4978458A

Abstract

The invention relates to a circuit which permits selecting any one of N unique selection intersections with equal probability. The selection intersections comprise a switch matrix with N switches, each switch comprising a selection intersection. The circuit consists of a clock circuit means with a low frequency and a high frequency output, and a counter circuit driven by the output. The counter circuit drives the switch matrix, and the high frequency output is applied to the counter only during a low output of the matrix. The counter has two sets of outputs, each one connected to a different axis of the matrix. Thus, after each count, a different intersection of the matrix is selected. The selected intersection is the one corresponding to the last count.

Description

United States Patent 1 1 Friedman 1 EQUAL PROBABILITY SELECTION CIRCUIT [76] Inventor: David Warren Friedman, No. 30-152 chome Kakinokizaka. Meguro-ku, Tokyo, Japan [22] Filed: Aug. 9, 1973 [21] Appl. No.: 387,195

Foreign Application Priority Data Nov. 29, 1972 Japan 47-119498 [52] U.S. Cl. 340/166 R, 340/147 R [51] Int. Cl. H04q 3/00 [58] Field-of Search 340/166 R, 147 R [56] References Cited UNITED STATES PATENTS 3,629,610 11/1971 Warring ..L 340/166 R Nov. 5, 1974 Primary Examiner-Harold I. Pitts Attorney, Agent, or F irmWenderoth, Lind and Ponack 7] ABSTRACT The invention relates to a circuit which permits selecting any one of N unique selection intersections with equal probability. The selection intersections comprise a switch matrix with N switches, each switch comprising a selection intersection. The circuit consists of a clock circuit means with a low frequency and a high frequency output, and a counter circuit driven by the output. The counter circuit drives the switch matrix, and the high frequency output is applied to the counter only during a low output of the matrix. The counter has two sets of outputs, each one connected to a different axis of the matrix. Thus, after each count, a different intersection of the matrix is selected. The selected intersection is the one corresponding to the last count.

15 Claims, 5 Drawing Figures PATENTEDNUV 5mm 3,846,757

SHEET 1-0? 3 ssvv I 2 3 13 ELECTRONIC SWITCH 7 CLOCK L 8% J E MATRIX 12 CIRCUIT CIRCUIT.

a FEED-BACK N 4 CIRCUIT LOW FREQUENCY CLOCK MlS-SELECTION PREVENTION a; 5 6 CIRCUIT v H9 8 3 'l2 -m=:SELECTlON 1 MIN MU NHIBW REQUEST w CIRCUIT V T MEMORY a C NTROL CIRCUIT CRCUT I CRCUIT I B HIGH WW ggggg V CIRCUIT 10 I4 f v f 7 LOW. ,"LL. PULSE i FORMING R CIRCUIT I62 I FA J'LJ'L. L CT, FIG} EQUAL- PROBABILITY SELECTION CIRCUIT BACKGROUND OF THE INVENTION This invention relates to an electronic selection circuit which is capable of having one or more once selected selection intersections removed from a group of N selection intersections by utilizing electronic circuit means and further is capable of selecting the unremoved' selection intersections with equal probability, and in more detailed description, relates to -an equal probability selection circuit including a specially controlled electronic clock circuit, a counter circuit driven by the said clock circuit, a switch matrix circuit driven by the said counter circuit having N unique intersecting points corresponding to N unique selection intersections numbered with N unique numbers and having a characteristic which allows removal of any number or all of the N selection intersections, and a feedback circuit driven by the aforesaid switch matrix circuit, all arranged such that the probability of selecting any one of.

the unremoved selection intersections is'equal to the probability of acquiring any other one without regard to the number of selection intersections already removed and also arranged in the form of a single cycle selection system involving the maximum number of selection intersections and where the probability of acquiring any one of the already removed selection intersections is zero.

The object of this invention is to provide an electronic circuit constructed such that it is possible to remove selection intersections once selected so as to reduce the number of possible objects remaining to be selected thereafter and also to make these selections with equal probability, and its main purpose is to obtain a circuit capable of selecting from among N unique selection intersections, consisting of an electronic clock circuit including a minimum time control circuit capable of controlling the minimum operation time of the selection start switch and two clock circuits, where the frequencies of both a high frequency circuit and a low frequency circuit are sufficiently higher than N cycles per second, a counter circuit driven by aforesaid electronic clock circuit and producing a set of N unique predetermined selection intersections, a switch matrix circuit driven by said counter circuit and having N unique intersecting points each corresponding to a unique selection intersection and each numbered with one of N unique numbers having such characteristics which allows removal of (N-M) selection intersections among the. N selection intersections, and a feedback circuit driven by said switch matrix circuit, wherein the output of the aforesaid low frequency clock circuit is selected as the output of the above-mentioned electronic clock circuit and allows selection of one of the selection intersections only when predetermined conditions exist. and a feedback control signal can control the aforementioned electronic clock circuit so as to select the output of the above-mentioned high frequency clockcircuit as the output of the above-mentioned electronic clock circuit at times when the selection intersection has already been removed inthe aforesaid switch matrix circuit, arranged such that the probability of selecting any one of a group of M selection intersections which have not yet been removed is essenitally equal to the probability of selecting any other one and additionally such that the (NM) selectionintersections which have already been removed may not be selected again.

DESCRIPTION OF THE DRAWINGS Preferred embodiments of the invention will be described hereunder referring to the attached drawings, in which:

FIG. 1 shows a block diagram of the whole circuit in an embodiment of the present invention;

FIG. 2'shows a more detailed block diagram of the electronic clock circuit 1 in FIG. I;

FIG. 3 shows a wiring diagram of an example of a typical astable multivibrator circuit used in clock circuit A;

FIG. 4'shows the entire circuit diagram of an embodiment of the equal probability selection circuit of the present invention; and

FIG. 5 shows a timing signal diagram of the outputs of each principal circuit as occurs in the case of performing selection using the equal probability selection circuit of the present invention.

DESCRIPTION OF THE EMBODIMENTS SHOWN HEREIN FIG. I shows an entire circuit containing N unique selection intersections in accordance with the present invention. 1 is an electronic clock circuit, its output being connected to a counter circuit 2 and further the counter 2 to a switch matrix-circuit 3 and the matrix 3 to a feedback circuit 4 and the feedback circuit 4 to the electronic clock circuit 1, The entire cireuit is activated by means of an input control signal 12 from the selection start switch SSW for the purpose of selecting one selection intersection, this selection made possible by a predetermined feedback control signal 14.

FIG. 2 shows a further detailed block diagram of the electronic clock circuit 1.

cal astable multivibrator circuit as used for clock circui't A is shown in FIG. 3. By establishing the values of capacitors C, and C two time constants, T, and T are determined and the frequency F is determined in this example as 1,000 cycles per second. The high frequency clock circuit B consists of another astable multivibrator circuit similar to clock circuit A where the two time constants, T and T are established so as to obtain a frequency F fulfilling the condition that F 2 NF In this embodiment the frequency F is a symmetrical squarewave having a frequency greater than 160,000 cycles per second. Further, both frequencies F and F are sufficiently greater than N cycles per second. In other words, even if any number of selection intersections or all N selection intersections are removed, it is feasable to obtain a series of selection intersections in a single cycle having such characteristics as to allow for such removals by setting the relation be- I tween frequencies F and F such that N pulses of the squarewave output of clock circuit B fall within one negative pulse (P) of the squarewave output of clock circuit A.

In this embodiment, N 80 selection intersections are produced in order to make use of a scale-of-S counter circuit and a scale-of-lo counter circuit combined in matrix form so as to obtain a continuous series of N 75 unique selection intersections by means of not using 5 of the 80 selection intersections. That is, nand gate 26 (FIG. 4) is not used.

Furthermore, since the use of the output of clock circuit B is prohibited during time delay I, l/F by means of a misselection prevention circuit 11, the following relationship is obtained:

F 2 X (75+5) X I000 160,000 c.p.s.

Clock circuits A and B are connected to a selection circuit 9 whose purpose is such that the output of either clock circuit A or clock circuit B or neither of the outputs of clock circuit A or clock circuit B may be correctly selected by means of the input control signal 12 and the predetermined feedback control signal 14. The selection circuit consists of nand gates l5, l6 and 17 (FIG. '4) with the output of clock circuit A being connected to the input of nand gate 15, the output of clock circuit B being connected to the input of nand gate 16, and the outputs of

nand gates

15 and 16 being connected to the input of nand gate 17. In addition, nand gate 17 has the output of an acquisition request memory circuit 8 applied to its input.

Referring again to FIG. 4, when the output of the acquisition request memory circuit 8 is 0, the output of nand gates 15 and 17 are'inhibited. That is, the outputs of nand gates 15 and 17 are 1 during this period.

When the output of the acquisition request memory circuit 8 is l and the output of resistor R21 is I, gate 15 is open to the output Aout of clock circuit A. Under these conditions, when the output Aout is l, the output ofnand gate 15 is 0, and when the output Aout is O, the output of nand gate 15 is 1. During this period the output of nand gate 16 is inhibited; that is its output is I.

In cases where the output of the acquistion request memory circuit 8 is l and the output of resistor R21 is O. and after the inhibit period 1,, l/F generated by the misselection prevention circuit following the l to 0 transition of output Aout. nand gate 16 is open to the output Bout of clock circuit B. At this time, when the output Bout is I. the output of nand gate 16 is O, and when the output Bout is 0, the output of nand gate 16 is l. During this period the output of nand gate 15 is I.

Nand gate 17 responds only when the output of either nand gate I5 or nand gate 16 is 0. Further, it is obvious that the output of nand gate 17 is in phase with output Aout or Bout of clock circuit A or B depending on which is being selected. Aout and Bout have no particular phase relationship at any time, in other words the signals Aout and Bout are asynchronous.

The misselection prevention circuit 11 is constructed in such a way that a capacitor C is connected between the output of clock circuit A and the input of nand gate 16. Capacitor C is discharged beginning when the output Aout makes a I to 0 transition and before the output of nand gate 16 could potentially make a l to 0 transition. lnother words, the object of-this circuit is to prohibit selection of output Bout of clock circuit B as 4 the output of nand gate 17 during the delay time of approximately l/F A pulse forming circuit 10 is connected to the output of nand gate 15 through capacitor C coupled to the input of inverter 18, the output of which is connected to the input of the acquisition circuit 7. When the output Aout of clock circuit A makes a O to 1 transition,

the output of nand gate 15 makes a I to 0 transition which coupled through capacitor C produces a negative pulse at the input of inverter 18. Thus, the output of inverter 18 provides a positive pulse to the input of the acquisition circuit 7 at the time immediately following a 0 to I transition of Aout.

The acquisition circuit 7 consists of nand gate 19, having three terminals on the input side and one terminal on the output side.

After the selection start switch SSW is operated and released the output ofinverter 5a of the minimum time control circuit 5 makes a 0 to I transition. When and if a selection intersection is selected at the same time or with a slight delay with respect to the O to l transition of inverter 5a, the output Aout will make a 0 to I transition and the output of the pulse forming circuit 10 will be a positive pulse and at this time the output of the acquisition circuit 7 makes a I to 0 transition which resets the acquisition request memory circuit 8. In other words, the operation of this circuit 7 is that of a monitor circuit whose purpose is to suspend the output 13 of the above-mentioned selection circuit 9 (i.e. the output of the electronic clock circuit 1) by resetting the said acquisition request memory circuit 8 and thereby suspending further operation of the counter circuit 2 when all the outputs of the inverter 5a, the resistor R21 and the pulse forming circuit 10 are l. The minimum time control circuit 5 consists of monostable multivibrator circuit comprising nand gate 5b, inverter 5a and capacitor C The said monostable multivibrator circuit is in a stable condition when the selection start switch SSW is in an ON or 0 condition or ordinarily OFF or I condition, but a pulse having a fixed pulse width is generated as the output of said minimum time control circuit 5 during the time capacitor C, is discharging. This prevents the possible rapid operation of selection start switch SSW from generating a very short pulse at the output of inverter 5a such that it is almost predictable that selection of closely following selection intersections would occur. In other words, the minimum operation time of selection start switch SSW can be controlled. Thus, it becomes feasible to always acquire the aforementioned selection intersection with essentially equal probability without any effect caused by the operating time of the selection start switch SSW.

The inhibit circuit 6 is provided for the purpose of preventing a further selection until the correct switch located at the intersecting point in the switch matrix circuit 3 is operated (i.e. open contacts) corresponding to the selection intersection to be removed. The circuit consists of nand gate 6b and inverter 6a. When the selection start switch SSW is ON or O in the process of selecting, the output ofnandgate 5b in the minimum time control circuit 5 is 1. Even if an operator who performs selection does not operate (i.e. open contacts) the switch, corresponding to the already selected selection intersection, by mistake and desires to perform selection, the lamps remain lit and the output of inverter 6a is 0 since the output of resistor R21 (i.e. the feedback control signal 14) is I, thus inhibiting the output of nand gate 612 (i.e. the output is held at 1). When the operator operates the switch corresponding to the already selected selection intersection, the feedback control signal 14 becomes and the output of inverter 6a becomes l. Accordingly, the output of nand gate 617 becomes 0. corresponding to the feedback control signal 14 during a time when the selection start switch SSW is ON or O. The acquisition request memory circuit 8 has the purpose of providing a resettable memory of one bit until the said acquisition request memory circuit 8 is set for the purpose of allowing operation of clock selection circuit 9, and comprises a set/reset flipflop consisting of nand gate 8:: and 8b. It is set such that the output of nand gate 8a becomes a 1 when the output of nand gate 612 is momentarily and is reset so as to obtain a 0 output from nand gate 8a when the output of the acquisition circuit 7 is momentarily 0.

P16. 4 shows the details of the counter circuit 2. The counter circuit 2 is driven by the electronic clock circuit 1, and consists of counter circuits X and Y constructed by using binary counter stages and decoders DX and DY, and is operated by the output 13 of the aforesaid electronic clock circuit 1. In FIG. 4, the counter circuit X consists of a three stage sequential type binary counter, stages B1, B2 and B3, and the outonly. Here. O1 and Q3 are the output logical values of the respective binary counter stages B1 and B3.

'The nand gates 21 through 25 constitute a decoder DX and usually have an output of l, but the output being selected at any moment has an output of 0. In FIG. 4. a counter circuit Y consists of four stages of binary counters connected in series B4 through B7, and 16 (i.e. 2 output combinations are possible so as to correspond to a series of unique selections which are mutually exclusive, but one combination is not used. Counter circuit Y is connected to the four each input terminals of nand gates 26 through 41, each gate having one output terminal. Nand gate 26 is not used as mentioned above. The output condition of counter circuit Y is similar to the output condition of counter circuit X previously mentioned.

Furthermore. the number of binary counter stages for counter circuits X and Y is appropriately determined depending'on the number of selection intersections N desired and the number of stages can be freely increased or decreased. The minimum number of stages is l, where it is logically possible to obtain N 7 In another embodiment, it is feasible to obtain N unique selection intersections even though the counter circuit is not constructed in matrix form.

Since the counter circuits X and Y divide the squarewave of the electronic clock selection circuit 1 by and 16 respectively, and a clock pulse is generated by means of a nand gate, they generate one decoder pulse each in such a way that the output pulses of decoders DX and DY are invariably in phase with each other at any one time.

The purpose of switch matrix circuit 3 is to provide memory for selection intersections already removed through selection, and consists of driving transistors TRl through TR5 and TR6 through TR20, resistors R1 through R5 and R6 through R20, diodes D1 through D75 and 75 switches S1 through S75, being driven by the aforementioned counter circuit 2 where selection I intersections are arranged by using one decoder pulse each from decoder DX and decoder DY corresponding to the above-mentioned N( N= in this embodiment) numbered intersections. Here, since the nand gate 26 is not used as described above, 1 X 5 5 intersections are not formed as selection intersections, but the feedback control signal 14 is O at such times and this causes output Bout to be selected as the output of the electronic clock circuit 1. Thus, 80 5 75, namely N 5 N is obtained, and N selection intersections are produced out of N intersections and are arranged at each point of intersection of the switch matrix circuit 3. Simultaneously, the switch matrix 3 should display which selection intersection is selected by some means such as a visible display using lamps as described in the time together with a decoder pulse from decoder DY corresponding to the aforesaid clock pulse, for example, in the case of nand gate 21 and nand gate 40, the current from the power supply B+ flows through lamp DSl, driving transistor TRl, switch S66, diode D66, driving transistor TRl9 and lamp DS19 to resistor R21. Thus, a potential difference is produced across resistor R21 and the feedback control signal 14 havinga 1 output is fed back to the aforesaid electronic clock circuit 1, because one end of resistor R21 is connected to ground. Diodes D1 through D75 are provided for the purpose of preventing the current from flowing through lamps other than the selected set.

Feedback circuit 4 consists of resistor R21 being driven by the above-mentioned switch matrix circuit 3 and is capable of transferring the memory of removed selection intersections to the electronic clock circuit 1- by means of the feedback control signal 14 such that selection may be feasible only when the output of said resistor R21 is l and the output of clock circuit A is in a predetermined output condition having just made a O to 1 transisition.

A detailed description of the mode of selection according to the equal probability selection circuit of the .present invention will be made hereafter.

Initially, all switches 81 through S75 of the switch A and B respectively. The current flowing through theselected selection intersection switch is then interrupted by operation of the appropriate switch (i.e. one of S1 through S75) in the switch matrix circuit 3 causing the feedback control signal to become which causes the output of inverter 6a to become 1 which enables nand gate 611. Next, when selection start switch SSW is operated ON in order to begin selection of any one of a series of selection intersections of a single cycle consisting of M selection intersections. The acquisition request memory circuit 8 is set which causes its output to change from 0 to l and the aforesaid nand gate 17 is enabled. Furthermore, since nand gate is inhibited, selection of squarewave F, becomes impossible and such a condition allowing selection of squarewave F is obtained. Squarewave F advances the counter circuit to the point where the next selection intersection not previously removed allows current to flow throughresistor R21 causing the feedback control signal'l4 to become 1 and thus inhibit nand gate 16 and enable nand gate 15 thereby selecting squarewave F, as the output 13 of nand gate 17 which is 0 at that time until the end of negative pulse P. This process is repeated many times while selection start switch SSW is held ON. Also, at the end of every negative pulse P when squarewave F and the output 13 of nand gate 17 make a 0 to 1 transition, the output of nand gate 15 makes a l to 0 transition which causes a positive pulse to appear at the output of inverter 18 through capacitor Next, depending on the operator, selection start switch SSW is released or placed OFF enabling one input of acquisition circuit 7.

When by means of either Fj, or F selection, the counter is advanced to a selection intersection not yet deleted causing feedback control signal 14 to become 1, another input of acquisition circuit 7 is enabled. Finally, at the end of negative pulse P, the output of inverter 18 provides a positive pulse fully enabling acquisition circuit 7 such that during the pulse time, the output of nand gate 19 becomes 0 resetting acquisition request memory circuit 8 output to 0 and in turn inhibiting the clock output 13 of clock selection circuit 1 thus completing the single selection cycle wherein a single selection intersection is selected. In other words, a series of selection intersections of a single cycle consisting of M cycles of squarewave Aout of clock circuit A is arranged in such a way that one of M unique selection intersections and the transition from O to l of Aout correspond to each other in every cycle.

Furthermore, since F 1000 c.p.s. and N 80, N 75 the probability of selecting any one of N selection intersections is substantially l/N, where F, in c.p.s. is sufficiently large with respect to N c.p.s. and also due to the operation of the minimum time control circuit 5, which is equal to the probability of selecting any other one of the N selection intersections and is also essentially independent of the number of selection intersections.

Further, since switches in the switch matrix circuit 3 corresponding to previously removed (N-M) selection intersections are OFF (i.e. open contacts) in the case where M selection intersections have not yet been removed, the current from the power supply B+ does not flow through the intersection point corresponding to the aforesaid selection intersection which has already been removed and the output across resistor R21 (i.e. the feedback control signal 14) is 0. Accordingly, the 1 input of nand gate 15 is changed to O and the 0 input of nand gate 16 is changed to 1, thus output Aout is inhibited and output Bout is selected as output 13 of the above-mentioned electronic clock circuit 1.

Also, since the frequency of clockcircuit B is F 2N'F,,, N cycles of Bout can be contained within the negative pulse portion P of the aforementioned clock circuit A and the 0 to 1 change of the output Aout is still obtained even if any number or totally all N selection intersections have been removed, and it is feasible to select selection intersections in any case. In other words, the switch matrix circuit 3 has such a characteristic that any number or the total number of selection intersections can be removed. Furthermore, the circuit is arranged such that selection is performed independently of the (N-M) selection intersections already removed and the probability of selecting any one selection intersection is l/M which is equal to the probability of selecting any other one, and further, so that the (N-M) selection intersections already removed are prevented from being selected again by means of the feedback control signal 14. Thus, it is feasible according to the present invention to perform selection successively with the same probability of selecting selection intersections numbered with predetermined N unique numbers among those selection intersections which have not yet been removed, and the present invention can be practically applied in the construction of bingo game number selection units as well as having wide application in other fields of equal probability selection.

1 claim:

1. An equal probability selection circuit allowing the selection of any one of N unique selection intersections with equal probability and comprising:

a selection start switch means;

clock circuit means, driven by said selection start switch, and having a low frequency output and a high frequency output;

counter circuit means, driven by the output of the clock circuit means, and having two sets of outputs;

a switch matrix, comprising N switches each switch comprising a selection intersection; each switch having two terminals, one terminal of each switch being connected to an output from one of the two sets of outputs of the counter circuit; the other terminal of each switch being connected to an output from the other of the two sets of outputs of the counter circuits; and

feedback circuit means receiving an output from said matrix when a selection intersection has been selected and providing, at that time, an output to the clock circuit to inhibit the high frequency output of the clock circuit.

2. A circuit as defined in claim 1 wherein said clock circuit means comprises a high frequency clock to provide said high frequency output and a low frequency clock, to provide said low frequency output;

the frequency of said low frequency clock being numerically greater than N;

the high frequency output being numerically greater than 2-(N)'(low frequency output).

3. A circuit as defined in claim 1 and further comprising an acquisition circuit to control the acquisition of a next selection intersection.

4. A circuit as defined in claim 1 and further comprising a misselection prevention circuit means to disconnect the clock circuit means from the counter circuit means for a delay time of l/(the high frequency output).

5. A circuit as defined in claim 2 and further comprising a misselection prevention circuit means to disconnect the clock circuit means from the counter circuit means for a delay time of l/(the high frequency output).

6. A circuit as defined in claim 3 and further comprising a misse'lection prevention circuit means to disconnect the clock circuit means from the counter circuit means for a delay time of l/(the high frequency output).

7. A circuit as defined in claim 1 wherein, when a selection intersection is selected, the intersection is removed by opening the switch associated with said intersection, whereby (N-M) intersections may be removed; t

the remaining M intersections being selectable with equal probability.

8. A circuit as defined in claim 2 wherein, when a selection intersection is selected, the intersection is removed by opening the switch associated with said intersection, whereby (N-M) intersections may be removed;

the remaining M intersections being selectable with equal probability.

9. A circuit as defined in claim 3 wherein, when a Se lection intersection is selected, the intersection is removed by opening the switch associated with said intersection, whereby (N-M) intersections may be removed;

the remaining M intersections being selectable with equal probability.

1.0. A circuit as defined in claim 1 and further com- 10 I prising inhibit circuit means for preventing the further selection of selection intersections until after a previously selected selection intersection, has been removed by opening the contacts of the switch corresponding to the previously selected selection intersection.

11. A circuit as defined in claim 2 and further comprising inhibit circuit means for preventing the further selection of selection intersections until after a previously selected selection intersection, has been removed by opening the contacts of the switch corresponding to the previously selected selection intersection.

12. A circuit as defined in claim 3 and further comprising inhibit circuit means for preventing the further' selection of selection intersections until after a previously selected selection intersection, has been removed by opening the contacts of the wsitch corresponding to the previously selected selection intersection.

13. A circuit as defined in claim 1 wherein one of the two sets of outputs of the counter circuit means comprises n outputs, and wherein the other of the two sets of outputs of the counter circuit means comprises n outputs; and wherein (n )'(n N.

14. A circuit as defined in claim 2 wherein one of the two sets of outputs of the counter circuit means comprises m outputs, and wherein the other of the two sets of outputs of the counter circuit means comprises in; outputs; and wherein (n )'(n N.

15. A circuit as defined in claim 3 wherein one of the two sets of outputs of the counter circuit means comprises n outputs, and wherein the other of the two sets of outputs of the counter circuit means comprises 11 UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,846,757 Dated November 5, 1974 In n (s) David Warren Friedman It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

On the first page of the patent, after the Inventors name, the address should be corrected to read as follows:

- No. 30-15, 2-chome Kakinokizaka, Meguro-ku,

Tokyo, Japan Signed and sealed this 3rd day of June 1975.

(SEAL) AtteSt:

C. MARSHALL DANN RUTH C. MASON Commissioner of Patents Attesting Officer and Trademarks

Claims

1. An equal probability selection circuit allowing the selection of any one of N unique selection intersections with equal probability and comprising: a selection start switch means; clock circuit means, driven by said selection start switch, and having a low frequency output and a high frequency output; counter circuit means, driven by the output of the clock circuit means, and having two sets of outputs; a switch matrix, comprising N switches each switch comprising a selection intersection; each switch having two terminals, one terminal of each switch being connected to an output from one of the two sets of outputs of the counter circuit; the other terminal of each switch being connected to an output from the other of the two sets of outputs of the counter circuits; and feedback circuit means receiving an output from said matrix when a selection intersection has been selected and providing, at that time, an output to the clock circuit to inhibit the high frequency output of the clock circuit.

2. A circuit as defined in claim 1 wherein said clock circuit means comprises a high frequency clock to provide said high frequency output and a low frequency clock, to provide said low frequency output; the frequency of said low frequency clock being numerically greater than N; the high frequency output being numerically greater than 2.(N).(low frequency output).

4. A circuit as defined in claim 1 and further comprising a misselection prevention circuit means to disconnect the clock circuit means from the counter circuit means for a delay time of 1/(the high frequency output).

5. A circuit as defined in claim 2 and further comprising a misselection prevention circuit means to disconnect the clock circuit means from the counter circuit means for a delay time of 1/(the high frequency output).

6. A circuit as defined in claim 3 and further comprising a misselection prevention circuit means to disconnect the clock circuit means from the counter circuit means for a delay time of 1/(the high frequency output).

7. A circuit as defined in claim 1 wherein, when a selection intersection is selected, the intersection is removed by opening the switch associated with said intersection, whereby (N-M) intersections may be removed; the remaining M intersections being selectable with equal probability.

8. A circuit as defined in claim 2 wherein, when a selection intersection is selected, the intersection is removed by opening the switch associated with said intersection, whereby (N-M) intersections may be removed; the remaining M intersections being selectable with equal probability.

9. A circuit as defined in claim 3 wherein, when a selection intersection is selected, the intersection is removed by opening the switch associated with said intersection, whereby (N-M) intersections may be removed; the remaining M intersections being selectable with equal probability.

10. A circuit as defined in claim 1 and further comprising inhibit circuit means for preventing the further selection of selection intersections until after a previously selected selection intersection, has been removed by opening the contacts of the switch corresponding to the previously selected selection intersection.

12. A circuit as defined in claim 3 and further comprising inhibit circuit means for preventing the further selection of selection intersections until after a previously selected selection intersection, has been removed by opening the contacts of the wsitch corresponding to the previously selected selection intersection.

13. A circuit as defined in claim 1 wherein one of the two sets of outputs of the counter circuit means comprises n1 outputs, and wherein the other of the two sets of outputs of the counter circuit means comprises n2 outputs; and wherein (n1).(n2) > N.

14. A circuit as defined in claim 2 wherein one of the two sets of outputs of the counter circuit means comprises n1 outputs, and wherein the other of the two sets of outputs of the counter circuit means comprises n2 outputs; and wherein (n1).(n2) > N.

15. A circuit as defined in claim 3 wherein one of the two sets of outputs of the counter circuit means comprises n1 outputs, and wherein the other of the two sets of outputs of the counter circuit means comprises n2 outputs; and wherein (n1).(n2) > N.