US3825895A - Operand comparator - Google Patents

Operand comparator Download PDF

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US3825895A
US3825895A US00360331A US36033173A US3825895A US 3825895 A US3825895 A US 3825895A US 00360331 A US00360331 A US 00360331A US 36033173 A US36033173 A US 36033173A US 3825895 A US3825895 A US 3825895A
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operands
signals
bits
dif
bit
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D Larsen
M Clements
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Fujitsu IT Holdings Inc
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Amdahl Corp
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Priority to US00360331A priority Critical patent/US3825895A/en
Priority to GB1479374A priority patent/GB1453769A/en
Priority to CA196,723A priority patent/CA1022682A/en
Priority to JP4743574A priority patent/JPS5629303B2/ja
Priority to DE2421130A priority patent/DE2421130A1/de
Priority to FR7416440A priority patent/FR2230015B1/fr
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/02—Comparing digital values
    • G06F7/026—Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers

Definitions

  • ABSTRACT Disclosed is a digital data processing system and comparator for comparing operands for equality relationg% 8'' 340/91 ships.
  • the operands are compared on a bit-by-bit basis d 5 177 from the highest-order bit toward the lowest-order bit. 1 0 care
  • the comparison is carried out simultaneously and in parallel for all bits.
  • the equality relationships deter- [56] 1 References cued mined by the comparison are greater than, less than,
  • the present invention is a method and apparatus for use in a data processing system for comparison of operands to determine equality relationship.
  • Operands are compared on a'bit-by-bit basis from high-order bit to low-order bit.
  • the bit-by-bit comparison is performed to detect the first equality relationship between corresponding bits. That first equality relationship is either identity (corresponding bits equal) or non-identity (corresponding bits unequal).
  • the comparison is carried out for positive and negative operands in fixed point or normalized floating point arithmetic.
  • the comparisons determined are greater than, less than, equal to and overflow in the case of fixed point additions and subtractions.
  • the first equality relationship is non-identity.
  • the first equality relationship is nonidentity.
  • the first equality relationship is identity.
  • two 32 bit operands are compared, on a bit-by-bit basis, simultaneously and in parallel for finding the first equality relationship.
  • an improved operand comparator is provided for performing highspeed comparisons which are suitable for the early setting of condition codes utilized in controlling instruction processing.
  • FIG. 1 depicts a block diagram of the data processing system with an expanded view of the execution unit which includes the operand comparator of the present invention.
  • FIG. 2 depicts a block diagram of the operand comparator of the present invention organized by logic block levels I, II, III, IV, V, VI, VII and VIII.
  • FIG. 3 depicts schematic representations of circuits within blocks I, II, and III of the FIG. 2 circuitry.
  • FIG. 4 depicts 'a schematic representation of circuits within block III of the FIG. 2 circuitry.
  • FIG. 5 depicts schematic representations of the circuits within block IV of the FIG. 2 circuitry.
  • FIG. 6 depicts schematic representations of circuits within block IV of the FIG. 2 circuitry.
  • FIG. 7 depicts schematic representations of circuitswithin block IV of the FIG. 2 circuitry.
  • FIG. 8 depicts schematic representations of circuits within block V of the FIG. 2 circuitry.
  • FIG. 9 depicts schematic representations of circuits within block V of the FIG. 2 circuitry.
  • FIG. 10 depicts schematic representations of output I circuits within blocks VI, VII, and VIII of the FIG. 2
  • FIG. 11 depicts schematic representations of circuits in block VI of the FIG. 2 circuitry.
  • the data processing system of the present invention is shown to include a main store 2, a storage control unit 4, an instruction unit 8, an execution unit 10, a channel unit 6 with associate I/O and a console 12.
  • the system of FIG. 1 operates under control of instructions where an organized group of instructions form a program. Instructions and the data upon which the instructions operate are introduced from the I/O equipment via the channel unit 6 through the storage control unit 4 into the main store 2. From the main store 2, instructions are fetched by the instruction unit 8 through the storage control 4 and are processed so as to control the execution within the execution unit 10.
  • IBM System/360 Principles of Operation IBM Systems Reference Library, Form A22-6821.
  • IBM System/360 Architecture IBM System Reference Library C20-l667'.
  • IBM System/370 Principles of Operation IBM Systems Reference Library GA22- 7000.
  • each byte also typically includes a ninth bit for parity used in error detection.
  • the ninthbit in each byte is not generally made throughout this specification, it is assumed that there is a paritybit associated with each byte and that the normal parity checking circuitry is included throughout the system in a wellknown manner.
  • Two bytes are organized into a larger field defined as a half-word, and four bytes or two-half words are organized into a still larger field called a word.
  • Two words form a double word.
  • a word is four consecutive bytes. While these definitions are employed in the specification, it will be understood that words or bytes can equal any number of bits.
  • the instruction formats include RR, RX, RS, SI, and SS.
  • the RX instruction includes an 8-bit OP code, a 4-bit R1 code, a 4-bit X2 code, a 4-bit B2 code and a 12-bit D2 code.
  • the OP code specifies one out of a possible 256 instructions.
  • the R1, X2 and B2 fields each identify one of 16 general registers.
  • the D2 field contains a displacement number betweenand 2".
  • the ADD instruction adds the contents of the register identified by the R1 field to the contents of the main storage location addressed by the sum of the number in the D2 field added to the contents of the register identified by the X2 field again added to the contents of the register identified by the B2 field. The result is placed in the register identified by the R1 field.
  • the RX instructions require two accesses to storage for execution, one to fetch the instruction and one to fetch one of the two operands. RR instructions require one storage access while SS instructions require three or more.
  • the E-unit includes a plurality of functional units indicated generally as 18, 19 30 and 32 as well as a functional unit indicated as LUCK unit 20.
  • Data enters the E-unit 10 through the LUCK unit 20 via the input buses 285 and 286.
  • the OP decoder 142 is connected to receive the curcounters 143 are operative to set appropriate control triggers 145 for controlling, via lines 146, the comparison to be carried out by the operand comparator 274 in the LUCK unit 20.
  • an output signal from comparator 274 is supplied via lines 147 to the l- 7 unit 8 where that signal causes the instruction processing controls to make the correct condition code dependent decision.
  • the LUCK unit 20 is operative to carry out logical operations, comparisons, counts and checking functions on operands 0P2 and 0P1 input on 32-bit buses 285 and 286, respectively.
  • Unit 20 generally includes five or more levels of logic and a plurality of data paths with outputs representing the indicated functions.
  • first level (I) of logic includes conventional phasesplitters 266 and 267 which form bipolar output signals to logic blocks 270 and 271 from the unipolar input signals on buses 285 and 286.
  • Logic block 270 is operative to perform EXCLU- SIVE-OR functions on the input operands providing an output on bus 283 and an input to comparator 274.
  • Logic block 271. is operative to perform EXCLUSIVE- NOR functions on the input operands providing on its output an input to the operand comparator 274.
  • Operand Comparator The operand comparator 274 in FIG. 1 performs comparisons on 0P1 input on bus 286 and 0P2 input on bus 285. In FIG. 2, the operand comparator of the present invention is shown including the phase splitters 266 and 267 and the logic blocks 270 and 271 of FIG. 1.
  • phase splitters 285 and 286 and EXCLUSIVE OR/NOR circuits 270 and 271 are considered part of the operand comparator of the present invention but they may also be considered as separate units providing necessary inputs to the comparator 274 and other circuitry of FIG. 1.
  • the operand comparator receives additional inputs on bus 146 from the control triggers and the timing and control circuitry 924.
  • the bus 146 determines criteria derived from a decode of the operation code of the instruction currently being processed by the LUCK unit 20 and establishes criteria for specifying the particular comparison to be performed by the operand comparator.
  • the operand comparator determines whether or not the input operands on buses 285 and 286 are greater than, less than, or equal to each other and determines whether or not an overflow condition will exist if an addition or substration is specified.
  • the results of the comparison are output on lines 147 from comparator 274.
  • condition code valid (CCV)
  • condition code condition code
  • I condition code
  • condition code condition code
  • condition code 2 (CC 2) condition is implied.
  • the condition code equal to 0 implies that 0P1 equals 0P2.
  • the condition code equal to 1 implies that 0P1 is less than 0P2 in the COMPARE instruction and implies that the result is l ess than O in the ADD and SUBTRACT instructions.
  • condition code equal to 2 implies that P2 is less than OPI in the COMPARE instruction and that the sum is greater than 0 in the ADD and SUBTRACT instructions.
  • condition code equal to 3 implies that an addition or subtraction is called for and that an overflow will result from the addition or subtraction. An overflow is defined as occurring when the carry into the sign bit is not the same as the carry out of the sign bit.
  • the valve of the condition code is connected via lines 147 to the instruction unit 8 where it is utilized in the control of the processing of instructions. While these condition code settings are typical, condition code settings are in general utilized to indicate many different conditions within a data processing system as identified for example, in the above-referenced IBM System/370 Principles of Operation".
  • condition code setting may be obtained by reference to the above-identified application entitled CONDITION CODE. DETERMINATION AND DATA PROCESSING SYSTEM which application is hereby incorporated by reference in the present specification for the purpose of teaching the use of condition codes set by an operand comparator in control- -25 ,block of FIG. 2 which performs the comparison indiling the processing of branch instructions.
  • the FIRST bit position in which an inequality exists is that position determined by commencing with the highest-order bit and proceeding toward the lowestorder bit making a bit-by-bit comparison for equality.
  • the column labelled 0P1 signifies whether or not the operand OP]. is positive (Pos) or negative (Neg) and whether or not the first DIFF" bit for OP]. is a l or a 0 as indicated by the postscrips l or 0 for cases 3 through 6.
  • the column COMP signifies the relationship between (CPI) and (0P2) when the conditions in each of the previous three columns is existent.
  • the comparison relationship of CPI and 0P2 is a magnitude comparison.
  • the column CIRCUIT identifies the particular circuit icated. I,
  • the operands are compared for equality on a bit-by-bitbasis with the order running from the highest order bitl toward the lowest order bit. While the order of comparision is logically from high to low the actual compar- 1; ison is preferably carried out in parallel and simultaneously on a time basis. In the case of TABLE II, the comparison is carried out in order to detect the first identity (both ls or both 's) as indicated by the column FIRST SAME BIT POSITION.
  • cases 1 and 2 represent the conditions where none of the bits in corresponding positions are the same. Under these conditions, the absolute value of the positive operand is less than the absolute value of the negative operand.
  • the operand comparison circuitry 274 functions to compare the magnitude of CPI and 0P2 for both normalized floating point and fixed point arithmetic and for positive and negative operands employing the same generalrules of comparison. Note that the search for equality (identity) used in connection with the TABLE II operations is the inverse of the search for equality (non-identity) used in connection with the TABLE I operations.
  • the comparison of operands CPI and 0P2 is carried out with a bit-by-bit comparison from higher-order bits to lower-order bits ignoring the higher-order sign bit.
  • the equality relationship sought is non-identity, that is, the first occurence of a difference between the corresponding bits in CPI and 0P2.
  • Comparator Apparatus a schematic representation of an operand comparator in accordance with the present invention is shown.
  • the comparator in FIG. 2 includes eigher levels of logic, I through VIII.
  • the phase splitters 266 and 267 correspond to the like-numbered phase splitters in FIG. 1.
  • the phase splitters receive the two 32 bit input buses 285 and 286, respectively.
  • Operand l (0P1) is input orlTaus 286 and comprises the 32 bits +a(0), rl-a(1), ,+a(3l) designated as +a(0 3 I in block I-l.
  • the block [-1 includes 32 phase splitters, one for each of 32 inputs, which produce the 32 pairs of bipolar outputs 121(0), a(1), ia(3l) which are deisgnated ia(0 31). I
  • the block 1-2 receives the 32 in puts +b(0), +b( 1), +b(3l) which are designated +b(0 31) and produces the 32 pairs of bipolar outputs i-b(0), i-b(1), i-b(3l) which are designated i-b(0 31).
  • FIG. 3 the blocks 1-1 and 1-2 are shown in further detail in connection with a typical single bit position
  • the +a(0) input forms the a(0) and the +a(0) outputs.
  • the 0 bit is typical of the 32 bits as indicated by the X32 in the lower right hand corner of blocks I-1 and I-2.-The +b(0) input is similarly phase split to form the bipolar outputs b(0) and +b(0) or simply fl(0).
  • the outputs from each of the blocks I-1 and 1+2 connect as inputs to the blocks II-l through 11-4 in the second level (II) of logic.
  • logic block II-l forms the EXCLUSIVE- OR's of corresponding bits of CPI and 0P2.
  • the I-1 circuit shown for bit 0 is typical of the 32 EXCLUSIVE-OR circuits.
  • the inputs ia(0), +b(0), -a(0), and b(0) are combined forming the EXCLUSIVE-OR output DIF(0).
  • the -DIF(0) output is a I if the input bits +a(0) and +b(0) of operands OPI and Op2 are the same and is a 0 if they are different.
  • the block II-2 forms the EXCLU- SIVE-NOR of the input operands on a bit-by-bit basis to form the 32 outputs SAM(0 31).
  • the block II-2 shows a typical EXCLUSIVE-NOR circuit for bit 0.
  • the inputs u(0), +b(0), +a(0), and b(0) produce the output +DIF(0).
  • block II-3 forms OR/NOR and AND/NAND combinations of the 0 bits of CPI and 0P2. Since and 0 bits are the sign bits, the outputs from block II-3 circuitry define the positive and negativesign relationships between CPI and 0P2.
  • gate 920 As a typical gate, the input bits +a(0) and +b(0) form the outputs +OPS POS and OPS F08.
  • the gate 920 performs the logic functions of a NOR- /OR gate for positive input signals.
  • gate 920 can be characterized as performing the logical functions of a NAND/AND gate for negative input signals. Accordingly, gate 920 in forming the output signal l-OPS POS performs the OR/NOR chi-11(0) and +b().
  • gate 920 can perform the AND/NAND of -a(0) and b(0).
  • the gate 920 is typical of the gates shown in connection with the present application. Each gate like gate 920 can be interpreted as a NOR/OR gate for positive inputs or as a NAND/AND gate for negative inputs. The logical functions are as indicated independent of the particular. nomenclature preferred.
  • the block II-4 performs 32 logical ORs on each of the corresponding bits 0 through 32 for 0P1 and OP2 forming the 32 output signals Z(O 31
  • the block H4 is a typical one of the 32 bits, particularly bit 0.
  • the inputs +a(0) and +b(0) produce the OR output Z(O).
  • the output Z(O) is a 1 if either of the inputs is not 0.
  • the blocks III-1, III-2, and III-3 form logical ANDs of groups of the outputs from the level II circuits. Specifically, the block III-1 logically combines groups of the signals -DIF(0 31) to form the group difference signals DIF(G) as shown in detail in FIGS. 3 and 4.
  • FIG. 3 and block III-1A and referring to FIG. 4 and block III-1B a typical circuit is now described. Referring to the circuit having the inputs DIF( I4) and DIF( that circuit produces the logical NAND of those signals forming the output DIF(- 14-15). Each of the other circuits in block III-1A is employed once (X1) to form the indicated NAND outputs. In FIG. 4 and block III-1B, some of the circuits are employed a multiple number of times. For example, the circuitry having the inputs DIF(14) and DIF( 15) in circuit block III-1B produces the NAND output DIF(14-15).
  • the block III-2 performs the NAND of groups of the signals SAM(O 31 derived from block 11-2.
  • the outputs from block III-2 are the group AND signals SAM(G) which are shown in FIG. 4.
  • the block III-2 the circuits are again duplicated as shown.
  • block III-3 forms the groups NANDs of combinations of the signals Z(O 31) derived from block 11-4.
  • the details of the III-3 circuitry are shown in FIG. 4.
  • the level IV logic includes the blocks IV-1, IV-2, IV-3, W4 and IV-S.
  • the IV -1 block ANDs combinations of the DIF(O 31 -a(1 31 SAM(G) and SAM(X) signals to form the four outputs +FIRST DIF(A D).
  • An output from block IV-l indicates that the first bit position that there is a difference between corresponding bits in CPI and 0P2, 0P1 has a 1 in that position (necessarily 0P2 has a 0).
  • block IV-l includes four circuit groups which produce the outputs +FIRST DIF(A), +FIRST DIF(B), +FIRST DIF(C) and +FIRST DIF (D).
  • a 1 signifies that the first difference bit position is a 1 in operand 1.
  • seven AND gates have their outputs logically ORed. The gate having inputs DIF(I) and a(1) logically ANDs those inputs to produce the output +DIF(I).
  • +DIF(1) is a 1
  • bit 1 of operand 1 is a 1 when there is a difference between bit 1 of CPI and 0P2.
  • the gate having the inputs SAM(I), DIF(2), and a(2) produces an output under the conditions that all higher-order bits from bit 2 (excluding the sign bit) are thesame, there is a difference in corresponding bits 2 of 0P1 and 0P2, and bit 2 in operand 1 is a 1.
  • the gate with the inputs SAM(l-3), DIF(4), and -a(4) produces an output under the conditions that all high-order bits from bit 4 are the same, bit 4 in OPl and 0P2 are different, and bit 4 in operand 1 is a 1.
  • the gates of block IV-l having the inputs a(17), and -a(25) are sensed to determine if there is a difference in those respective bits and if all highorder bits rspectively, excluding the sign bit, are the same. If any one of the'seven indicated gates produces an output, the DOT OR produces an output energizing the signal +FIRST DIF(A).
  • the second column of gates functions for the bit positions 20, 18, 14, 12, 10, 7, 5, and 3 and produces an output signal at +FIRST DIF(B) if for any one of those bits the OH bit is a 1, all the high-order bits for both operands are the same and the corresponding bit position in 0P2 is a 0.
  • the four signals +FIRST DIF (A D) together search all of the bits 1 through 31, so that a logical OR of those four signals indicates that, when energized the first place there is a difference it is a l in OPl.
  • the circuitry of block IV-l in FIG. 5 performs the first difference search required in connection with TABLE I and TABLE IV above.
  • the block IV-2 receives the group AND signals -DIF(G) and selected ones of the individual DIF(O 31) signals, designated as DIF(X), to produce the output signals :L-DIF(031) and :DIF( 1-31).
  • the signals fiIF(0-31) and @IF(- l-3l) indicate that there is a difference in every bit position 0 through 31 and 1 through 31, respectively.
  • the details of the IV-2 block are shown in FIG. 7. In FIG.
  • the block IV-3 indicates when energized that the first bits which are identical in corresponding bit positions of OPl and 0P2 are 1's.
  • the block IV-3 includes the inputs SAM(O 31), #:(1 31), DIF(G), and DIF(X).
  • the details of the lV-3 block are shown in FIG. 6 and are analogous to the IV-l block previously explained.
  • each bit position from 1 through 31 is examined for identity under the condition that all high-order bits, excluding the sign bit are different.
  • the output from each bit position is ORed forming the four signals +FIRST SAM(A D) which, when ORed signify if energized that the first same bit is a l.
  • the block lV-3 also produces the outputs FIRST 1 SAM for each of the bit positions 1 through 31. For example, the FIRST 1 SAM(25) output indicates that bit position 25 is the first same position.
  • circuitry of block IV'-3 in FIG. 6 performs the first same search required in connection with TABLE II and TABLE III above.
  • the block IV-4 uses a combination of SAM signals for all bits through 31 or 1 through 31 for establishing identity relationships, with and without signs, for OPI and 0P2.
  • the 1st circuit of block IV-4 ANDs and NANDs the inputs SAM( 1-24), .-SAM(2529), SAM(30), and SAM(31) to indicate the identity of CPI and 0P2 ignoring the high-order 0 bit.
  • the 2nd circuit of block IV-4 performs the AND/NAND comparison additionally including the 0 bit.
  • block IV-S receives inputs Z(B) from the group NAND block III-3 and selected ones of the signals Z(O'. 31) from the OR gates of block H4.
  • the function of the-block IV-5 is to produce output signals-ZR which specify that all low-order bits, starting with different ones of corresponding bits in each operand, are Os.
  • FIG. 7 the details of block IV-S are shown.
  • the gate having inputs Z(3), Z(4-7), and Z(8-31) responsively NANDs those inputs andproduces output ZR3.
  • the -Z(3) input indicates that in OH and 0P2 both bits 3 are 0.
  • the Z(4-7 input indicates that all bits 4 through 7 in both operands are 0.
  • the Z(8-31) input indicates that all bits 8 through 31 in both operands are 0.
  • the ZR3 output indicates therefor that all of the bits 3 through 31 inclusive in both operands are Os.
  • all of the other gates in block IV-5 of FIG. 7 produce signals which indicate that all low-order bits including the postscripted number up to bit 31, inclusive, are identically equal to 0 in both operands.
  • the 0 condition of lower-order bits produced by the IV-S circuitry is used in connection with cases 7 and 8 of TABLE II.
  • the block V-1 receives the inputs +FIRST DIF(A D) and OR/NORs them to produce the outputs iFIRST DIF PLUS.
  • the function of block V-l is to OR the input signals to form the output signals which indicate that the first difference in corresponding bits
  • the block V-3 NORs the inputs +FIRST SAM(A D), +DIF(0-3l), DIF(0), +b(0), and +a(0) to form the outputs UNl and UN2.
  • the details of block V-3 are shown in FIG. 9 where the 1st circuit produces the UNl output and the 2nd circuit produces the UN2 output.
  • the upper gate is a NOR which indicates that, if any same exists,
  • the bottom gate is a NAND which indicates that not all bits 0 through 31 are different, +DIF(0-3l), and that bit 0 is different, DIF(0), and that 0P1 is positive, +a(0).
  • the UNl output is an-OR of the negative outputs from the two gates and indicates that 0P1 is greater than or equal to 0P2 in absolute value.
  • the circuit V-3-1st of FIG. 9 performs case 5 of TABLE II above.
  • the 2nd circuit of block V-3 in FIG. 9 indicates that 0P2 is greater than or equal to OPI in absolute value as indicated in connection with case 6 of TABLE II above.
  • the function of block V-4 is to which indicate, when the 0 bitsare different (operands of opposite sign), and a first same is a I, that all low-order bits from that first same bit position are Os.
  • the block V-5 receives the inputs +FIRST SAM(A D), DIF(0), +b(0), and +a(0) to produce the outputs ARl and AR2.
  • the details of the block V-5 as shown in FIG. 9 where the ARI signal is produced by an OR of the negative outputs of of CPI and 0P2 which exists from high-order to loworder is a l in CPI and a 0 in 0P2.
  • block V-2 receives the four inputs +FIRST SAM(A D) and OR/NORs them to produce the outputs iFIRST SAM PLUS.
  • the OR]- NOR operation is shown in detail in block V-2 of FIG. 9.
  • the outputs iFIRST SAM PLUS indicate that the first place from high'order to low-order where CPI and 0P2 have corresponding bits which are identical, the identity is a l.
  • the first gate is a NOR which indicates that the first same bit is a 1 bit.
  • the second gate indicates that bit 0 is different and that bit 0 of 0P2 is not a l.
  • the -AR2 signal is produced under the same conditions except that bit 0 of operand is not a 1.
  • the level VI, VII and VIII circuitry receives inputs from the previous levels I through V to develop further equality relationships'which are typically employed to set the condition code signals on the output lines 147.
  • the details of block VI, VII and VIII of FIG. 2 are shown in FIGS. 10 and 11.
  • 16 circuits are shown indicated as running from the 0th to 15th circuit.
  • the circuits VI- 4th represent the outputs for cases 3 and 6 of TABLE I above.
  • the first AND gate is energized whenever both operands are positive (OPS POS) and the first difference is a 1 in OPl (FIRST DIF F08).
  • the second AND provides an output signal whenever both operands are negative (OPS NEG), whenever bits 1 through 31 are not all the same (SAM( l-31)), ahd whenever the first difference is not a 1 in P1 (+FIRST DIF POS).
  • the top gate is operative during case 3 of TABLE I while the bottom gate is operative during case 6 of .TABLE I.
  • circuitry VI-3rd is operative during cases 4 and 5 of TABLE I.
  • the cases 1 through 4 in TABLE II are provided for by the circuits VI-9th, Vlth, VI-l lth, VI-l2th, respectively.
  • the cases 5 and 6 in TABLE II are provided for by the circuits V-3-1 and V-3-2, respectively, as previously described.
  • circuits VI-lst, VI-2nd, VI-Sth, VI-6th, VI- 7th, VI-8th, VI-13th, VI-l4th and VI-lSth in FIG. 11 represent other interesting equality relationships which may be derived in accordance with the present invention.
  • the equality relationships of FIG. 11 are exemplary and are not intended to be exhaustive of all possibilities.
  • Circuits VI-l4th and VI-15th for example, may be used to resolve the ambiguity of cases 5 and 6 of TABLE II, that is, whether the equality relationship exists or whether the greater than or less than relationship exists.
  • the input A CYCI is derived from the control triggers 145 via line 146 in FIG. 1 specifying, as a decode of the operation code that an add instruction is being specified.
  • the second input signifies that both CPI and 0P2 are negative and the third input signifies that there is not a difference in every bit position 1 through 31.
  • the output from the gate OFl is latched in the latch L1.
  • the second gate OF2 provides an output whenever the first same position is a 1 bit. That signal is stored in L2 and is ANDed in gate 957.
  • the AND gate treats inputs as negative so that the input from L2 is a signal which indicates that the first same in corresponding bits of CPI and 0P2 is not a l and hence must be a 0.
  • the combination of the OF 2 and OF 1 conditions satisfies the requirements of case 5 in TABLE III.
  • the combination of gates OF2 and OF3 satisfies the requirements of case 3 in TABLE III. 1
  • the gate OF4 satisfies the conditions of case 4 in TABLE III.
  • gate OF6 produces an output that indicates that the first difference is a 1 in 0P1 and the reciprocal that the the absence of the case 7 and case 8 conditions of TABLE IIare utilized to indicate that the inequality of cases 5 and 6 must be the controlling result.
  • the output circuitry 922 is part of the blocks VI, VII, and VIII of FIG. 2.
  • Circuitry 922 receives inputs from block VI of FIG. 11 and from the other blocks in FIG. 2 to provide the outputs on the four lines 147.
  • the magnitude control signals from the circuitry of FIG. 11 are input to the AND gates Ml through M6 in the manner indicated.
  • the output from the circuitry lV-4-2 and from the circuitry Vl-Oth from FIGS. 7 and 11, respectively, are input to the AND gates M1 and M2, respectively.
  • Those inputs are ANDed with the outputs from control circuits 931 and 932, respectively, to provide inputs to the OR gate 950.
  • the AND gates M3 through M6 combine control signals from controllers 932 through 936 with the outputs of the circuits V-3-2nd, VI-lOth, VI-l2th, and VI-3rd, respectively.
  • condition code valid (CCV) output also appears as one of the lines 147 and is produced by the circuitry 949 which is not pertinent to the presentinvention.
  • the latch circuits Ll through L8 function to store overflow conditions developed in the gates OFl through OF8.
  • the overflow conditions in the gates OFl through OF8 correspond with those previously indicated in connection with cases 3,
  • the various control signals generated by the controls 931 through 936 (which typically include latches like latches 941 to 948) and the latches 941 through 948 are derived in conjunction with the timing and control circuitry 924 of FIG. 1 and the output from the control triggers 146.
  • the clocking of the system of the present invention is carried out in accordance with the above-identified application entitled CLOCK APPARATUS AND DATA PROCESSING SYSTEM.
  • the input signals on lines 285 and 286 are derived, as indicated in that abovereferenced application, as the output from latch circuits (not shown) at one clock timing period and the information passes through the operand comparator of FIG.
  • latch circuits are utilized to store data at an intermediate point of the comparison where necessary. The comparison is then completed in a second or subsequent clock period.
  • the operand comparator of the present invention is employed where it is desired to set the condition code at the end of the E1 cycle of the instruction processing unit. Accordingly, the timing and control signals in FIG. 10 and the input to the operand comparator of FIG. 2 in the system of V 31) are energized.
  • FIG. 1 are operative generally during the two cycles prior to the E1 cycle, that is, during OBI for operand buffer access initiation and DB2 for operand buffer access completion.
  • the operation code from the condition code setting instruction is decoded for setting the control triggers 145.
  • the A CYCl signal indicating an addition and the S CYCI signal indicating a subtraction, and the other timing and control signals are input gates of FIG. 10 and are operative to enable the outputs on lines 147 at the completion of the E1 cycle'.
  • Comparator Operation An example of a comparison of two floating point operands in accordance with TABLE 1, case 4, is given as follows where OPl is /2 X 16' and where P2 is X 16-9:
  • L-FIRST pm The comparison of CPI and 0P2 commences with OPl input on bus 286 and 0P2 input on bus 285 of FIG. 2 where they are phase split in blocks [-1 and I-2 to provide inputs to the level II blocks.
  • the -DIF(9) circuit is energized indicating a difference in bit 9 of CPI and 0P2. None of the other circuits in block "-1 are energized.
  • the SAM(O 8) circuits and the SAM( 31) circuits are energized while the SAM(9) circuit is not energized.
  • the signal +OPS P08 is energized since both CPI and 0P2 are positive as indicated by (TS in the high-order (left most) bits.
  • the signals Z(O 6) and the signals Z(lO 31) are energized indicating all 0s in all but bits -7, 8 and 9 of CPI and 0P2.
  • none of the group difference signals DIF(G) are energized.
  • the group signals SAM( 14-15), SAM(22-23), SAM(1-3), SAM( 17-19), SAM(25-27), SAM( 1-5), -.SAM(- 17-21), SAM(25-29), SAM( l-8),"- SAM(0-7), SAM( 16-23), and SAM(24-3l) are energized.
  • the group signal Z(8-31) and Z(4-7) which includes one or more of the bits 7, 8 and 9 are the only signals not energized.
  • block IV-5 the signals ZR(10 In block V-l, the circuit is not energized because none of the circuits in block IV-l were energized.
  • block V-2 none of the circuits are energized because none were energized in block IV-3.
  • block V-4 none of the circuits are energized.
  • the circuit VI-3rd is energized to produce a logical output +OP1 OPZLS because the input OPS POS from block "-3 and the input +FIRST DIF PLUS from block V-l are simultaneously present.
  • the output signal +OP1 OPZLS is input to the gate M6'in FIG. 10.
  • the output from gate M6 at the appropriate time determined by controller 936 satisfies the gate 951 to energize one of the output lines 147 which indicates that the C@l condition exists.
  • the controller 936 for the typical floating point COMPARE instruction is energized during the El seg- 1 1...1100 o 0...oo1o
  • L-FIRST SAME OPl 0P2 An example of TABLE lII, case 3, fora fixed point addition instruction isgiven for 0P1 having the value.
  • an operand comparator for comparing first and second operands comprismg

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US00360331A US3825895A (en) 1973-05-14 1973-05-14 Operand comparator
GB1479374A GB1453769A (en) 1973-05-14 1974-04-03 Operand comparator
CA196,723A CA1022682A (en) 1973-05-14 1974-04-03 Operand comparator
JP4743574A JPS5629303B2 (de) 1973-05-14 1974-04-26
DE2421130A DE2421130A1 (de) 1973-05-14 1974-05-02 Operandenvergleicher
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US4007439A (en) * 1975-08-18 1977-02-08 Burroughs Corporation Select high/low register method and apparatus
WO1985003148A1 (en) * 1984-01-03 1985-07-18 Motorola, Inc. Floating point condition code generation
US4683546A (en) * 1984-01-03 1987-07-28 Motorola, Inc. Floating point condition code generation
US4918636A (en) * 1987-12-24 1990-04-17 Nec Corporation Circuit for comparing a plurality of binary inputs
US4967351A (en) * 1986-10-17 1990-10-30 Amdahl Corporation Central processor architecture implementing deterministic early condition code analysis using digit based, subterm computation and selective subterm combination
US5495434A (en) * 1988-03-23 1996-02-27 Matsushita Electric Industrial Co., Ltd. Floating point processor with high speed rounding circuit
EP0827068A2 (de) * 1996-09-02 1998-03-04 Siemens Plc Datenverarbeitungsanlage für Gleitkommazahlen
US6298365B1 (en) * 1999-02-24 2001-10-02 International Business Machines Corporation Method and system for bounds comparator
US6516332B1 (en) 1996-09-02 2003-02-04 Siemens Plc Floating point number data processing means
US20090182992A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Load Relative and Store Relative Facility and Instructions Therefore
US20090182984A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Execute Relative Long Facility and Instructions Therefore
US20090182988A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Compare Relative Long Facility and Instructions Therefore
US20090182942A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Extract Cache Attribute Facility and Instruction Therefore
US20090182979A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Computer Configuration Virtual Topology Discovery and Instruction Therefore
US20090182985A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Move Facility and Instructions Therefore
US7739434B2 (en) 2008-01-11 2010-06-15 International Business Machines Corporation Performing a configuration virtual topology change and instruction therefore
US7895419B2 (en) 2008-01-11 2011-02-22 International Business Machines Corporation Rotate then operate on selected bits facility and instructions therefore
US9280480B2 (en) 2008-01-11 2016-03-08 International Business Machines Corporation Extract target cache attribute facility and instruction therefor

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JPS6111003U (ja) * 1984-06-27 1986-01-22 パイオニア株式会社 コ−ドクランパ−

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US3363233A (en) * 1963-04-22 1968-01-09 Licentia Gmbh Digital comparison element
US3316535A (en) * 1965-04-02 1967-04-25 Bell Telephone Labor Inc Comparator circuit
US3390378A (en) * 1965-10-22 1968-06-25 Nasa Usa Comparator for the comparison of two binary numbers
US3492644A (en) * 1966-03-02 1970-01-27 Monroe Int Parallel comparator using transistor logic
US3601804A (en) * 1969-03-14 1971-08-24 British Aircraft Corp Ltd Digital comparator utilizing dual circuits for self-checking
US3660823A (en) * 1970-07-20 1972-05-02 Honeywell Inc Serial bit comparator with selectable bases of comparison

Cited By (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4007439A (en) * 1975-08-18 1977-02-08 Burroughs Corporation Select high/low register method and apparatus
WO1985003148A1 (en) * 1984-01-03 1985-07-18 Motorola, Inc. Floating point condition code generation
US4683546A (en) * 1984-01-03 1987-07-28 Motorola, Inc. Floating point condition code generation
US4967351A (en) * 1986-10-17 1990-10-30 Amdahl Corporation Central processor architecture implementing deterministic early condition code analysis using digit based, subterm computation and selective subterm combination
US4918636A (en) * 1987-12-24 1990-04-17 Nec Corporation Circuit for comparing a plurality of binary inputs
US5495434A (en) * 1988-03-23 1996-02-27 Matsushita Electric Industrial Co., Ltd. Floating point processor with high speed rounding circuit
EP0827068A2 (de) * 1996-09-02 1998-03-04 Siemens Plc Datenverarbeitungsanlage für Gleitkommazahlen
EP0827068A3 (de) * 1996-09-02 1999-05-19 Siemens Plc Datenverarbeitungsanlage für Gleitkommazahlen
US6516332B1 (en) 1996-09-02 2003-02-04 Siemens Plc Floating point number data processing means
US6298365B1 (en) * 1999-02-24 2001-10-02 International Business Machines Corporation Method and system for bounds comparator
US7895419B2 (en) 2008-01-11 2011-02-22 International Business Machines Corporation Rotate then operate on selected bits facility and instructions therefore
US8301815B2 (en) 2008-01-11 2012-10-30 International Business Machines Corporation Executing an instruction for performing a configuration virtual topology change
US20090182988A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Compare Relative Long Facility and Instructions Therefore
US20090182942A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Extract Cache Attribute Facility and Instruction Therefore
US20090182979A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Computer Configuration Virtual Topology Discovery and Instruction Therefore
US20090182985A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Move Facility and Instructions Therefore
US7734900B2 (en) 2008-01-11 2010-06-08 International Business Machines Corporation Computer configuration virtual topology discovery and instruction therefore
US7739434B2 (en) 2008-01-11 2010-06-15 International Business Machines Corporation Performing a configuration virtual topology change and instruction therefore
US20100223448A1 (en) * 2008-01-11 2010-09-02 International Business Machines Corporation Computer Configuration Virtual Topology Discovery and Instruction Therefore
US7870339B2 (en) 2008-01-11 2011-01-11 International Business Machines Corporation Extract cache attribute facility and instruction therefore
US20090182992A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Load Relative and Store Relative Facility and Instructions Therefore
US20110131382A1 (en) * 2008-01-11 2011-06-02 International Business Machines Corporation Extract Cache Attribute Facility and Instruction Therefore
US7984275B2 (en) 2008-01-11 2011-07-19 International Business Machiness Corporation Computer configuration virtual topology discovery and instruction therefore
US8015335B2 (en) 2008-01-11 2011-09-06 International Business Machines Corporation Performing a configuration virtual topology change and instruction therefore
US8131934B2 (en) 2008-01-11 2012-03-06 International Business Machines Corporation Extract cache attribute facility and instruction therefore
US20090182984A1 (en) * 2008-01-11 2009-07-16 International Business Machines Corporation Execute Relative Long Facility and Instructions Therefore
US8516195B2 (en) 2008-01-11 2013-08-20 International Business Machines Corporation Extract cache attribute facility and instruction therefore
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US9135004B2 (en) 2008-01-11 2015-09-15 International Business Machines Corporation Rotate then operate on selected bits facility and instructions therefor
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FR2230015B1 (de) 1978-03-24
JPS5054258A (de) 1975-05-13
JPS5629303B2 (de) 1981-07-07
DE2421130C2 (de) 1987-07-16
CA1022682A (en) 1977-12-13
FR2230015A1 (de) 1974-12-13
DE2421130A1 (de) 1974-12-05
GB1453769A (en) 1976-10-27

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