US3820107A - Sign display device - Google Patents

Sign display device Download PDF

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Publication number
US3820107A
US3820107A US00288738A US28873872A US3820107A US 3820107 A US3820107 A US 3820107A US 00288738 A US00288738 A US 00288738A US 28873872 A US28873872 A US 28873872A US 3820107 A US3820107 A US 3820107A
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Prior art keywords
display
signal
register
digit
arithmetic operation
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Expired - Lifetime
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US00288738A
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English (en)
Inventor
M Ito
J Ishiata
Y Niizawa
R Hirano
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Canon Inc
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Canon Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1407—General aspects irrespective of display type, e.g. determination of decimal point position, display with fixed or driving decimal point, suppression of non-significant zeros
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/02—Digital computers in general; Data processing equipment in general manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators

Definitions

  • G08b 5/36 g su as inus is required o e p yed, [58] Field of Search 340/324 R, 336; 235/92 EA such sign is displayed in the digit adjacent to the most significant digit of the number or significant digits to [56] References Cited be displayed.
  • a sign display device is incorporated therein in order to display a sign such as a minus sign in a fixed digit position independently of the information being displayed when such a sign is needed.
  • a minus-sign display unit is disposed in the l3th digit in order to display the minus sign when required indepently of the significant digits of the number displayed. Therefore it is very inconvenient to read thenumber displayed with the minus sign.
  • the present invention has been made in order to overcome the above and other defects encountered in the prior art display device by displaying the minus sign in the digit adjacent to the most significant digit of the number displayed.
  • One of the objects of the present invention is to provide a novel sign display device which may display a sign without destroying the content held in a display register.
  • Another object of the present invention is to provide a novel sign display device which may suppress the zero or zeros in the digit or digits except the significant digit and may display a sign in a digit spaced apart by a predetermined digit length from the most significant digit of the number displayed.
  • FIG. 1 is a block diagram of one preferred embodiment of a sign display device in according to the present invention.
  • FIG. 2 is a diagrammatic view of a flip-flop in an entry control unit included in the device shown in FIG. 1;
  • FIG. 3 is a diagrammatic view of a flip-flop .in an arithmetic operation control unit included in the device shown in FIG. 1;
  • FIG. 4 is a view illustrating display segments in a display unit of the device shown in FIG. 1;
  • FIG. 5 shows the waveforms of the control signals and the number to, be displayed used for the explanation of the mode of operation of the preferred embodiment shown in FIG. 1;
  • FIG. 6 is a view used for the explanation of the mode of shift in the display device of the decimal digits as they are entered;
  • FIG. 7 is a block diagram of a zero suppressor circuit used in the preferred embodiment shown in FIG. 1;
  • FIG. 8 shows the gate signal to be used in suppressing zeros or detecting the significant digits
  • FIG. 9 is a view used for the explanation of the change in content in the register when zero suppression or detection of significant digits is effected.
  • a display register 11 is a dynamic circulating register with a circulation loop 13 and an OR gate 12, and holds the binary coded decimal digits to be displayed each consisting of four bits.
  • the content in the display register 11 is circulated from the least significant digit position to the most significant digit position through the circulation loop 13 and the OR gate 12.
  • the decoder 15 has a function of decoding the four binary bit signals into patterns signals, and has seven output terminals in order to select the desired ones out of the seven segments A-G of the seven bar format shown in FIG. 4 in a display device.
  • the decimal point segment P is directly energized by a decimal point counter to be described hereinafter.
  • the output terminals 16 -16 of the decoder 15 are connected to AND gates 17 -17 to which are applied the control signal to be described hereinafter.
  • Each of cold-cathode-discharge type display units 18 -18 may display one digit or sign by the combinations of seven segments l8 a-18 g, 18,,a18,,g and by the decimal point segments P 18 p18 p.
  • the similar segments 18 a, 18 a, and 18,,a; 18 b, 18 b, and 18, 1); and l8 f, 18 and 18,,f are connected together to the AND gates 17 -17 and are designated by 18a, 18b, and 18f respectively hereinafter.
  • the similar segment 18 g, 18,,g, which will be designated by 18g hereinafter, are connected together to the output terminal of an OR gate 20 to which is also applied the output signal of the AND gate 17
  • the decimal point segments 18p are connected to the decimal point counter to be described hereinafter. It is seen that the segment G shown in FIG. 4 may be used to display the minus sign in the digit adjacent to the most significant digit of a significant number to be displayed.
  • To terminals 21,41 of the anode electrodes 19 -19,, of the display units 18 -18 are applied the digit selection pulses.
  • the input numerical information is fed by a keyboard 22 including a decimal point entry key into an encoder 23.
  • the encoder 23 converts the input numerical information into the binary coded signals which are fed to the display register 11 through the OR gate 12 and to an entry control unit 24.
  • the entry control unit 24 comprises a plurality of flip-flops FN (See FIG. 2) which are set when the binary coded signals are entered and other flip-flops. By the combinations of the output signals of the flip-flops, the various controls are effected.
  • the arithmetic operation command is entered by a function keyboard 25 and is converted into the binary coded signals by an encoder 26 to be applied to an arithmetic operation control unit 27.
  • the arithmetic operation control unit 27 comprises a plurality of subtraction flip-flops FS (SEE FIG. 3) and other flip-flops which are set when the function keys such as (X), and are depressed.
  • the various arithmetic operations may be effected in response to the output signals of the flip-flops.
  • the output signals of the entry control unit 24 and the arithmetic operation control unit 27 are applied to an AND gate 28, the output signal of which is applied to an OR gate 29.
  • the carry output of an adder 30 is applied to the OR gate 29 through an AND gate 31, and the output of an accumulator 32 is also applied to the OR gate 29 through an AND gate 33.
  • the arithmetic command control signals which are produced by an arithmetic operation command control signal generator 34 are applied to the AND gates 31 and 33.
  • the output signal of the OR gate 29 is applied to the set terminal of a flipflop 35.
  • the set output signal which is generated when the flip-flop 35 is set in response to the signal given when the minus sign must be displayed, is used to drive the display unit to display the minus sign.
  • the flip-flop 35 is reset in response to the reset signal given by a clear circuit 36 which is activated upon depression of a clear key.
  • the set output signal of the flip-flop 35 is applied to an AND gate 37 whose output signal is ap plied to the OR gate 20 so that the cathode electrode or segment 18g is energized to display the minus sign
  • the decimal point signal entered by the keyboard 22 is stored in a decimal point counter'38 as a digit information, and the output signal of the decimal point counter 38 is applied to the cathode electrode 18p in the display units and to a zero suppressor circuit 39 which serves to display only the significant figure.
  • thezero suppressor circuit 39 detects zero or zeros in the digits higher than the decimal point or the most significant digit, and gives the output signal to the AND gates 17 -17
  • Various kinds of zero suppressor circuits have been already devised and demonstrated, but in the instant embodiment the zero suppressor circuit of the type shown in FIG. 7 is used.
  • the signals representing four bits in the buffer register 14 are applied to an OR gate 42 so that the latter gives the signal when the binary coded signal inthebufferregister represents zero but gives the signal 1" when the numeral stored in the buffer register is other than zero.
  • the decimal point signal is applied to an OR gate 44 to which is applied the output signal of the OR gate 42.
  • the output signal of the OR gate 45 is fed into an onebit memory 46 and the output signal of the memory 46 is fed into a memory 49 capable of holding a group of binary bits through an OR gate 47 and an AND gate 48.
  • Four bits in each digit in the display register 11 are compressed in one bit and stored in the memories 46 and 49.
  • the zero suppression signal may be obtained from the memory or register 49.
  • the least significant bit in the memory 49 is applied to the OR gates 45 and 47, and the shift pulses are applied to the memories 46 and 49 in synchronism with the shift in the display register 11.
  • the gate signals as shown in FIG. 8 are applied to the terminal 50 of the AND gate 48. It is assumed that the display register have five digits bits) and the memories 46 and 49 have one and five bits respectively. At time T T T the digits in the least significant digit position in the display register are read out.
  • the numeral 500 is stored in the display register 11 in the form of 00500. During a time interval equal to (one bit X five periods), that is a time interval between T1 and T5, the information 00500 is converted into 00100.
  • the memory 46 holds 0 whereas the memory 49 holds 0100.
  • the mode of obtaining the zero suppression signals by circulating the information through the memories 46 and 49 is illustrated in FIG. 9.
  • the display register holds 00500 whereas the memories 46 and 49 hold 00100.
  • the AND gate 48 is closed, and the information is shifted to the right so that the content in D1 is transferred into D5.
  • the high-level signal is applied to the terminal 50 of the AND gate 48, and the content in D1 is shifted to D5 and is also transferred into D4 through the OR gate 47 and the AND gate 48.
  • the binary bit in D1 is 0 so that the content in D4 remains unchanged.
  • the output signal of the zero suppressor circuit 39 is at a high level El as shown in FIG. 5-II when the digits to be displayed exist, and falls to a low level E when the zeros are suppressed.
  • FIG. 5-I shows the digits to be displayed which are obtained from the display register 11.
  • the output signal of the zero suppressor circuit 39 is delayed by one bit time by a delay line 40 comprising a flip-flop or the like, and the output signal shown in FIG. 5-111 and the inverted output signal of the zero suppressor circuit 39 are applied to an AND gate 41, which in turn gives the pulses (FIG. 5-IV) at the digit adjacent to the most significant digit to the AND gate 37.
  • the output signals of the buffer register 14 are decoded by the decoder 15, and are also applied to the zero sup- I pressor circuit 39 so that the latter gives the highJevel signal BS to the AND gates 17 -17 for a time equal to one digit time.
  • the decoder 15 gives the segment selection signals so that the segments A, C, D, F and G (See FIG. 7) in the display unit 18 are energized to display 5.
  • the flip-flop FN in the entry control circuit 24 is set so that the set output signal is applied to the AND gate 28. Since the set output signal from the flip-flop FS in the arithmetic operation control circuit 27 is already applied to the AND gate 28, the latter is opened so that the output signal is applied through the OR gate 29 to the flip-flop 35 to reset it.
  • the output signal of the flip-flop 35 is applied to the AND gate 37 to which is also applied the output signal X of ire AND gate 41.
  • This output signal X is BS'BS l or BS'BS 1 because the output signal BS of the zero suppressor circuit 39 and the output sig- S nal BS 1 of the delay line 40 are applied to the AND gate 41 which gives the logical product of the two output signals.
  • the signal X rises to a high level for one digit time as soon as the signal BS of the zero suppressor circuit 39 falls from the high level to low level as shown in FIG. -IV.
  • the AND gate 37 is openedfor one digit time immediately when the output signal BS or the signal indicating the digits to be displayed of the zero suppressor circuit 39 disappears while the flip-flop 35 is set.
  • the output signal of the AND gate 37 is applied to the segment G (See FIG. 4) through the OR gate 20, so that the segment G is energized to display the minus sign
  • the signal X appears immediately after the signal BS falls to a low level so that the minus sign is displayed in the digit adjacent to the digit 5. Hence 5 may be displayed.
  • the zero suppression signal BS When the signal X' is at high level, the zero suppression signal BS is at low level; the digit pulse has been already applied to the digit at which a numeral is to be displayed; and the signal X remains at high level during the time when the digit pulse is applied to the digit adjacent to the digit at which a numeral is to be displayed.
  • the minus sign may be displayed in the digit adjacent to the most significant digit of the decimal number displayed by the logic product of the outputs of the zero suppressor circuit and the one-bit delay line.
  • the flip-flop 35 is set when the logic product of the carry signal of the adder 30 and the subtraction command signal SUB from the arithmetic opera tion control signal generator 34.
  • the AND gate 33 is applied with a signal representing that the minus-sign signal is stored in the sign detection digit in the accumulator 32.
  • the multiplication command, division command or the like is applied to the AND gate 33 from the arithmetic operation control signal generator 34.
  • the negative number is multiplied or divided, the result is always a negative number so that the flip-flop 35 is set in order to display the minus sign in the digit adjacent to the most significant digit to be displayed.
  • the signal may be applied to the reset terminal of the flip-flop 35 so that the latter may be reset and may give no output signal. This will be described in more detail with reference to the clear circuit 36.
  • the flip-flop 35 When the clear key (not shown) is depressed, not only the minus sign but also the number must be cleared.
  • the entry keys are depressed to enter -4 5 l the minus sign is once displayed, but the result of the arithmetic operation is positive. Therefore when the result is positive, the flip-flop 35 must be reset. In like manner the flip-flop 35 may be reset when it is desired to eliminate the minus sign.
  • a sign display device comprising:
  • a register having a plurality of bit positions for holding the information to be displayed
  • an arithmetic operation control unit for controlling an arithmetic operation under control of function keys
  • arithmetic operation means for executing an operation
  • memory means for storing an output signal from said arithmetic operation control means and a signal generated by said arithmetic operation means
  • said memory means comprises a flip-flop.
  • a sign display device wherein said memory means is arranged to store a signal from a sign detection digit of an accumulator.
  • a sign display device wherein there is provided a gate through which the signal generated by said arithmetic operation means and the signal from the sign detection digit of said accumulator are applied to said memory means, said gate being connected for control by an arithmetic command control signal from an arithmetic operation command control signal generator.
  • a sign display device wherein said memory means is connected to a clear circuit operable in accordance with an operation of a clear key.
  • a sign display device according to claim 1, wherein the means for controlling said display means includes:
  • a gate circuit to which is applied the signal indicative of the detected digit position and the output signal from said memory means;
  • said arithmetic operation control unit is connected to apply its output signal to said memory means through a gate circuit controlled by a signal from an entry control unit.
  • a sign display device comprising: a. a register having a plurality of bit positions for holding the infonnation to be displayed; b. display device for visually displaying said information read out from said register;
  • arithmetic operation means for executing an operation
  • memory means for storing an output signal from said arithmetic operation control means and a signal generated by said arithmetic operation means
  • a sign display device comprising:
  • a register having a plurality of bit positions for holding the information to be displayed
  • a first gate circuit to which are applied an output signal from said detecting means and a delayed signal corresponding to said output signal from said detecting means;
  • an arithmetic operation control unit for controlling an arithemtic operation under control of function keys
  • h. arithemtic operation means for executing an operation
  • memory means for storing an output signal from said arithmetic operation control unit and a signal generated by said arithmetic operation means
  • a sign display device comprising:
  • a register having a plurality of bit positions for holding binary coded information to be displayed
  • a decoder for converting said binary coded information held in said register into signals to drive said display means
  • an arithmetic operation control unit for controlling an arithmetic operation under control of function keys
  • arithmetic operation means for executing an operation
  • memory means for storing an output signal from said arithmetic operation control unit and a signal generated by said arithmetic operation means
  • j. means for supplying to said display means a signal in accordance with any of said signals stored in said memory means to display a special sign at a digit position spaced apart by a predetermined number of digit positions from the most significant digit of the significant digits in said display means.
  • a sign display device comprising:
  • a register having a plurality of bit positions for holding binary coded information to be displayed
  • a decoder for converting the binary coded infor mation held in said register into signals for driving said display means
  • a delaying circuit for delaying the output signal from said detecting means for a time corresponding to the shifting of one digit
  • a first gate circuit to which are applied the output signal from said detecting means and a delayed signal of the output signal from said detecting means;
  • j. means for applying a signal generated by'an arithemtic operation means and a signal derived from a sign detection digit of an accumulator to said flipflop through third gates controllable by an arithmetic command control signal generated in an arithmetic operation command control signal generator;

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  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Digital Computer Display Output (AREA)
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US00288738A 1971-09-20 1972-09-13 Sign display device Expired - Lifetime US3820107A (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3962571A (en) * 1974-11-26 1976-06-08 Texas Instruments Incorporated Low power digit blanking circuit
US3965466A (en) * 1973-04-23 1976-06-22 Sharp Kabushiki Kaisha Digital display
US4100600A (en) * 1976-10-27 1978-07-11 Texas Instruments Incorporated Data display system for electronic calculator or microprocessor
US4190892A (en) * 1977-06-07 1980-02-26 Citizen Watch Co., Ltd. Zero suppressing system for electronic device
US4292624A (en) * 1974-10-25 1981-09-29 Serp William K International Morse Code number generator
US4326148A (en) * 1978-07-14 1982-04-20 Matsushita Electronics Corporation Gas discharge display device

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS599933B2 (ja) * 1975-04-09 1984-03-06 シャープ株式会社 ゼロサプレス装置
JPS5228225A (en) * 1975-08-28 1977-03-03 Fujitsu Ltd Indication control system
JPS60114156U (ja) * 1984-01-09 1985-08-02 日本電気株式会社 書状の集積装置

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3965466A (en) * 1973-04-23 1976-06-22 Sharp Kabushiki Kaisha Digital display
US4292624A (en) * 1974-10-25 1981-09-29 Serp William K International Morse Code number generator
US3962571A (en) * 1974-11-26 1976-06-08 Texas Instruments Incorporated Low power digit blanking circuit
US4100600A (en) * 1976-10-27 1978-07-11 Texas Instruments Incorporated Data display system for electronic calculator or microprocessor
US4190892A (en) * 1977-06-07 1980-02-26 Citizen Watch Co., Ltd. Zero suppressing system for electronic device
US4326148A (en) * 1978-07-14 1982-04-20 Matsushita Electronics Corporation Gas discharge display device

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