US3813623A - Serial bcd adder - Google Patents

Serial bcd adder Download PDF

Info

Publication number
US3813623A
US3813623A US00317303A US31730372A US3813623A US 3813623 A US3813623 A US 3813623A US 00317303 A US00317303 A US 00317303A US 31730372 A US31730372 A US 31730372A US 3813623 A US3813623 A US 3813623A
Authority
US
United States
Prior art keywords
shift register
full adder
output
input
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US00317303A
Other languages
English (en)
Inventor
K Nomiya
T Tsuiki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of US3813623A publication Critical patent/US3813623A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/02—Digital computers in general; Data processing equipment in general manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators

Definitions

  • the present invention relates to a digital processing system which employs shift registers connected in ser1es.
  • a principal object of the present invention is to provide a processing system wherein the number of circuit elements is reduced, and more particularly, a digital processing system which is suitable for a small-sized calculator such as a desk-top calculator.
  • Another object of the present invention is to provide a digital processing system which can easily display processed information signals.
  • Still another object of the present invention is to provide a digital processing system which can easily execute arithmetics such as multiplication and division.
  • Yet another object of the present invention is to provide a digital processing system which can shorten the length of the register. means.
  • a further object of the present invention is to provide a digital processing system which is free from overflow of a processed result.
  • a digital processing system characterized by a first display shift register-of a certain capacity prescribed for numerical information for display in a display unit (for example, a capacity for storing numerical information of eight digits), a calculating shift register having the same capacity as said first display shift register, a binary digit full adder connected to the output side of said first display shift register and having a memory circuit (delay circuit) with a capacity of two to four bits, and a second display shift register disposed between said binary digit full adder and said first display shift register and having a capacity which is equal to one obtained by subtracting the capacity of said memory circuit of said binary digit full adder from the capacity of said first display shift register; said first display shift register, said second display shift register and said full adder forming a circulative closed circuit for information signals; the total capacity bit time of said first display shift register, said second display shift register and said delay circuit in said full adder is time-shared by a sector pulse corresponding to the capacity bit time of said calculating shift register; thus
  • FIG. 1 is a block diagram showing an embodiment of a digital processing system according to the present invention
  • FIGS. 2a and 2b are wave-form diagrams of controlling and synchronizing pulses which are used in the digital processing system of the present invention
  • FIGS. 3 and 4- are block diagrams each showing a delay type full adder which is employed in the present invention.
  • FIGS. 5a 5e, 6a 6c and 7a 7d are explanatory diagrams for illustrating changes of information signals of display shift registers in the digital processing system of the present invention.
  • FIG. 8 is a block diagram showing an example of a prior-art digital processing system.
  • R designates the first display shift register which has a fixed capacity.
  • the capacity of the shift register R is eight digits (32 bits) from the least significant digit LSD, to the most significant digit MSD R indicates the second display shift register which is directly coupled to the register R at a stage preceding thereto.
  • the capacity of the register R is set so that the total capacity (32 bits) of the capacity (for example, four bits) of a binary digit full adder AD referred to below and the capacity (forexample, 28 bits) of the register R itself may be equal to the capacity (32 bits) of the first display shift register R R represents a calculating shift register, which has the same capacity (32 bits) as the first display shift register R Shown at AD is the binary digit full adder, to which are supplied the output of the display register R for the posterior stage and the output of the calculating register R or a different control'input Dt
  • the output of the binarycoded decimal full adder AD is supplied through a line F L2 to the input side of the display register R); for the anterior stage.
  • the binary-coded decimal full adder AD is composed of a binary full adder FA a memory circuit DM for carry detection (for BCD correction) and a binary full adder FA
  • the carry detecting memory circuit DM has, for example, N digits (at least two bits). The number of digits of the memory capacity of the display register Rxb for the anterior stage is subtracted to the amount of the length of the N digits.
  • N2 and N be the numbers of digits of the anterior stage display register R posterior-stage display register R and calculating register Ry, respectively, they are thus set so as to hold the relation of N N, N N Accordingly, among the three registers, the length of the anterior-stage display register R is shorter by the N digits than that of the other register R or R while the sum between the length of the carry detecting memory circuit DM and that of the anterior-stage display register R becomes equal to the length .of the other register R or R
  • the above-noted relation may also be defined in the manner the memory capacity of the circuit DM is 4N bits, the memory capacities of the first display shift register R and the calculating shift register R are both 4N bits and the memory capacity of the second display shift register is 4(N N bits, where N, and N are integers of at least one and N N,.
  • An indicator unit IN for indicating the information contents of the display register R (the first and second display registers R and Rxb) is also provided.
  • information subjected to calculating processing are read out from the output side of the first display shift register R to the indicator unit by a line FL and are brought into visible display or recording display by the indicator unit.
  • a decoder circuit and a drive circuit which are connected between the display shift register R and the indicator unit IN, are omitted for the sake of convenience of explanation.
  • the display system of the indicating unit is a dynamic one
  • the foregoing construction is very effective in a processing system in which the information stored in the circulating path including the registers R and R and the memory circuit DM amounts to eight digits being a half of the total capacity, and in which the remaining eight digits are brought into the blank state after completion of the calculation.
  • the transfer of information from the display shift register R to the calculating shift register Ry is accomplished by a line F L.
  • a controlling gate portion necessary for the calculating processing is incorporated into each of the lines which is controlled on-and-off by a synchronizing pulse for control, the controlling gate section is omitted from the drawing.
  • the information signal stored in the calculating register R ,-the display register R and the memory circuit DM of the full adder AD is shifted by clock pulses Cp and Cp as shown in FIG. 2a.
  • the total capacity bit time (64-bit time) of the loop-like closed circuit passing through the display register R and the full adder AD is prescribed at double of the capacity bit time (32-bit time) of the calculating register Ry.
  • the information of the first display register R X and the second display register R are distinguished by timing pulses (pulses for distinguishing higher digits and lower digits) Sp shown in FIG. 2b, and are subjected to the calculating processing.
  • the timing pulse Sp has a pulse width equal to the period of the digit pulse Dt shown in FIG.
  • the information of the first display shift register R is processed for a period of time T in which the timing pulse Sp is of a high level
  • the information of the second display shift register R M is processed for a period of time T in which it is of a low level.
  • the information of R and Ry are applied to the adder Ad in the period of time T of the timing pulse Sp.
  • the upper level of a pulse signal indicates a reference potential or the ground potential (logic l while the lower level represents a negative potential (logic 0").
  • the clock pulses Cp, and Cp are generated by, e.g., astable multivibrators, and tick away the time by themselves in the calculator. They are used for the drive or shift of, e.g., memory elements (delay type flip-flop circuits) connected in cascade within the shift registers R R and Ry and the memory circuit DM for correcting a binarycoded decimal number.
  • Cp Bit signals Bt, Bt are used in case of, e.g., converting binary parallel signals derived from the encoder into binary series signals.
  • the judging signal of the bit signal Bt is utilized in the binary-coded decimal full adder as stated below.
  • Digit signals Dt Dt are used as, e.g., digit changing signals in the dynamic display system. In the embodiment, they are used in order to add 1 to or subtract the same from the second operand in multiplication and division as is stored in the shift register for display.
  • the sector pulses Sp have the state changed to T or T every eight digits, and can be composed from the digit signal Dt or Dt by utilizing a flip-flop circuit and a logical gate circuit. Digit pulses Dp distinguish the digits of a binary-coded decimal number. Word pulses Wp are used for distinguishing words or instructions. The characteristic equations of the respective pulses Dp and W are re resented by D Btf CE and W,, Dt Cp S; which can be composed of the foregoing pulses.
  • the bit signals Bt, BL, and the digit signals Dt Dt can be respectively generated from the clock pulses Cp and the bit signal Bt, by making use of, e.g., counters.
  • the pulse width of the bit signals Bt Bt corresponds to the period of the clock pulses Cp, or CM, and to the time of 1 bit of the series binary signal.
  • the pulse width of the digit signals Dt, Dt and the period of the digit pulses Dp correspond to the period of the bit signals Bt Btq, namely, the time of one digit (four bits) of the series binary-coded decimal number.
  • the period of the word pulses Wp corresponds to double of the period of the digit signals Dt Dt
  • the delay type full adder AD is constructed as shown, by way of example, in FIG. 3.
  • DL represents a delay circuit having a memory capacity of four bits (one digit), DL and DL;, delay circuits for effecting delay of one-bit time, CC a correction judging circuit, G a gate circuit which has its gate opened by a predetermined timing signal Bt,, and CG a generator for generating in response to an output of the correction judging circuit CC an output which serves to add 6 in decimal number (01 10 in binary number) to the binary full adder FA
  • the delay circuits DL DL correction judging cirucit CC, generator CG and gate circuit G constitute the carry detecting memory circuit DM.
  • the output of the binary full adder FA is supplied through the delay circuit DL, to the binary full adder FA in consequence of the addition of the outputs of the posterior-stage register X and the register Y as have been supplied to the binary full adder FA,.
  • the output of the binary full adder F a is transmitted to the anterior-stage register X or R
  • a binary carry signal is supplied through the delay circuit DLg to the input side of the binary full adder FA to add l to a higher binary digit. At this time, it is a matter of course that, even with the binary carry, no overflow occurs beyond four binary digits.
  • the correction judging circuit CC and the gate circuit G do not operate.
  • the binary carry signal is supplied through the delay circuit DL to the input side of the binary full adder PA, for the binary carry in the binary full adder FA
  • the correction judging circuit CC is operated by an instruction of the delay circuit DL,.
  • the correction judging circuit CC supplies an output to the generator CG, and simultaneously supplies a decimal carry signal to the binary full adder FA to conduct decimal carry.
  • the output of the delay circuit DL, and that of the generator CG are added by the binary full adder.
  • the binary carry is conducted in such way that the output of the binary full adder FA is supplied through the gate circuit G, adapted to be opened by the predetermined timing signal E, to the input side of the binary full adder FA with delay of one-bit time by the delay circuit DL In this manner, -5 in the binary-coded decimal notation is transmitted from the binary digit full adder AD, that is, the binary full adder FA Further, in the case where the result of the addition in the binary full adder FA, is 16-19, the output of the binary full adder FA is supplied through the delay circuit DL to the input side of the binary full adder FA thereby to conduct the binary carry and the decimal carry.
  • the instructing output of the delay circuit DL is not supplied to the correction judging circit CC.
  • the instructing output of the binary full adder FA operates the correction judging circuit CC.
  • the output of the correction judging circuit CC operates the generator CG.
  • the output of the generator CG is supplied to the input side of the binary full adder FA
  • the output of the binary full adder FA is supplied through the delay circuit DL to the input side of the binary full.
  • adder FA The binary carry signal is supplied through the gate circuit G and delay circuit DL from the output side of the binary full adder FA Since the decimal carry has been already conducted in the binary full adder FA no decimal-carry is executed in the binary full adder FA In this manner, an output of 6-9 is transmitted as the output of the binary digit full adder AD, that is, the output of the binary full adder FA FIG.
  • FIG. 4 shows another embodiment of the binarycoded decimal full adder in FIG. 1.
  • the delay circuits DL DL the correction judging circuit CC and the generator CG constitute the carry detecting memory circuit.
  • a point of difference from the embodiment in FIG. 3 resides in that, without using the gate circuit G, the output of the binary full adder FA is supplied through the delay circuit DL to the correction judging circuit CC and the input side of the binary full adder FA With such a construction, in the case where the result of addition in the binary full adder FA, is 09 or 16-19, the foregoing applies,
  • the output of the binary full adder FA is supplied through the delay circuit DL to the input side of the binary full adder FA, thereby to conduct binary carry.
  • the output of the binary full adder FA is supplied through the delay circuit DL to the binary full adder FA
  • the instructing output of the delay circuit DL is supplied to the correction judging circuit CC.
  • the output of the binary full adder FA is supplied through the delay circuit DL to the input side of the binary full adder FA as a binary carry signal and to the correction judging circuit CC as a decimal carry signal.
  • the output of the correction judging circuit CC operates the generator CG.
  • the output 0110 of the generator CG is supplied to the input side of the binary full adder FA In this way, 0-5 is transmitted as the output of the binary-coded decimal full adder AD, namely, that of the binary full adder FA,.
  • the carry detecting memory circuit DM has the memory capacity of four bits, it is a matter of course that the invention is not restricted thereto, but that three bits, for example, may
  • a delay circuit for 1-bit delay is incorporated into an output supply line of, for example, from the correction judging circuit CC to the binary full adder FA, in FIG. 4.
  • FIG. 5 illustrates changes with time in information stored in the display register R in a calculating process in the case of executing the multiplication of 5 X 3 15.
  • the contents of all the shift registers are cleared to 0 beforehand.
  • the multiplicand 5 is set by means of a number setting keyjik not shown) of the calculator, it is inputted from an input terminal i (FIG. 1) into and stored in the circulative memory circuit which the shift register R the correcting memory cir cuit DM and the feedback line FL, constitute.
  • a function keylzl is depressed, and the multiplier 3 is set by a number setting keyE].
  • the multiplicand 5 is transferred from the register R through the line FL, to the register Ry, and is circulated and held by the feedback path FL
  • the multiplier 3 is stored, as in the foregoing setting of the multiplicand 5, in the circulative memory circuit constituted of the shift register R the correcting memory circuit DM and the feedback path FL.,.
  • the circulative memory circuit stores therein the first or second operand corresponding to eight digits. The remaining eight digits are held in the blank 0 state.
  • FIG. 5b illustrates the state in which, after the first addition, an added result 5 is set in the display register R
  • the subtraction for R is carried out by the information Dt (refer to FIG. 1) for subtracting 1 as is generated in the period of time T of the timing pulse shown in FIG. 2b, and through the adder AD.
  • the multiplicand 5 in Ry is successively added to the information in R in the same way, until the information at LSD of R becomes 0.
  • the situations are illustrated in FIGS. 50 and 5d.
  • the calculation is stopped.
  • the calculated result 15 is shifted rightwards from R to R and is set as in FIG. 5e.
  • the multiplication is performed.
  • 1 is successively subtracted from the least significant digit to the most significant digit.
  • the subtraction at each digit of the multiplier is carried out at LSD of R
  • processing is as below.
  • the division of 4 2 2 is executed.
  • the first operand 4 is stored in the register Ry, while the second operand 2 is stored in the circulative memory circuit including the register R
  • the calculation starting key (ElKey) is depressed.
  • a shift instruction is first issued, so that the second operand 2 is shifted from the register R through the line F L to the register Ry and is stored therein, while the first operand 4 is shifted from the register Ry through the line FL, to the circulative memory circuit composed of the register R adder AD and feedback line FL, and is storedtherein (FIG.
  • FIG. 70 shows a state in which the subtraction has been conducted once, and in which an information (calculated result) I indicating the one subtraction is set (added) at LSD of R
  • the subtractions are executed between R and Ry until the information of R becomes 0.
  • the answer 2 of the division can be obtained at LSD of R as shown in FIG. 7d.
  • the addition of l to the information of R is effected from the input Dt, shown in FIG. 1.
  • the eight-digit register Ry is prepared for eight-digit numerical information.
  • one more digit is added to make the memory capacity of the register Ry 9 digits, that the memory capacity of the circulative memory circuit including the register R is accordingly made 18 digits, and that a digit signal Dt is added to those Dt, Dt
  • the delay type full adder for binary-coded decimal signals is adopted. It forms the loop-like closed circuit jointly with the display shift register having a capacity integral times as large as that of the calculating shift register, and conducts additions in the series synchronism system. Therefore, the system of the invention makes it unnecessary to employ a number of controlling gates between shift registers, as compared with a prior-art system shown in FIG. 8 in which the shift registers of equal capacities are arrayed in parallel.
  • the use of the delay type binary-coded decimal adder makes it possible to constitute of a single line the line of the loop-like closed circuit which is formed by the display register R the delay type adder AD, a line a and the line FL A line b for the connection between the calculating register Ry and the adder AD can also be constituted of a single line.
  • the number of controlling gate circuits to be connected anteriorly and posteriorly to each shift register can be made small.
  • the correction memory circuit DM for correcting a pure binary number to a binary-coded decimal number, and the circulating register for display can be combined into one unit. Therefore, the circuit arrangement can be made simple.
  • the above feature is very advantageous in the degree of integration and the arrangement of the respective elements.
  • the display register forms, along with the delay type adder, the loop-like closed circuit. Therefore, a predetermined position of the display register can be easily selected and controlled by the sector pulse.
  • Processed information signals from the adder AD (information signals for display) can be successively set from the least significant digit of the lower digit portion one of the series-connected display shift registers. Therefore, the memory capacity for the display information signal can be made equal to the total capacity of the loop-like closed circuit. For example, in the case of the embodiment, a calculated result of at most 16 digits can be stored. In this case, when the number of digits of the indicating unit is eight, it is also allowed to control the lines FL and FL in FIG. 1 by making use of the foregoing sector pulses Sp, so as to display the higher eight digits or the lower eight digits. Overflow due to multiplication processing etc. can be prevented in this way.
  • a calculated result to be displayed is circularly held by the loop-like closed circuit which includes the display register and the delay type adder. Therefore, it is not necessary to provide any special feedback path for the display register, and the dynamic display system can be easily adopted for the indicator unit (IN). More specifically, information is transmitted from the LSD part of the higher-digit display register R or that of the lowerdigit display register R to the indicator in FIG. 1 every digit by means of a gate controlled by every fourbit time. Thus, dynamic display signals can be easily taken out.
  • the digital processing system according to the present invention, calculating processing such as multiplication and division can be easily executed in the simple construction and using the binarycoded decimal numbers.
  • the circulative register can have the length shortened in its joint use for the memory circuit for the binary-coded decimal number correction.
  • overflow can be aliminated with the resultant various advantages.
  • a digital processing system comprising a binarycoded decimal full adder having two binary full adders and a correction detecting memory circuit arranged therebetween and serving to subject two information inputs to addition and subtraction, the correction de tection memory circuit having a memory capacity, a first shift register having a fixed memory capacity and having an output connected to an input of said binarycoded decimal full adder, a second shift register having a memory capacity and having an output connected to another input of said binary-coded decimal full adder, means for connecting an output of said binary-coded decimal full adder with an input of said second shift register so as to form a loop-like circuit of said second shift register and said binary-coded decimal full adder, the total memory capacity of said second shift register and said detecting memory circuit being n times as large as said memory capacity of said first shift register where n is an integer of at least 2', and means for actuating the binary-coded decimal full adder to define a plurality of predetermined positions of said second shift register, information signals at said predetermined
  • said correction detection memory circuit means includes first, second and third delay circuit means, correction judging circuit means, generator means, said first full adder having an output connected to said first delay circuit means and another output connected to said second delay circuit means and to said correction judging circuit means, said second delay circuit means having an output connected to a third input of said first full adder which receives an output from said first shift register and an output from said calculating shift register means, said first delay circuit means having an output connected to a first input of said second full adder and an output connected to said correction judging circuit means, said correction judging circuit means having an output connected to the third input of said first full adder and an output connected to said generator means, said generator means having an output connected to a second input of said second full adder, said second full adder having an output connected to said second shift register and an output connected to an input of a gate circuit means, said gate circuit means adapted to receive a predetermined timing signal at another input thereof and having an output connected to said third delay circuit means, said third delay circuit means having
  • a digital processing system comprising binarycoded decimal full adder means for subjecting two information inputs to at least one of addition and subtraction, said full adder means including circuit memory means having a fixed memory capacity, display shift register means providing an output to one input of said full adder means and including first and second series connected shift registers each having a memory capacity, and calculating shift register means having a predetermined memory capacity, said calculating shift register means receiving the output of said display shift register means at an input thereof and providing an output to another input of said full adder means, the output of the full adder means being applied to an input of the second shift register and the output of the first shift register being applied to the one input of said full adder means so as to form a loop-like circuit for circulation of information signals through the full adder means and the display shift register, the total memory capacity of said circuit memory means of said full adder means and said display shift register means being n times as large as the memory capacity of said calculating shift register means, where n is any integer greater than 1.
  • a digital processing system wherein the memory capacity of the first display shift register is equal to the memory capacity of the calculating shift register means, and the memory capacity of the second display shift register is equal to the memory capacity of the first display shift register minus the memory capacity of the circuit memory means of said full adder means.
  • said binary-coded decimal full adder means includes first and second binary full adders and correction detection memory circuit means connected therebetween, said correction detection memory circuit means including said circuit memory means.
  • a digital processing system further comprising display means for displaying the contents of said display shift register means.
  • a digital processing system comprising binarycoded decimal full adder means for subjecting two information inputs to at least one of addition and subtraction, said binary-coded decimal full adder means including first and second binary full adders and correction detection memory circuit means connected there between; display shift register means providing an output to one input of said full adder means, said display shift register means including first and second series connected shift registers; and calculating shift register means having a predetermined memory capacity, said calculating shift register means receiving the output of said display shift register means at an input thereof and providing an output to another input of said full adder means; the output of the full adder means being applied to an input of the second shift register and the output of the first shift register being applied to the one input of said full adder means so as to form a loop-like circuit for circulation of information signals through the full adder means and the display shift register; said correction detection memory circuit means including first, second and third delay circuit means, correction judging circuit means, and generator means, said first full adder having an output connected to said first delay circuit means and another output connected to said second delay
  • a digital processing system comprising binarycoded decimal full adder means for subjecting two information inputs to at least one of addition and subtraction, said full adder means having circuit memory means having a memory capacity, display shift register means including a first and a second shift register connected in series and having memory capacities, respec tively, calculating shift register means having a memory capacity, first means for supplying an output of said first shift register to an input of said full adder means, second means for supplying an output of said full adder means to an input of said second shift register, third means for supplying an output of said calculating shift tegers of at least one, and N N

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Complex Calculations (AREA)
US00317303A 1971-12-24 1972-12-21 Serial bcd adder Expired - Lifetime US3813623A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP46104579A JPS5219746B2 (de) 1971-12-24 1971-12-24

Publications (1)

Publication Number Publication Date
US3813623A true US3813623A (en) 1974-05-28

Family

ID=14384331

Family Applications (1)

Application Number Title Priority Date Filing Date
US00317303A Expired - Lifetime US3813623A (en) 1971-12-24 1972-12-21 Serial bcd adder

Country Status (8)

Country Link
US (1) US3813623A (de)
JP (1) JPS5219746B2 (de)
CA (1) CA999084A (de)
DE (1) DE2262796A1 (de)
FR (1) FR2165625A5 (de)
GB (1) GB1377860A (de)
IT (1) IT972711B (de)
NL (1) NL7217471A (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4172288A (en) * 1976-03-08 1979-10-23 Motorola, Inc. Binary or BCD adder with precorrected result

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2872107A (en) * 1951-05-16 1959-02-03 Monroe Calculating Machine Electronic computer
US3214576A (en) * 1959-10-27 1965-10-26 Gen Electric Multiple accumulators
US3249745A (en) * 1962-01-09 1966-05-03 Monroe Int Two-register calculator for performing multiplication and division using identical operational steps
US3571582A (en) * 1968-02-29 1971-03-23 Gen Electric Serial bcd adder/subtracter utilizing interlaced data
US3584206A (en) * 1968-02-29 1971-06-08 Gen Electric Serial bcd adder/subtracter/complementer utilizing interlaced data
US3621219A (en) * 1967-08-15 1971-11-16 Hayakawa Denki Kogyo Kk Arithmetic unit utilizing magnetic core matrix registers
US3707622A (en) * 1969-12-15 1972-12-26 Omron Tateisi Electronics Co Digital serial arithmetic unit

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2872107A (en) * 1951-05-16 1959-02-03 Monroe Calculating Machine Electronic computer
US3214576A (en) * 1959-10-27 1965-10-26 Gen Electric Multiple accumulators
US3249745A (en) * 1962-01-09 1966-05-03 Monroe Int Two-register calculator for performing multiplication and division using identical operational steps
US3621219A (en) * 1967-08-15 1971-11-16 Hayakawa Denki Kogyo Kk Arithmetic unit utilizing magnetic core matrix registers
US3571582A (en) * 1968-02-29 1971-03-23 Gen Electric Serial bcd adder/subtracter utilizing interlaced data
US3584206A (en) * 1968-02-29 1971-06-08 Gen Electric Serial bcd adder/subtracter/complementer utilizing interlaced data
US3707622A (en) * 1969-12-15 1972-12-26 Omron Tateisi Electronics Co Digital serial arithmetic unit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4172288A (en) * 1976-03-08 1979-10-23 Motorola, Inc. Binary or BCD adder with precorrected result

Also Published As

Publication number Publication date
IT972711B (it) 1974-05-31
FR2165625A5 (de) 1973-08-03
JPS5219746B2 (de) 1977-05-30
JPS4871154A (de) 1973-09-26
CA999084A (en) 1976-10-26
NL7217471A (de) 1973-06-26
DE2262796A1 (de) 1973-07-12
GB1377860A (en) 1974-12-18

Similar Documents

Publication Publication Date Title
US4635292A (en) Image processor
US3304418A (en) Binary-coded decimal adder with radix correction
US5132925A (en) Radix-16 divider using overlapped quotient bit selection and concurrent quotient rounding and correction
US3535498A (en) Matrix of binary add-subtract arithmetic units with bypass control
US3553445A (en) Multicipher entry
US3202805A (en) Simultaneous digital multiply-add, multiply-subtract circuit
US4381550A (en) High speed dividing circuit
US4065666A (en) Multiply-divide unit
US3308281A (en) Subtracting and dividing computer
US6519621B1 (en) Arithmetic circuit for accumulative operation
US4692891A (en) Coded decimal non-restoring divider
GB2262637A (en) Padding scheme for optimized multiplication.
US3813623A (en) Serial bcd adder
US4013879A (en) Digital multiplier
US3627999A (en) Two{40 s complement negative number multiplying circuit
US4380051A (en) High speed digital divider having normalizing circuitry
US4935890A (en) Format converting circuit for numeric data
GB742869A (en) Impulse-circulation electronic calculator
US3735107A (en) Coded decimal divider with pre-conditioning of divisor
GB2265739A (en) Non-restore division with dividend-width ALU
GB1105694A (en) Calculating machine
US4025773A (en) Enhanced apparatus for binary quotient, binary product, binary sum and binary difference generation
EP0529755B1 (de) Verfahren und Anordnung zur Negierung eines Multiplikationsoperanden
US3564225A (en) Serial binary coded decimal converter
US3657529A (en) Entry mark system for entry and display of numbers