GB1377860A - Digital processing system - Google Patents

Abstract

1377860 Data processing HITACHI Ltd 22 Dec 1972 [24 Dec 1971] 59464/72 Heading G4A The output of a binary coded decimal full adder AD (Fig. 1) including a correction circuit is connected, via cascade connected shift registers Rxa, Rxb, to a further shift register Ry, the output of which is connected to the full adder. As described an indicator IN receives an input from the least significant digit position of the registers Rxa, Rxb. Addition.-The outputs of shift registers Rxa, Ry are connected to a first binary full adder FA 1 (Fig. 3), binary carry being effected by a one bit delay circuit DL 2 . The output of the adder FA 1 is fed via a four bit delay circuit DL 1 controlling the correction circuit CC to a second full adder FA 2 receiving its second input from a correction generator CG, supplying a digit 6 when enabled by the correction circuit CC. Carry in the second adder is effected via a one bit delay DL 3 disabled when the most significant bit of a digit is being processed. The output of adder FA 2 is connected to the shift register Rxb. A sum from adder FA 1 of between 0 and 9 results in no decimal carry to the next digit from delay circuit DL 2 and no operation of the correction circuit CC. A sum of between 10 and 15 results in operation of the correction circuit CC to provide both a decimal carry to adder FA 1 and generation of the digit 6 to be added to the sum from adder FA 1 in adder FA 2 . A sum of between 16 and 19 results in a decimal carry being generated by adder FA 1 which operates correction circuit CC to generate the digit 6. In a modification (Fig. 4) for sums between 10 and 15 the decimal carry is derived from the delay circuit of the second full adder. Multiplication.-This is effected by repeated addition. The multiplicand, stored in register Ry, is added a number of times determined by the multiplier, stored in register Rxa, the result being stored in register Rxb and the multiplier decremented each time. The number in register Rxb is shifted one step right as each digit of the multiplier is processed. When the multiplier becomes zero the resulting product is shifted into register Rxa. Division.-This is effected by repeated subtraction. The dividend is stored after depression of the equals key in register Rxb and the divisor in register Ry. The contents of register Ry are then subtracted from the contents of register Rxb until the contents of the latter becomes zero, the number of times this is effected being stored in register Rxa.