US3811092A - Variable-ratio electronic counter-divider - Google Patents

Variable-ratio electronic counter-divider Download PDF

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US3811092A
US3811092A US00298424A US29842472A US3811092A US 3811092 A US3811092 A US 3811092A US 00298424 A US00298424 A US 00298424A US 29842472 A US29842472 A US 29842472A US 3811092 A US3811092 A US 3811092A
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scale
input
output
counter
inputs
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R Charbonnier
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Adret Electronique SA
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Adret Electronique SA
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle

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  • H03k 23/06 shifts in whole units under the action of control signals [58] Field of Search 328/39-58 applied thereto, the second scale including a fixedcapacity counter set to count permanently and to [56] References Cited apply to the first scale a control signal which is en- UNITED STATES PATENTS abled for a predetermined number of counts of the 3.581.116 5/1971 Leostic 328/41 Second 3.218.560 1 H1965 Peters 328/39 Such a divider is adapted for operation at frequencies 3.624.517 lI/l97l Kobayashi 328/44 higher than that of the prior art dividers, and will be 3.646.371 2/1972 F130 328/48 used in frequency genefators 3.426.180 2/1969 Smith 328/39 3.671.872 6/1972 Pauly 328/41 15 Claims, 12 Drawing Figures WENTEDHAY 14 1974 SHEET 1 [IF 4 FIG.2
  • This invention relates to the variable capacity electronic counters used in frequency dividers.
  • variablecapacity counter which constitutes the basic element of these dividers work at higher frequencies than those which are currently made possible by known connections.
  • a known connection consists e.g. of associating with the counter a coincident circuit with a predetermined digital value N. At the Nth pulse, the coincident'circuit returns the counter to zero.
  • the connections resolution time is then equal to the sum of the coincident circuits response time, to which must be added the counters return-to-zero time and its re-sensitization time. This resolution time is thus considerably increased at the moment of coincidence.
  • the maximum frequency that the divider can handle is the inverse of its working cycles longest resolution time.
  • this method does not enable the de vices maximum resolution time, which is governed by the sensing time of the counters N-P or P state and the switching times, to be reduced as much as one would wish.
  • the invention proposes the making of a divider wherein the resolution time is constant and reduced to the response time of a J K flip-flop, which makes it possible to work at considerably higher frequencies than those made possible by known connections.
  • the frequency divider in accordance with the invention includes first and second division scales connected in series, and is chiefly characterised in that the first scale is set so that its division ratio shifts in whole values under the action of control signals, the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale a control signal which is enabled for a predetermined number of counts of the second scale.
  • the second scale moreover includes means of comparing the counters count with at least one instruction number to enable at least one control signal and also shiftthe division ratio by at least one unit.
  • the counter comprises a -N scale followed by a -two scale
  • the comparator is set to compare the binary number expressed by the logical levels of the parallel outputs of the -N scale with a binary number n a/2, n being the instruction number and a a zero value when is even, and equal to I when n is odd
  • the device comprises means, associated with the comparator, of enabling or otherwise the comparator output signal, according to the parity of n, said means only acting for N of the counters counts.
  • FIG. 1 is a basic diagram of a divider connection in accordance with afirst form of embodiment of the invention
  • FIG. 2 shows a first form of embodiment of the leading division scale which it comprises
  • FIG. 3 shows thewave shapes of the output signal the circuit in FIG. 2;
  • FIG. 4 shows a variant of the division scale
  • FIG. 5 shows the connection of the .I inputs of the flip-flops of the circuit in FIG. 4;
  • FIG. 6 shows a first form of embodiment of the counter-divider comprised 'in the connection in FIG. 1;
  • FIGS. 7 and 8 show two variants of this counterdivider
  • FIG. 9 is a basic diagram of a'counter-divider in accordance with a second form of embodiment.
  • FIG. 10 illustrates a particular form of embodiment given as an example
  • FIG. 11 is a basic diagram of a counter-divider in accordance with a third form of embodiment'of the invention.
  • FIG. 12 illustrates a more particular form of embodiment, designed to provide a division ratio varying between 20 and 29.
  • FIG. 1 shows a leading divider 1 which receives at E the frequency F pulses whose frequency is to be divided, andv whose output drives a tailing counterdivider 2 which delivers the divided frequency at its output S.
  • Dividers 1 and 2 are of the type known as division scale (scale-of-two with a ratio 2, etc.).
  • the counter 2 has a capacity N and is set, as soon as it reaches a count n, to send an information to a control input C of the divider 1, i
  • the divider 1 is set sd as to have a division ratio (M) so long as this information is not enabled, and to pass to the capacity (M+l') when this information is. en
  • the switching information it is not essential for the switching information to be enabled during the N-n last counts of each cycle of the counter 2. To obtain the required result, it is sufficient for said information to be enabled, during each cycle, for a certain number (N-n) of counts of the counter 2 and disabled for the it other counts of the cycle, these two series of counts being able to be interleaved in any way.
  • each output pulse of the divider 1 will be generated by M input pulses, while during the n counts, each output pulse of the divider. 1 will be generated by (M+l) input pulses.
  • the N counts of each cycle of the counter 2 at the end of which it will be returned to zero and will supply at pulse at its output S, will correspond to: M+l )n M (N-n) MN n input pulses of the connection.
  • the counter 2 works on a-frequency. 3 or 4 times weaker than the input frequency, and does not comprise any return-to-zero device for a variable capacity.
  • the result is that it can be made very simply and inexpensively, without thereby limiting the connections working frequency; for the latter to depend only on the divider 1, it is sufficient that the coincidence device between the count of the counter 2 and the instruction n should, in the example in question, be capable of switching at least at the frequency F/3, which is easy to achieve.
  • the connections limit working frequency is then completely independent of n.
  • FIGJZ shows apreferred formof embodiment of the divider l, in the case where M 3.
  • the flip-flops 4 and 6 have their K inputs connected to a one logical level, while the K input of the flip-flop 5 is connected to the 6 output of the flipflop 6.
  • the Q output of the flip-flop 5 is connected to the J input of flip-flop 4, while the Q output of the flipflop 4 is connected on the one hand to the input of the counter 2 and on the other hand to the J inputs of the flip-flops 5 and 6.
  • the latter is moreover of the type comprising two inputs J and J driving an internal AND gate 6a.
  • the J input is connected to the switching terminal C26 of the counter 2.
  • FIG. 3 shows, at (a), (b) and (0) respectively, the wave'shapes of the Q outputs of the flip-flops 4, 5 and 6, when the level is applied at J (which corresponds to the n first counts of the counter'2) and at (d), (e), (f), the same outputs when the one level is applied at J (which corresponds to the (N-n) last counts of the counter 2).
  • the input signal has been shown at (E).
  • flip-flop 6 not being actuated, its 0 output, and thus the K input of the flip-flop 5, is at One level. The result is that when the wavefront descends from the next clock pulse, the flip-flop 5 will be de-actuated. The J input of the flip-flop 4 will then go from One level, so that at the next clock pulse, the flip-flop 4 will again be actuated.
  • flip-flops 4 and 5 will therefore not change their condition, while flip-flop 6 will be deactuated, which makes the K input of flip-flop 5 go to one.
  • the informations on the J inputs of the top flip-flops 5-6 are taken into account by the leading flip-flop 4, and therefore by the connection just before the wavefront descending from the 0 signal of the flip-flop 4.
  • this counter 2 and its circuit for comparing count and instruction must simply work at the maximum at frequency F/M.
  • FIG. 4 shows a divider making it possible to programme the division ratio, either from '20 to 29 or from 30 to 39 or from 40 to 49 or from 50 to 59, according to the position of the switches 12, 13, 14.
  • the leading counter is made up of five flip-flops 7 to l 1, connected as in FIG. 2 as regards their terminals C, K, O and, in the case of flip-flop 7, terminals J and Q.
  • flip-flop 11 has two terminals J and J, connected to an internal AND gate (not shown) while flip-flops 8, 9 and 10 each have four terminals J1, J'l, J2, J2, connected to an internal logical unit which has been shown separately in FIG. 5.
  • his logical unit includes two AND gates 10a, 10b and an OR gate 10c to form the J K flip-flop 18, whose C input I is connected to the terminal and whose Q output is connected to the switching terminal C26 of the divider 1.
  • An AND gate 19 enables the J input only when the coincidence at 0 is present, and its input connected to the output of 17 comprises a logical inverter element, without thecoincidence at n being so. In this Way, when n O, the J and K inputs of the flip-flop are prevented from being enabled simultaneously, which would make it deliver a toothed waveform at the clock frequency.
  • this flip-flop is required to deliver a signal enabled for the n first pulses of each cycle received by the circuit 15 and disabled for the N-n last pulses.
  • the element 20 is a binary amplitude comparator, which compares the binary instruction number n of the corresponding binary number with the count of the counting .At the fourth'pulse, flip-flop5 will therefore be decircuit 15. According to whether the former is greater than, equal to or less than the latter, the output terminal a or b or c is enabled.
  • a device symbolised by the block 3 enables either output a or output b or output c or the logical sum of outputs b and c to be connected to terminal C26.
  • the terminal C26 is enabled, so that the divider has a ratio equal to MN n, as explained above.
  • the division ratio is thus Mn+(M+l )N-n (M+l )N-n.
  • FIG. 8 does not make it possible to obtain an inverted spectrum.
  • a counting circuit 15 of a particular type, known as a bit rate multiplier (or more commonly by the English abbreviation B.R.M.).
  • Such a circuit has a counting capacity N and whean an n instruction is applied to it, it delivers atan output (connected here to C26) n output pulses per counting cycle.
  • N a counting capacity
  • dividers l and 2 may be devised by a technician, without departing from the spirit of the invention.
  • the values of M, N and n may be any whatsoever. It is even possible, providing the forms of embodiment in FIGS. 6 or 8 are used, to make n vary between 0 and 10, which will give a division ratio going e.g. from 30 to 40 (or, more generally, from 10 M to l0 (M+l), known counter-dividers do not enable this result to be obtained.
  • the device described with reference to FIGS. 1 to 7 allows a division ratio in the form MN n or (M+l )N n or (M+l )N n l to be obtained.
  • N 10 and n programmable from 0 to 9 will be taken.
  • M will then be the tens digit of the number which expresses the division ratio. If, e.g., M 4, the division ratio will be programmable from 40 to 49 or from 50 to 41 or from 49 to 40.
  • a divider with a ratio programmable e.g. from 43 v to 52 or, more generally, in the form MN n +p, i.e. from any digit of the units.
  • a second binary amplitude comparator comparing the count of the counter with the instruction number p 'and a logical circuit which supplies a supplementary control signal suitable to shift the division ratio of the first scale by two units.
  • FIG. 9 again shows the elements already described above, bearing the same reference numbers, i.e.:
  • a logical circuit 22 made so as to enable its output 22a, its output 22b, or its output 22c according to the condition of the respective outputs 20a and 21a of the comparators.
  • 22a will be enabled when'20a and 21a are simultaneously enabled: 22b will be enabled I when only one of the two outputs 22a or 22b is enabled.
  • the leading divider l is set so that its division ratio is equal to M+2, M+l or M, according to whether the control input 22a, 22b or 220 is enabled.
  • the'working of the connection is as follows:
  • the count of 15 is less than n and p, so that the outputs 20a and 21a are simultaneously enabled and the division ratio of I is equal to
  • the count of 1 5 is less than p but greater than n, so that only the output 21a is enabled andthe division ratio of l is equal to n+1.
  • the binary comparator 2 in FIG. 2 can then be made in the form of three NAND gates 211- 212-213, connected to the weight outputs l, 2 and 4 of the counter 15 as the diagram shows. It is obvious that the output of gate 213 is at One level when at least one of its two inputs is at zero level. Now, the output of gate 211 is at zero level when the weight outputs l and 4 of the counter 15 are enabled, i.e. for'count 5; the output of gate 211 is at zero level when'the weight outputs 2 and 4 of counter 15 are enabled, i.e. for count 6 and the two outputs of gates 21 1 and 212 are simultaneously at zero level when the weight outputs l, 2 and 4 of counter 15 are enabled, i.e. for count 7.
  • the logical circuit 22 in FIG. 9 is made in the form of a NOR gate 221 and a NAND gate 222, connected to the output a of the binary amplitude comparator 20 and to the output of the gate 213 in the manner shown.
  • the outputs of gates 221 and 222 are respectively connected to the parallel inputs B1 and A1 of a shift register 1 whose two other parallel inputs Cl and D1 are at Zero level (symbolised by a grounding).
  • These two clock inputs CC are connected to the input terminal E of the connection; the series input SI is put at One level (symbolised by the sign the QD parallel output is on the one Hand connected to the input of the counter and on the other hand applied to the mode control line MC.
  • the other parallel outputs, not connected, are not shown.
  • the informations present at the parallel inputs are transferred to the outputs by the first clock pulse, therefore QD goes to zero.
  • the result is that MC goes.tozero.-
  • the clock pulses then have the effect of transferring to B1 the information present at A1, to C1 the information present at B1, and to QD the'information present at D1. If B1 is enabled, three pulses are needed to make this transfer. If Al is enabled, Bl not being so, four pulses are needed to make this transfer.
  • the register 1 will act as a divider by' 3 when B1 is enabled (irrespective of the condition of Al); as a divider by 4 when Al is enabled, B1 not being so; and as a divider by 5 when neither Al nor B1 is enabled.-
  • the division ratio of the register will be equal to 4 for the n first counts and for the counts 5-6-7 of the counter 15, while it will be equal to 3 for the counts 8 and 9 and for the 5-n counts following the n first.
  • a division ratio of the connection equal to 4 (n+3) 3 (2+5n) 33+n.
  • This ratio therefore varies from 33 to 42 when n is programmed from 0 to 9. To obtain a variation of 33 '8 to 43,,it is sufficient to apply a dummy code to the inputs of 20. 7
  • the shift register 1 shown in FIG. 9 could be used as a first division scale in any one of the connections illustrated in FIGS. 1 to 8 (for example, this shift register can be the 74-95 type manufactured by the Company TEXAS Instruments lnc.”). 7
  • comparators do not necessarily use the binary code and can moreover be made in the form of a suitable logical circuit.
  • the output signal may be very dissymetrical; in fact, as the division ratio of the first scale varies during the second scales counting cycle, the durations of the two halfperiods of the output signal can correspond to two input pulse numbers which are substantially different from each other.
  • connection illustrated in FIGS. 1 1 and 12 is to eliminate this disadvantage and obtain a strictly symmetrical output signal for the even division ratiosand, for the odd division ratios, an output signal such-thatthe duration of one of the two half-periods does not exceed by more than one step the duration of the other (the step being the duration of an input pulse of the connection).
  • FIG. 11 shows a first division scale 1 fitted with a pulse input E and a control input C which, when it is enabled, makes the division ratio go from an M 1 value to an M value.
  • the output of this first scale drives a counter 15 fitted with an output S which constitutes the output of the connection.
  • a binary amplitude comparator 20 receives, at its inputs A A and A the respective weight codes 2,-4 and 8 of a binary coded in- I struction number n.
  • the code 1 is applied to an input of an AND gate 23.
  • the output A B of the comparator isconnected to the input C of scale 1.
  • a zero logical level (which is symbolised by the ground) is permanently applied to the One weight input A of the comparator 20. 1
  • the counter 15 consists'of a scale-of-five with out puts a, b and c with respective weights 1, 2 and 4,' respectively connected to the inputs 8,, B and B of the comparator 20, and a scale-of-two whose-output; d is connected on the one hand to the output S and on the other hand to the other input ofthe gate 23.
  • the output of the gate 23 is connected'to a logical circuit 24 with two outputs, respectively connected to the two inputs a B and a B of the comparator 20.
  • n If n is even, the code (1) willnever be enabled.
  • the logical circuit 24 is set, when its input is thus at Zero level, to enable its output a B.
  • n if n is odd, the code (1) is enabled, so that the input of the circuit 24 is enabled during the five last counts of the counter 15.
  • the circuit 24 is set so that it then-enables its output a B. It should be noted that the comparator will compare the weight digits 1, 2 and 4 of the count of the counter 15 with the weight digits 2, 4
  • n is even; the output a B being enabled, A B is too and the division ratio of the scale 1 is M. Consequently, the division ratio of the connection is then equal to: 2M (5-n/2) n (M+ l).
  • the output signal picked up at S is then strictly symmetrical, since it corresponds to the same numberof input of input pulses for each of the two halves of the cycle. 7
  • FIG. 12 shosw a simplified connection designed to obtain this particular result.
  • the code 1 of the number n is then applied directly to the input a B of the comparator 20 and, after inversion by a logical inverter 25, to the input a B.
  • the scale 1 is made in the form of a shift register with a series input SI at One level, its clock inputs CC connected to each other to constitute the input E of the connection, its parallel inputs A1, B1 at One level, its parallel input D1 at Zero level, and its parallel input Cl connected to the enabling terminal A B.
  • the parallel output QD is connected on the one hand to the input of the counter 15 and on the other hand to the mode control input MC of the register.
  • the inverter 25 en ables the input B of the comparator. 20, while with n'odd, it enables the input L B.
  • Frequency divider comprising a first and a second division scales each having one pulse input and one pulse output, the pulse output of thesecond scale being.
  • the first scale has a control input and is set so that its division ratio shifts in whole units under the action of control signals applied to its control-input
  • the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale control input a control signal and means for enabling the control signal for a predetermined number of the counts displayed by the second scale.
  • Frequency divider in accordance with claim 1, characterised in that the second scale includes a decimal counter and a binary amplitude comparator which compares the count of said counter with said predetermined number.
  • Frequency divider in accordance with claim 1 characterized in that the second scale moreover incharacterised in that at least one cludes means for comparing the count of the fixedcapacity counter with at least one instruction number to enable at least one control signal and thus shift the division ratio by at least one unit.
  • Frequency divider in accordance with claim 4 of the instruction numbers is variable.
  • the counter being decimal, a first division ratio shifts in whole units under the action of control signals applied to its control input
  • the second scale including a fixed-capacity counter set to count permanently-and to transmit to the first scale control input a control signal and means for enabling the control signal for 'a predetermined number of the counts displayed by the second scale
  • the first scale including a number of J K flip-flops at least equal to the value which its division ratio assumes when the control signal is not enabled, the said flip-flops having clock impulse driven in synchronism by the frequency to be divided, the said flip-flops further having .I and K inputs and Q and Q outputs, the Q output of the first flip-flop driving the J inputs of the other flip-flops andthe pulse input of the second scale, the 6 output of each of said other flip-flops driving the K input of the next flip-flop down with the exception of the first, the Q output of the second flip-flop driving the J input of the first, the K inputs of the first and last flip-
  • Frequency devider comprising a first and a second division scales each having one pulse input and one pulse output, the pulse output of the second scale being connected to the pulse output of the first scale, wherein the first scale has a control input and is set so that its division ratio shifts in whole units under the action of control signals applied to its control input, the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale control input a control signal and meansfor enabling the control signal for a predetermined number of the counts displayed by the second scale, the first division scale comprising a shift register of the type having a mode control input which, according to whether or not it is enabled, makes it possible to obtain the transfer in parallel of information from the parallel inputs to the-corresponding parallel outputs thereof, or to obtain the gradual transfer of the information from one parallel output thereof to the following ones, one of the parallel outputs of said shift register being connected to the fixed-capacity counter and to the said mode control input and means for comparing the count of the fixedcapacity counter with at least one instruction number
  • Frequency divider comprising a first and a second division scales each having one pulse input and one pulse output, the pulse output of the second scale being 9.
  • the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale control input a control signal and means for enabling the conconnected to the pulse output of the first scale
  • the first scale has a control input and is set so that its division ratio shifts by one unit under the action of control signals applied to its control input
  • the second scale including a fixed-capacity counter set to count permanently and to transmit to the first scale control input a control signal
  • the second scalefurther including a binary amplitude comparator comparing the count of said fixed-capacity counter with an instruction number .to generate said control signals
  • the fixed-capacity trol signal for a predetermined number of the counts displayed by the second scale
  • -the second scale including a decimal counter having first and second outputs, means for generating a One logical level respectively at said first output when the count of-the decimal counter coincides with said predetermined number and at a second output when the said count coincides with
  • Frequency-divider in accordance with claim 14, characterised by a decimal counter comprising a scaleof-five followed by a scale-of-two,'and by a binary comparator having a first couple of inputs which respectively receive the 1 weight output of the counter and the 8 code of the instruction number, a second couple of inputs which respectively receive the 2 weight output of the counter and the 4code of the instruction number, a third couple of inputs which respectively receive the 1 weight output of the counter and the 2 code of the instruction number, a fourth couple of inputs which respectively receive the 5 weight output of the counter and a Zero logical level, and a fifth couple of inputs respectively connected to the 1 code of the instruction number, directly and via a logical inverter, said couples of inputs having priorities decreasing in the order in which they are enumerated.

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US3949311A (en) * 1974-02-27 1976-04-06 Siemens Aktiengesellschaft Ring counters with synchronously controlled counting flip-flops
US3970941A (en) * 1975-02-18 1976-07-20 Texas Instruments Incorporated Fast programmable divider with a new 5-gate flip-flop
US3976946A (en) * 1974-01-05 1976-08-24 U.S. Philips Corporation Circuit arrangement for frequency division by non-integral divisors
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US4234849A (en) * 1976-07-26 1980-11-18 Hewlett-Packard Company Programmable frequency divider and method
US4264863A (en) * 1977-11-10 1981-04-28 Tokyo Shibaura Denki Kabushiki Kaisha Pulse swallow type programmable frequency dividing circuit
US4316151A (en) * 1980-02-13 1982-02-16 Motorola, Inc. Phase locked loop frequency synthesizer using multiple dual modulus prescalers
US4325031A (en) * 1980-02-13 1982-04-13 Motorola, Inc. Divider with dual modulus prescaler for phase locked loop frequency synthesizer
US4575867A (en) * 1982-08-09 1986-03-11 Rockwell International Corporation High speed programmable prescaler
US20080222441A1 (en) * 2007-03-09 2008-09-11 Analog Devices, Inc. Software programmable timing architecture

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Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3976946A (en) * 1974-01-05 1976-08-24 U.S. Philips Corporation Circuit arrangement for frequency division by non-integral divisors
US3949311A (en) * 1974-02-27 1976-04-06 Siemens Aktiengesellschaft Ring counters with synchronously controlled counting flip-flops
US3970941A (en) * 1975-02-18 1976-07-20 Texas Instruments Incorporated Fast programmable divider with a new 5-gate flip-flop
US4234849A (en) * 1976-07-26 1980-11-18 Hewlett-Packard Company Programmable frequency divider and method
US4081755A (en) * 1976-08-10 1978-03-28 Litton Business Systems, Inc. Baud rate generator utilizing single clock source
US4072904A (en) * 1976-09-23 1978-02-07 The United States Of America As Represented By The Secretary Of The Navy Presettable rate multiplier
US4264863A (en) * 1977-11-10 1981-04-28 Tokyo Shibaura Denki Kabushiki Kaisha Pulse swallow type programmable frequency dividing circuit
US4316151A (en) * 1980-02-13 1982-02-16 Motorola, Inc. Phase locked loop frequency synthesizer using multiple dual modulus prescalers
US4325031A (en) * 1980-02-13 1982-04-13 Motorola, Inc. Divider with dual modulus prescaler for phase locked loop frequency synthesizer
US4575867A (en) * 1982-08-09 1986-03-11 Rockwell International Corporation High speed programmable prescaler
US20080222441A1 (en) * 2007-03-09 2008-09-11 Analog Devices, Inc. Software programmable timing architecture
US20080219112A1 (en) * 2007-03-09 2008-09-11 Analog Devices, Inc. Software programmable timing architecture
US8006114B2 (en) * 2007-03-09 2011-08-23 Analog Devices, Inc. Software programmable timing architecture
US8135975B2 (en) 2007-03-09 2012-03-13 Analog Devices, Inc. Software programmable timing architecture
US8732440B2 (en) 2007-03-09 2014-05-20 Analog Devices, Inc. Data pattern generator with selectable programmable outputs

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FR2157119A5 (enrdf_load_stackoverflow) 1973-06-01

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