US3798632A - Parallel addressed, multiplexed-driver plasma display system and method - Google Patents
Parallel addressed, multiplexed-driver plasma display system and method Download PDFInfo
- Publication number
- US3798632A US3798632A US00259128A US3798632DA US3798632A US 3798632 A US3798632 A US 3798632A US 00259128 A US00259128 A US 00259128A US 3798632D A US3798632D A US 3798632DA US 3798632 A US3798632 A US 3798632A
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- US
- United States
- Prior art keywords
- panel
- sector
- parallel
- display
- serial
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/297—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels using opposed discharge type panels
Definitions
- PATENTEMR 19 I974 i F I 5 F/GI. 2b
- Group multiplexing techniques have been applied to plasma display systems, which address a single line at a time, in order to reduce the number of active drivers required.
- This invention relates an adaptation of this technique, in which the multiplexed elements are organized to permit an entire group of 16 lines, for example, to be addressed in parallel without increasing the number of active drivers required.
- an external interface and a compact data structure are disclosed, which allow efficient picture generation in the parallel mode of operation.
- the standard serial mode of operation is most useful for vector generation, curve plotting, and producing characters of various sizes.
- Parallel operation is preferable where large blocks of text must be displayed, or an entire 5 l 2 X 512 line picture" rapidly updated.
- the serial mode writes 1,400 characters/second, or updates the display in 5.24 seconds, while the parallel mode of operation can produce text at 10,000 characters/second, and update the display in 0.33 seconds.
- the display unit has two 9-bit address registers (X and Y). a 16-bit data register, and control lines to produce write, erase, and clear commands and to select the mode of operation (serial or parallel).
- run-length coding developed for digital television applications, provides an efficient data structure in which each code tells the display how many successive cells are to be ON or OFF as a single raster is scanned from left to right. This technique reduces memory and transmission requirements, but allows only a single line to be scanned at a time.
- run-length coding is used with the l6-line parallel display by an external interface which decodes the incoming run-length codes serially into an 8K-bit map, and then scans its map 16 bits at a time into a sector of the display panel.
- the invention while being applicable because of the inherent memory of the display panel, it is not necessary for the entire 262K-bit map to exist at one time, and so only 8K bits of local buffer (enough for one sector) are required in the external interface.
- This invention avoids these problems in that it allows use of parallel address display (for increased writing speed) while utilizing a run-length code data structure, which greatly reduces computer memory and data transmission requirements.
- the invention features inelude: l Serial/parallel operation of the sector buffer (serial input/parallel output); (2) Use of temporary" bit map of only one panel sector at a time; (3) Alternately loading one bufier while scanning from another to achieve uninterrupted input/output.
- FIG. 1 is a block diagram of a plasma panel display system incorporating the invention
- FIG. 2A is a diagramatic illustration of a resistor diode multiplex system modified in accordance with the invention for parallel panel addressing
- FIG. 2(b) shows one resistor-diode element of the circuit of FIG. 2A
- FIG. 3 is a diagramatic illustration of the serial/parallel sector buffer system
- FIG. 4 is a block diagram of the interface using dual buffers.
- the panel P is a display panel (described in greater detail in Baker et al. US. Pat. No. 3,499,167 and other patents of the assignee hereof) constituted by row and column conductor support plates RS and CS, respectively, carrying a plurality of row conductors l0 and a plurality of column conductors 11, respectively.
- the conductors are coated with a dielectric or insulating coating or layer (not shown) and the plates are joined in spaced relation by a spacer sealant 12 to form a thin gas chamber in which is placed a working or electroresponsive medium, preferably under pressure.
- electroresponsive mediums may be used, but the preferred embodiment disclosed herein uses a neon-argon gas mixture (99.9% Ne, 0.1% Ar at a pressure of about 600 Torr) as the working medium between the transverse conductor arrays 10 and 11.
- a neon-argon gas mixture 99.9% Ne, 0.1% Ar at a pressure of about 600 Torr
- the row conductors R are supplied with operating (sustaining and discharge condition manipulating) voltages by way of a row resistor-diode multiplex circuit 15 and the column conductor 11 receive operating (sustaining and discharge condition manipulating) voltages from column resistor-diode multiplex circuit 16, both said multiplex circuits effectively electrically floating on their sustainer generators VSR and VSC, respectively, which have a point of common potential, S. G.
- Data and control 17 supplies timing control signals to multiplex circuits 15 and 16 and the row and column sustainer circuits VSR and VSC and include the circuits of FIGS. 3 and 4 hereof.
- each line of the 512 X5 12 line plasma panel connects to two diodes D and D and a resistor R.
- One diode D provides a current path for the sustaining signal a.
- the resistor R and remaining diode D perform an AND function, in which a writing pulse is applied to a group of resistors from a voltage pulser for the resistors, R R R and R The entire pulse voltage is dropped across those resistors whose associated diodes D are forward-biased, while a diode D which is back-biased or floating causes the pulse to be applied to the selected panel electrode. Whether a diode is forward biased or back-biased is controlled by diode control circuits D D D D which, with voltage pulsers R R,, R R receive controlling signals from the circuits of FIGS. 3 and 4.
- the resistor pulsers and diode switches are grouped in such a way that the selection of single diode switch enables one of 32 sectors of 16 panel lines, i.e., lines 0-15, 16-31, etc. (see FIG. 2). Within this sector, any or all of the 16 lines may be simultaneously addressed by selecting the desired corresponding resistor pulsers R R R etc. It should be noted that, for each line selected in the enabled sector, the pulse voltage is dropped across the corresponding resistor in 31 other sectors, drawing current which is not used in addressing a cell. This situation could be altered by selecting the sectors by resistor pulser and individual lines by diode switch, and thus never energizing more than 16 resistors at one time.
- the sustainer VS is shown as having the return connection a via diode D,,.
- serial mode of operation is most useful for vector generation, curve plotting, and producing characters of various sizes.
- Parallel operation is preferable where large blocks of text must be displayed, or an entire 5 l 2 X 512 line picture rapidly updated.
- the serial mode writes 1,400 characters/second, or updates the display in 5.24 seconds, while the paral lel mode of operation can produce text at 10,000 characters/second, and update the display in 0.33 seconds.
- the display unit has two 9-bit address registers (X and Y), a l6-bit data register, and control lines to produce write, erase, and clear commands and to select the mode of operation (serial or parallel).
- a DATA STRUCTURE AND INTERFACE FOR PICTURE GENERATION provides an efficient data structure in which each code tells the display how many successive cells are to be ON or OFF as a single raster is scanned from left to right. This technique reduces memory and transmission requirements, but allows only a single line be scanned at a time.
- run-length coding is adapted for use with the l6-line parallel display by an external interface which decodes the incoming runlength codes serially into an 8K-bit map, and then scans this map 16 bits at a time into a sector of the display panel. Because of the inherent memory of the display panel, it is not necessary for the entire 262K-bit map to exist at one time, and so only 8K bits of local buffer (enough for one sector) are required in the external interface.
- the buffer consists of sixteen 512- bit MOS shift registers 20, 21 36, initially connected in cascade (series).
- the cascade connection of the registers is established by AND gates 40, 41, 42 55, which have a load signal from control 17 via inverter l as one input and the output of its associated register as a second input, with the output of each AND gate being supplied to the next register in the sequence.
- the output from the line buffers to display data inputs occurs from AND Gates 80, 81, 82, on receipt of a scan input signal on the load/scan control line.
- each of the l6 shift registers is separately connected to one of the 16 display data inputs by a steering logic network 64, and the data is shifted out of each shift register 2036 (FIG. 3) and simultaneously displayed as the sector is scanned from left to right, by a low-speed clock 63 enabled by the display unit ready" line at the 50 KHz display unit speed.
- the entire buffer is loaded in 10 milliseconds, which is exactly the time required to scan one display sector. If two such 8K buffers are used alternately, one may be loaded while the other is scanned, and the display can accept an uninterrupted stream of run-length codes while writing at full speed. Steering logic 72 is used to control the alternate loading and scanning of sector buffers A and 8.
- a serial-type 512 line plasma display unit can thus be reorganized to permit the simultaneous addressing of an entire multiplex group (lo-line sector) without an increase in the number of driving or mixing elements. This allows an entire sector to be addressed each 20 mi croseconds, rather than a single point, and reduces the full screen update time from 5.24 seconds to 0.33 sec onds.
- Run-length coding provides an efficient way to store and transmit pictures for the display, rather than a complete 260K-bit map.
- An external interface containing a simple serial/parallel shift register cascade allows the codes to be translated into a single-sector bit map of only 8K bits.
- Two such local buffers used alternately allow a continuous stream of run-length codes to be accepted by the interface while allowing the display to write at full speed.
- first steering logic means for alternately and sequentially directing said run-length coded data to each said translating means, respectively,
- second steering logic means for selecting individual ones of said translating means and controlling the transfer of information in said parallel data bit format to said panel.
- said means for translating includes a plurality of line buffer shift registers, means alternately connecting said line buffer shift registers in cascade for input of said runlength coded data and in parallel for output of said parallel data bit format, respectively.
- a gas discharge display panel having inherent memory, a plurality of matrix display points defined by selectively energizable row-column conductor pairs for entry of information to said display panel and gas medium between said row-column pairs, means for applying a periodic sustaining voltage to said cross points and a source of serial run-length coded data bits,
- said means for translating includes a plurality of serial/parallel shift registers for translating said run-length coded signals to a single sector bit map having a selected number of discrete information bits and delivering said single sector bit map to said panel.
- Step 1 converting and storing the received serial format information to parallel format for a selected number of lines of one of the array of crossed conductors at one selected rate of speed
- Step 2 converting and storing the received serial format information for a like related number of lines of the same array of crossed conductors at said one rate of speed and simultaneously at a second selected rate of speed transferring the stored parallel format information of step 1 to display on said display panel,
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US25912872A | 1972-06-02 | 1972-06-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
US3798632A true US3798632A (en) | 1974-03-19 |
Family
ID=22983644
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US00259128A Expired - Lifetime US3798632A (en) | 1972-06-02 | 1972-06-02 | Parallel addressed, multiplexed-driver plasma display system and method |
Country Status (7)
Country | Link |
---|---|
US (1) | US3798632A (ja) |
JP (1) | JPS4963343A (ja) |
CA (1) | CA1009329A (ja) |
DE (1) | DE2327483A1 (ja) |
FR (1) | FR2187154A5 (ja) |
GB (1) | GB1436388A (ja) |
IT (1) | IT985643B (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4009335A (en) * | 1973-08-09 | 1977-02-22 | Stewart-Warner Corporation | Gray scale display system employing digital encoding |
US4149111A (en) * | 1977-11-25 | 1979-04-10 | Science Applications, Inc. | Method and apparatus for modulating the perceptible intensity of a light emitting display |
US4323896A (en) * | 1980-11-13 | 1982-04-06 | Stewart-Warner Corporation | High resolution video display system |
US4344622A (en) * | 1978-06-16 | 1982-08-17 | Rockwell International Corporation | Display apparatus for electronic games |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3600626A (en) * | 1969-11-26 | 1971-08-17 | Burroughs Corp | Multicell display device having communication paths between adjacent cells |
US3609746A (en) * | 1968-10-08 | 1971-09-28 | Univ Illinois | Apparatus for driving plasma panels |
US3665400A (en) * | 1971-04-19 | 1972-05-23 | Owens Illinois Inc | Switching circuits and method for diode elements in conductor selection matrices |
US3668688A (en) * | 1969-12-29 | 1972-06-06 | Owens Illinois Inc | Gas discharge display and memory panel having addressing and interface circuits integral therewith |
US3686661A (en) * | 1969-07-04 | 1972-08-22 | Philips Corp | Glow discharge matrix display with improved addressing means |
-
1972
- 1972-06-02 US US00259128A patent/US3798632A/en not_active Expired - Lifetime
-
1973
- 1973-05-30 DE DE2327483A patent/DE2327483A1/de active Pending
- 1973-06-01 FR FR7320110A patent/FR2187154A5/fr not_active Expired
- 1973-06-01 CA CA173,012A patent/CA1009329A/en not_active Expired
- 1973-06-01 IT IT50366/73A patent/IT985643B/it active
- 1973-06-01 JP JP48061770A patent/JPS4963343A/ja active Pending
- 1973-06-04 GB GB2650573A patent/GB1436388A/en not_active Expired
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3609746A (en) * | 1968-10-08 | 1971-09-28 | Univ Illinois | Apparatus for driving plasma panels |
US3686661A (en) * | 1969-07-04 | 1972-08-22 | Philips Corp | Glow discharge matrix display with improved addressing means |
US3600626A (en) * | 1969-11-26 | 1971-08-17 | Burroughs Corp | Multicell display device having communication paths between adjacent cells |
US3668688A (en) * | 1969-12-29 | 1972-06-06 | Owens Illinois Inc | Gas discharge display and memory panel having addressing and interface circuits integral therewith |
US3665400A (en) * | 1971-04-19 | 1972-05-23 | Owens Illinois Inc | Switching circuits and method for diode elements in conductor selection matrices |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4009335A (en) * | 1973-08-09 | 1977-02-22 | Stewart-Warner Corporation | Gray scale display system employing digital encoding |
US4149111A (en) * | 1977-11-25 | 1979-04-10 | Science Applications, Inc. | Method and apparatus for modulating the perceptible intensity of a light emitting display |
US4344622A (en) * | 1978-06-16 | 1982-08-17 | Rockwell International Corporation | Display apparatus for electronic games |
US4323896A (en) * | 1980-11-13 | 1982-04-06 | Stewart-Warner Corporation | High resolution video display system |
Also Published As
Publication number | Publication date |
---|---|
CA1009329A (en) | 1977-04-26 |
GB1436388A (en) | 1976-05-19 |
FR2187154A5 (ja) | 1974-01-11 |
IT985643B (it) | 1974-12-10 |
JPS4963343A (ja) | 1974-06-19 |
DE2327483A1 (de) | 1973-12-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: OWENS-ILLINOIS TELEVISION PRODUCTS INC.,OHIO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:OWENS-ILLINOIS, INC., A CORP. OF OHIO;REEL/FRAME:004772/0648 Effective date: 19870323 Owner name: OWENS-ILLINOIS TELEVISION PRODUCTS INC., SEAGATE, Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:OWENS-ILLINOIS, INC., A CORP. OF OHIO;REEL/FRAME:004772/0648 Effective date: 19870323 |