US3798428A - Electronic time-keeping apparatus - Google Patents

Electronic time-keeping apparatus Download PDF

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US3798428A
US3798428A US00235959A US3798428DA US3798428A US 3798428 A US3798428 A US 3798428A US 00235959 A US00235959 A US 00235959A US 3798428D A US3798428D A US 3798428DA US 3798428 A US3798428 A US 3798428A
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time
signals
output
carry
adder
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M Izawa
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Seikosha KK
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Seikosha KK
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G3/00—Producing timing pulses
    • G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G04G3/022—Circuits for deriving low frequency timing pulses from pulses of higher frequency the desired number of pulses per unit of time being obtained by adding to or substracting from a pulse train one or more pulses
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G3/00—Producing timing pulses
    • G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency
    • G04G3/025—Circuits for deriving low frequency timing pulses from pulses of higher frequency by storing time-date which are periodically investigated and modified accordingly, e.g. by using cyclic shift-registers
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G5/00—Setting, i.e. correcting or changing, the time-indication
    • G04G5/04—Setting, i.e. correcting or changing, the time-indication by setting each of the displayed values, e.g. date, hour, independently
    • G04G5/043—Setting, i.e. correcting or changing, the time-indication by setting each of the displayed values, e.g. date, hour, independently using commutating devices for selecting the value, e.g. hours, minutes, seconds, to be corrected

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  • ABSTRACT An electronic time-keeping apparatus generating SHIF T RE 6/6 TER SH/FT REGISTER .S/f/FT REGISTER SHIFT REGISTER CARRY CONT r/nwa PULSE man mm Pl/ZSE arm D/SRLAY L TIN/N6 PULSE FRO/1 T/lfl/VG PULSE GEN RESET CKT RESET sw/m/ [4 1 Mar. 19, 1974 counting pulses for a time count.
  • the counting pulses are stored in registers connected to input gates of adders that develop, from the counting pulses stored by the registers, output signals through gates corresponding to a time count.
  • the adders develop carry signals that are temporarily stored by a carry memory register and are applied back to the adders under control of a carry signal controller and through the latter for developing the time count output of the adders for higher order places in the time count.
  • the time count is displayed on visual display means as a time indication corresponding to the time count. Provision is made for initial counting errors by use of an automatic initial error preventive circuit that detects errors in the counting signals stored which may result from noise or at the start of the count and signals are developed that are applied to the adders thus varying the signal content received by the adders so that the time count output thereof is free of these initial errors.
  • Control circuitry in the form of reset circuitry is provided for resetting the time count by applying signals at will to the adders to reset the time count output and thereby the time indication of the visual display means.
  • the control circuitry includes time advancing circuitry by which the time count output is advanced by applying signals to the adders at will so that the time count indication is advanced and an advanced time or corrected time may be displayed.
  • the apparatus may be embodied in small clocks.
  • An example of a hitherto used time keeping device that keeps time electronically is a device having counters in series serving only to count a required time after the output frequency of a quartz oscillator which generates a standard frequency divided by a frequency divider.
  • the device counts the output signal of the abovementioned frequency divider thus indicating the time. For instance, when time is counted using the time unit of a second and using a 24 hour indication clock, the following counters are used: a decimal counter is provided for'use in counting the first place of a second, the first placeof a minute and the first place of an hour, and a hexadic counter is used for the tenth places of a second and a minute and a triadic counter for the tenth place of an hour.
  • circuitry is provided to reset at 24 hours minute 0 second. Time is displayed by supplying a time indicating element with a signal voltage through a decoder circuit for the output of each counter. But this requires input and output terminals to be needed in quantity and consequently, for example, when it is required to use an integrated circuit, especially a large scale integrated circuit, the number of terminals for input and output is limited. Ifa great number of terminals is needed, it could hinder the use of integrated circuits.
  • Resetting of the counters manually is generally required, and, therefore, resetting takes place only when a specific time unit or counter is off.
  • Manual switches are used to correct the time and are provided at interstages among the counters for the purpose of controlling the driving of each. Accordingly the known circuitry using semiconductors must use them in large quantities and this results in large power consumption. Thus when a small size, and therefore small capacity, power supply is required, for example in a small-sized clock which uses a dry cell, the power source has generally not been suitable.
  • An electronically-controlled time-keeping device comprises register means storing a time signal; adder means are provided to add the output time signal of the register means and the time signal and to apply the added counting time signalto the register means.
  • Carry memory register means are provided to store temporarily a carry signal generated by the adder means and to apply the carry signal to the adder means and add the carry signal to the time signal in a next place when the time signal in a next place is produced by the register means.
  • Carry controlled means generate an output signal upon receiving the counting time signal at each time of the carry operations and.
  • Clock pulse generating means generate clock signals controlling the above-mentioned respective operations, and display means display the counting time.
  • the device according to the invention is most suitable for being incorporated as [C circuitry and is very convenient for use with a secondary clock.
  • Still another object of the present invention is to provide an electronically-controlled time-keeping device capable of being reset when kept in storage in registers due to noise at the time of closing of a power supply, etc.
  • FIG. 1 is an overall functional block diagram of an electronically-controlled time-keeping device in accordance with the invention
  • FIGS. 2A and 2B are block diagrams of an embodiment of a system according to the invention.
  • FIG. 3 is a table of memory contents of registers shown in FIG. 2A.
  • the device comprises means to generate clock signals constructed as a clock pulse generating means 1.
  • This clock means consists of a standard pulse generator 1a and a timing pulse generator 1b.
  • the timing pulse generator lb is provided with a frequency divider having a 1/n dividing ratio and a decoder, and it generates timing pulses in turn at output terminals a a ...a,, of the timing pulse generator 1b every time it receives an output pulse of the standard pulse generator la.
  • Shift registers 2, 3, 4, and 5 store the time count.
  • this embodiment has a storage capacity of n bits and assume one bit storage position to be A1, A2...A B1, B2...B", C1, C ...C,,, D1, D2...D Half-adders 6,7,8 and 9 count time by adding the output of the shift registers 2,3,4 and 5 to a time signal.
  • a carry memory register 10 stores a carry signal for each place of time which is kept in the memory temporarily as a carry signal of the half-adder 9.
  • a carry controller 11 to control the carry of each place of time generates an output pulse when supplied with the carry signal prestored in the carry memory register 10 and another signal from the timing pulse generator lb while the outputs of shift registers 2,3,4 and 5 are ready to carry at each place indicative of the time.
  • An initial error preventive circuit 12 resets the erroneous contents that happen to be stored in the shift registers 2,3,4 and due to noise or other disturbances.
  • Gates 13,14... 17 connected to the shift registers are OR gates, and gates 18, l9...22 connected to the halfadders are AND gates.
  • a display 23 displays the time.
  • a time counting start switch 24 initiates the count.
  • a reset circuit 25 is composed of gate circuits which generates a reset output signal by the operation of a reset switch 26 and resets a desired counting time in the shift registers 2, 3, 4 and 5.
  • a time advance circuit 27 is used to advance a suitable time in the shift registers 2,3,4 and 5 and consists of flip-flop circuits and gates.
  • a time advance switch 28 is used to operate the time advance circuit 27.
  • a tIming pulse select switch 29 selects a suitable output pulse from the output terminals a,,a ...a,, of the timing pulse generator 1b.
  • timing pulse generator lb operates in nth notation, and so when the nth pulse produces a pulse at an output terminal a of the timing pulse generator lb, after that the (n+l)th pulse, (n+2)th pulse....produces in turn a pulse at output terminals a man.
  • time is counted to the order of a millisecond unit as a minimum, it will generate pulses to control the operation of time ranging to nine figures or places from the first place of the millisecond to the maximum time place, that is, to the tenth place of time because this embodiment takes up to a 12 hours display.
  • the shift registers 2,3,4 and 5 have a storage capacity covering from the place of the minimum time to the place of the maximum time. As explained above, this is n bits. And four bits consisting of four outputs of the shift registers 2,3,4 and 5 represent the time of each place. Now suppose all the shift registers 2,3,4 and 5 are reset at O, and the time counting start switch 24 is closed when they are under this condition.
  • N pulses are supplied from the standard pulse generator to the timing pulse generator 1b, a logical output 1 is generated at the output terminal a, of the place of the minimum time and fed to the input terminal 6a of the halfadder 6 through an OR gate 17, while the above nth pulse works as a shift pulse for shift registers 2,3,4 and 5 and shifts the storage contents in the shift registers to the right by one shift. But since the shift registers 2,3,4 and 5 are reset at O, the contents of the storage positions (An, Bn, Cn, Dn) are (0, O, O, O), and it is O which is supplied to the input terminals 6b, 7b, 8b and 9b of the half-adders 6,7,8 and 9 through the OR gates 13,14,15 and 16.
  • l, O, O, O are stored at the storage positions (A,,B,,C,, D,) of the shift registers 2,3,4 and 5.
  • (n+1 )th pulse from the standard pulse generator la is produced, and the contents of the shift registers 2,3,4 and 5 are shifted to the right by one shift.
  • the contents of the minimum time (1, O, 0, 0) are shifted at the storage positions (An,Bn,Cn,Dn) of the shift registers 2,3,4 and 5.
  • the contents (l,0,0,0) of storage positions (An,Brz,Cn,Dn) of the shift registers 2,3,4 and 5 are supplied to each input terminal 6b,7b,8b and 9b of the half-adders 6,7,8 and 9.
  • an output 1 at the terminal of the timing pulse generator lb is produced.
  • the output 1 is fed to the half-adder 6 through OR gate 7. Accordingly, I 1 addition is performed by the half-adder 6.
  • 0 is produced at the terminal 6c and stored at the storage position A of the shift register 2.
  • the carry controller 11 is operated by the outputs l, l of shift registers 2,5 and produces output 1, which is then supplied to the input terminals 6b,7b,8b and 9b of the half-adders 6,7,8 and 9 through OR gates 13,14,15 and 16. Since the abovementioned mth output 1 is being supplied to the input terminal 6a of the half-adder 6 through the OR gate 17, an output 1 is generated from the carry terminal 6a of the half-adder 6 and is then supplied to the input terminal 7a of the half-adder 7. It is thus added to the input 1 of the input terminal 7b, thereby causing the carry terminal 7d to produce an output 1. In the same way, half-adders 8,9 generate carry output I.
  • a carry output generated from the carry output terminal 9d of half-adder 9 is stored at the carry memory register 10. Since all outputs from the output terminals 6c,7c,8c and 9c of the half-adders 6,7,8 and 9 are 0, (0,0,0,0) are stored at the storage positions (A B C,,D,) of the shift registers 2,3,4 and 5.
  • the carry state of the first place of the time varies. In other words while the tenth place of the time is in decimal notation, the first place of the time is carried with 9, If the tenth place of the time becomes 1, however, the first place carry must be performed with 2. For example, suppose the contents of the first place of the time such as (l,0,0,0) are now stored at the storage positions (An,Bn,Cn,Dn) of the shift registers 2,3,4 and 5.
  • the carry contents of the first place of time is also stored in the carry memory register 10, and the contents of the tenth place of time, that is, (l,0,0,0) are stored up at the storage positions (An-l,Bn-1,Cn-l,Dn-l) of the shift registers 2,3,4 and 5. If the standard pulse generator 1a generates a pulse under thiscondition, the contents of the shift registers 2,3,4, and will be shifted to the right by one shift, and at the same time, the storage contents of the carry memory register can be taken out.
  • the carry controller l l operates with the outputs l of the storage positions An,An-l and supplies 1 to the input terminals 6b, 7b, 8b and 9b of the half-adders 6,7,8 and 9 through OR gates 13,14,15and 16.
  • the input terminal 6a of the half-adder 6 is being supplied with the output 1 of the carry memory register 10, (0,0,0,0) are generated at the output terminals 6c,7c,8c and 9c of the halfadders 6,7,8 and 9 and then stored at the storage positions (A,,B,,C,,D,) of the shift registers 2,3,4 and 5.
  • the time is reset in this way, followed by a display beginning with 0 again.
  • the initial error preventive circuit 12 is provided; and it is set in such a way as to generate a signal in case an output more than (0,l,0,l) is produced from the shift registers 3,4,5 and 6, so that the outputs of the half-adders 6,7,8 and 9 becomes 0 by its output and standard pulse.
  • the output I of the initial error preventive circuit 12 is supplied to the input 6a of the half-adder 6 through OR gate 17, and accordingly, 0 is generated at the outputs 6c,7c,8c and 9c of the half-adders 6,7,8 and 9 and (0,0,0,0) are then stored at the storage positions (A,,B,,C,,D,) in the shift registers 2,3,4 and 5.
  • any number more than (0,1 ,0,1 being kept in the storage at the shift registers 2,3,4 and 5 is reset.
  • the carry output on that occasion may be stored at the shift registers 2,3,4 and 5 if only the outputs of the half-adders become 0 after counting up to (1,1,1 ,1 and afterwards, complete normal operation is performed. For this reason, if an erroneous display at the initial operation can be ignored, the initial error preventive circuit 12 is not needed.
  • Resetting in this embodiment makes it possible to reset selectively not only the storage contents of the shift registers 2,3,4 and 5 but also the place of each time.
  • the timing pulse select switch 29, select, for instance, the output terminal a,, and close the reset switch 26, and the reset circuit 25 produces an output 1.
  • the reset circuit 2 produces O and makes the input terminal of the AND gate 9 maintain 0. Accordingly, the output becomes 0 and allows (0,0,0,0) to be stored at the positions (A,,B,,C,,D,) of the shift registers 3,4,5 and 6, thus performing reset action for the place of the minimum time.
  • any suitable terminal such as a,,a ...a,, with the select switch 29, any suitable place of time can be reset.
  • time advance function for the purpose of correcting time is explained below. From among the output terminals a,,a ...a,, of the time of the place advanced, select any suitable terminal, for example, a, with the select switch 29. And upon closing of the time advance switch 28, the output 1 is generated and stored once in a memory circuit of the time advance circuit 27 which produces an output, which is then applied to the input terminal 6b of the half-adder 6. It is added to the output of the shift register 2, thus a time advance operation is achieved. The contents stored in the memory circuit of the above-mentioned time advance circuit 27 are reset by a building-up of an adding pulse for advance.
  • FIG. 2 shows a time-keeping device with a function of 24 hours display in which the minimum counting time is lOOps.
  • Shift registers 30,31,32 and 33 store the counting time and have a storage capacity of 10 bits respectively.
  • Each place of the counting time is represented by four bits stored at each of the storage positions (A B C D (A ,B ,C D .(A ,B ,C ,D Half-adders 34, 35, 36 and 37 carry out the counting of time in adding time signals to the counting time of the shift registers 30,31,32 and 33.
  • F lip-flop circuit 38 constitutes a carry memory register and stores the carry signal of the half-adder 37 temporarily.
  • Gates consisting of OR gates 39,40...51, AND gates 52,53...68, NAND gates 69,70,73 and NOR gates 74,75, control logical operations.
  • Inverters 76,77...100 produce phase inversion between their input and output pulses.
  • OR gate 48 and AND gate 59 together compose an initial error preventive unit.
  • AND gates 56,57,58 and OR gates 44,45 compose a carry control unit in hexa notation.
  • AND gates 59,60,61 and OR gates 47,48 compose a carry control unit in decimal notation.
  • AND gates 62,63...66 and OR gates 49,50,51 compose a carry control unit in 24 notation.
  • a standard pulse generator 101 in this embodiment generates a train of pulses of lO,u.s width with a one-half duty cycle.
  • a frequency divider 102 with a setting of dividing ratio l/lO generates timing pulses to correspond with the place of each time through a decoder 103.
  • the decoder 103 is provided with output terminals, namely 103a, l03b...103j, which generate timing pulses, in turn, for each time of a place of loops, lms, l0ms, 100ms, 1 second, 10 seconds, 1 minute, 10 minutes, 1 hour and 10 hours. If the standard pulse generator 101 generates 10 pulses, the terminal 103a produces an output of pulse width 10p.s and the terminal l03b generates an output of a pulse width 10p.s when the llth timing pulse is produced.
  • pulses are generated at terminals 103e, 103d...103j in order every moment they are supplied with pulses transmitted from the standard pulse generator 101. Accordingly a pulse of 10 1.5 width in a lOOus cycle is generated from each output terminal 103a, 103b...103j.
  • the abovementioned standard pulse generator 101, the frequency divider 102 and the decoder 103 compose a clock pulse generating unit 104.
  • Flip-flop circuits 105,106 are circuits for advancing time by manual operation.
  • a decoder 107 converts the outputs of the shift registers 30,31,32, and 33 into codes to select the display elements of time of each place which compose a display 108.
  • a reset switch 109 resets the shift registers 30,31,32 and 33 and a time advance switch 110 properly advances the counting time by generating an output from a flip-flop circuit 106, and a time counting start switch 111 controls a, time counting operation.
  • a rotary switch 112 composes a timing pulse select switch for use in selecting a suitable output pulse of the decoder 103, consisting of an open contact 112a, output terminals for each place of time 1 12b, 1 12c...112k for each place of time and a segment 1121.
  • the frequency divider 102 produces an output 0 at the output terminal 103a for lOOps place of the decoder 103 because of its dividing ratio l/ 10.
  • the output then is inverted by the inverter 80, thus allowing the level of the input terminal 68b of the AND gate 68 to be inverted to 1.
  • the output of the AND gate 68 is inverted to 1 and makes the input terminal 34a of the half-adder 34 reach to 1 level through the OR gate 43 (F IG. 2A).
  • the contents of the shift registers 30,31,32 and 33 are shifted to the right by one shift when the above-mentioned tenth shift pulse is applied from the standard pulse generator 101 (FIG.
  • outputs 0 at the output terminals 35c,36c and 370 of half-adders 35,36 and 37 are fed back to shift registers 31,32, and 33 and stored as 0 at the storage positions B ,C and D and accordingly, (1,0,0,0) is stored at respective storage positions (A B C D
  • the storage contents (1,0,0,0) of shift registers 30,31,32 and 33 are shifted in turn to the right by one shift when given the 1 1th and 12th shift pulses from the standard pulse generator 101 (FIG. 2B) and further shifted to the memory positions (A B C D of the shift registers 30,31,32 and 33 when given the 19th shift pulse.
  • a carry output 1 generated from the output terminal 34d is supplied to the input terminal 35a of the half-adder 35, and an output l is then generated from the output terminal 350 and stored at the storage position B.
  • output 0 is generated from the output terminals 36c,37c of halfadders 36,37, and 0, 0 are stored at storage positons C D
  • (O,l,0,0) is stored at the storage positions (A ,B,,C ,D,). In this way counting time is performed in order.
  • the aforementioned pulse generated from the standrad pulse generator 101 produces output 0 at the output terminal 103g for the first place of minute in the decoder 103 through the frequency divider 102 and then selects another electrode of a display element for the first place of minute in the display 108 through inverters 87,97.
  • a voltage is applied between the aforesaid one electrode and another electrode of the display element, lighting up 2.
  • the standard pulse generator 101 After lOus elapse, the standard pulse generator 101 generates a pulse, shifting the contents of the shift registers 30,31,32 and 33 which causes a resultant output to be generated for the th place of a minute, and exactly in the same manner as mentioned above, the display element electrode for the 10th place of a minute in the display 108 is selected.
  • another electrode of the aforesaid display element is selected by a pulse from the output terminal l03h of the decoder 103, thus the 10th place of a minute or O in this example is displayed.
  • the lighting positions of the display elements are to be changed and respective elements are lighted in a lOOus cycle. Though lighting is intermittent, it looks as if it were to keep lighting continuously because the lighting cycle is l00us or within the scope of after image to the eyes.
  • a carry output 1 is generated from the terminal 34d and applied to the terminal 350 of the half-adder 35.
  • the terminal 35b is being supplied with 1, the terminal 350 of the half-adder 35 is 0, which is then stored at the storage position B, of the shift register 31 through the AND gate 53.
  • the carry output l at the carry terminal 35d is supplied to the input terminal 36a of the half-adder 36.
  • outputs at the output terminals 36c,37c of half-adders 36,37 become 0, and O is stored in the storage positions CD of shift registers 32, 33 through AND gates 54,55.
  • the storage positions (A,,B,,C,,D,) will be (0,0,0,0).
  • the carry output 1 of the output terminal 37d of the halfadder 37 is stored in the flip-flop 38.
  • the pulse generated from the standard pulse generator 101 is also supplied to the flip-flop 38 (FIG. 2A), and the carry output 1 of a previously stored place of time is taken out from the terminal 38,.
  • One of the outputs thus taken out is supplied to the input terminal 34, I
  • the contents of the shift registers 30,31,32 and 33 are shifted to the right by each shift, and at the same time addition is made by the half-adders 34,35,36 and 37 performing counting time relating to the first place, 10th place and 100th place of millisecond, and the first place of second entirely in the same way as mentioned above.
  • the rest terminal of the AND gate 58 is supplied 1 from the decoder 103 (FIG.2B) through the NOR gate 74 (FIG. 2A.).
  • the AND gate 58 then produces the output 1.
  • the output 1 is transmitted through OR gates 45,46 and the one is supplied to the input terminal 34,, of the half-adder 34 through the OR gate 43.
  • the other is supplied to the input terminals 34,,35,,,36, and 37,, through the OR gates 39,40,41 and 43. Accordingly, O is generated from the output terminal 34 and stored at the storage position A, of the shift register 30.
  • a carry output 1 is produced and supplied to the input terminal 35,, of the half-adder 35.
  • 0 is generated at this output terminal 35 and a carry output 1 at carry terminal 35, In this way 0 is stored at the storage position 13, of the shift register 31. And so 0 is stored at the storage positions C,D and carry output 1 of the half-adder 37 is stored in the flip-flop 38. The first place and the th place of minute can be counted exactly in the same manner.
  • the output pulse of the standard pulse generator 101 takes out the carry signal of a minute stored in the flip-flop 38 and supplies it to the input terminal 66,, of the AND gate 66. And 0 for the first place of an hour which produces at the output terminal 103] of the decoder 103 is inverted to 1 through the inverter 78 (FIG. 2A).
  • the l is supplied to the terminal 66 of the AND gate 66. Since full inputs of the AND gate 66 maintain l in this way, 1 is produced at the output terminal 66,. This is supplied, one through OR gates 49,46
  • the reset mechanism of this invention has features of selective opera tion. As an example, the reset action for the place of lOOus will be explained. First, the contact 112, for selecting a timing pulse is connected to the contact point 112,, of IOOus. Then, the contact 109 of the reset switch 109 is connected to the contact point 109, the input terminal of the NAND gate 70 ismaintained 0. Unless the carry output of ps is supplied, the output of the NAND gate 69 is kept 1, that is, the input terminals 52,53,54, and 55,, of AND gates 52,53,54 and 55 are maintained as 1. However, when after the place output 0 of 100ps of the decoder 103 is inverted to l through the inverter 80, the l is supplied to the input of the NAND gate 69, the output is maintained 0, and
  • the contact 109 of the reset switch 109 is connected to the contact point 109,, and the counting time start switch 111 set at the start side; the time after being corrected can be counted.
  • the selection of the time of a unit place is as above described, but by providing a proper select switch to-select suitable terminals connected tothe contact points ll2,,,ll2,....l12,,. of the rotary switch 112, simultaneously, the time of a plurality of places can be automatically reset.
  • the contact points 112,,1 12 ,112, and 112, of the rotary switch 112 are selected at the same time. Accordingly, every time the output is generated from respective output terminals 103 ,l03,,,103,, and 103; of the decoder 103, the outputs of AND gates 52,53,54 and 55 will become 0 as explained in the above-mentioned lOOus reset operation. Therefore, the storage contents of each time of the shift registers 30,31,32 and 33 are reset to 0. To reset all times, therefore, one must connect the output terminals of all times to a contact and exactly in the same manner as described above, all storage contents of registers 30,31,32 and 33 will be 0, and all places of time can be reset.
  • the time of l00p.s place at the storage positions (A, ,B ,C, ,D is shifted to the right by one shift and then supplied to the half-adders 34,35,36 and 37 through OR gates 39,40,41 and 42. It is added to 1 supplied at the input terminal 34,, of the half-adder 34, and the added product is then stored at the shift register 30. Since it is also shifted by the output pulse from the standard pulse generator 101, its output or time of lOOus place is supplied to the input terminal 34,, of the halfadder 34 and counted by addition.
  • the flip-flop 106 is reset by the output of the flip-flop inverted by the output pulse of the AND gate 67 or a building up of a lOOps time signal pulse.
  • counting time outputs are supplied to the carry control means, the initial error preventive means and the display means from the output terminals of the shift registers 30,31,32 and 33, but they are not always limited to these.
  • outputs taken from a suitable position between the half-adders 34,35,316 and 37 and the inputs of the shift registers 31,32,32 and 33 are supplied to the above-said means.
  • the device according to the invention can also be used as a stop watch.
  • An electronic time-keeping apparatus comprising, means generating pulsedcounting signals for a time count, register means storing the counting signals, adder means developing from the counting signals of said register means a time count output and developing carry signals corresponding to higher order places in the time count, carry signal memory register means temporarily storing said carry signals, carry signal controlled means controlling application of the carry signals to said adder means, display means displaying an indication of the time corresponding to said time count, and time-advancing means developing signals under manual control applied to said adder means for varying the stored contents of said register means received by said adder means to advance the time count output of said adder means to correspond to a desired time in advance of the time indicated at said display means.
  • An electronic time-keeping apparatus comprising, means generating pulsed counting signals for a time count, register means storing the counting signals, adder means developing from the counting signals of said register means a time count output and developing carry signals corresponding to higher order places in the time count, carry signal memory register means temporarily storing said carry signals, carry signal controlled means to receive the temporarily stored carry signals and apply them to said adder means to develop output signals corresponding to said time count output and representative of said higher order places of said time count, clock pulse generating means generating timing clock pulses applied to said carry signal controlled means controlling application of the carry signals to said adder means, display means displaying an indication of the time corresponding to said time count, and error preventive means automatically detecting initial errors in the stored counting signal content of said register means and developing signals applied to said adder means for varying in response to the detection of said errors the stored contents of said register means received by said adder means to correctly effect said time count.
  • An electronic time-keeping apparatus comprising, means generating pulsed counting signals for a time count, register means storing the counting signals, adder means developing from the counting signals of said register means a time count output and developing carry signals corresponding to higher order places in the time count, carry signal memory register means temporarily storing said carry signals, carry signal controlled means to receive the temporarily stored carry signals and apply them to said adder means to develop output signals corresponding to said-time count output and representative of said higher order places of said time count, clock pulse generating means generating timing clock pulses applied to said carry signal controlled means controlling application of the carry signals to said adder means, display means displaying an indication of the time corresponding to said time count, and start switch means for controlling the start of a time count, and error preventive means automatically detecting errors in the counting signal content of said register means developed at the start of a time count and correcting the time count output of said adder means to correctly effect said indication of time.
  • An electronic time-keeping apparatus comprising, means generating pulsed counting signals for a time count, register means storing the counting signals, adder means developing from the counting signals of said register means a time count output and developing carry signals corresponding to higher order places in the time count, carry signal memory register means temporarily storing said carry signals, carry signal controlled means connected to receive the temporarily stored carry signals and apply them to said adder means to develop output signals representative of said higher order places of said time count, time-advancing means for developing signals applied to said adder means varying the stored contents of said register means received by said adder means to advance the time count to correspond to an advanced time, error preventive means detecting errors in the stored counting signal content of said register means and developing signals applied to said adder means varying the stored contents of said register means received by said adder means upon detection of said error to correctly make said time count, clock pulse generating means generating clock pulses applied to said carry signal controlled means controlling application of the carry signals to said adder means, and display means receptive of the time count output and displaying an indication of the time corresponding to
  • An electronic time-keeping apparatus comprising: pulse generating means for developing a plurality of timing pulses and clock pulses; register means for storing and reading out a plurality of words of time data in synchronization with the clock pulses, adder means responsive to a given timing pulse of the timing pulses for incrementing the time data applied thereto from said register means and for applying the incremented time data to said register means; carry signal memory register means for temporarily storing a carry output from said adder means and coactive with said adder means to effect an increment in the time data of a higher order word of the time data in synchronization with the clock pulses, carry signal controlled means successively receptive of the words of time data, said timing pulses and the carry output of each word stored in said carry signal memory register, for controlling the coaction of said adder means and said carry signal memory register means to increment the time data in a higher order word of time data; and display means for displaying the words of time data.
  • An electronic time-keeping apparatus including time-advancing means developing signals under manual control applied to said adder means for varying the stored time data of said register means received by said adder means to advance the time data output of said adder means to correspond to a desired time in advance of the time indicated at said display means 7.
  • An electronic time-keeping apparatus including error preventive means automatically detecting initial erroneous time data stored in said register means and developing signals applied to said adder means for varying in response to the detection of said erroneous time data the stored contents of said register means received by said adder means to correctly effect the time data.
  • An electronic time-keeping apparatus including reset means to reset at will the time data of a selected word in said register means to a desired time data, thereby to indicate a reset time indication on said display means.
  • An electronic time-keeping apparatus including start switch means for controlling the start of a time count, and error preventive means automatically detecting erroneous time data stored in said register means developed at the start of a time count and correcting the time data output of said adder means to correctly effect said indication of time.
  • An electronic time-keeping apparatus comprising: pulse generating means for developing a plurality of timing pulses and clock pulses; register means for storing and reading out a plurality of words of time data in synchronization with the clock pulses adder means responsive to a given timing pulse of the timing pulses for incrementing the time data applied thereto from said register means and for applying the incremented time data to said register means; carry signal memory register means temporarily storing a carry output from said adder means and coactive with said adder means to effect an increment in the time data of a higher order word of the time data in synchronization with the clock pulses; carry signal controlled means successively receptive of the words of the time data, and timing pulses and the carry output of each word of the time data stored in said carry signal memory register means for controlling the coaction of said adder means and said carry signal memory register means to increment the time data in a higher order word of time data; time advancing means for developing signals applied to said adders to vary the stored contents of said register means received by said adders to advance the time data to

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
US00235959A 1971-03-20 1972-03-20 Electronic time-keeping apparatus Expired - Lifetime US3798428A (en)

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JP (1) JPS5327630B1 (enrdf_load_stackoverflow)
FR (1) FR2130450B1 (enrdf_load_stackoverflow)
GB (1) GB1354231A (enrdf_load_stackoverflow)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3916612A (en) * 1972-10-02 1975-11-04 Citizen Watch Co Ltd Electronic timepiece
US3940595A (en) * 1974-05-30 1976-02-24 American Medical Electronics Corporation Electronic thermometer decoder and display system
US3988886A (en) * 1973-08-14 1976-11-02 Casio Computer Co., Ltd. Time setting device for an electronic watch
US4025774A (en) * 1975-06-16 1977-05-24 American Hospital Supply Corporation Timing apparatus including electronic calculator circuits
US4078375A (en) * 1975-12-26 1978-03-14 Casio Computer Co., Ltd. Electronic timepiece
US4092819A (en) * 1975-07-02 1978-06-06 Tokyo Shibaura Electric Co., Ltd. Electronic timepiece circuit
US4132060A (en) * 1976-06-24 1979-01-02 Casio Computer Co., Ltd. Electronic timepiece
US4146779A (en) * 1977-02-28 1979-03-27 Osborne-Hoffman, Inc. Display controller for time recorders and time actuators
US4150535A (en) * 1974-10-31 1979-04-24 Citizen Watch Company Limited Electronic timepiece
US4242728A (en) * 1978-02-27 1980-12-30 The Bendix Corporation Input/output electronic for microprocessor-based engine control system
US4250370A (en) * 1975-10-31 1981-02-10 Tokyo Shibaura Electric Co., Ltd. Digital control for a cooking time and power of an electric cooking device
US4253175A (en) * 1978-03-16 1981-02-24 Tokyo Shibaura Denki Kabushiki Kaisha Time data processing circuit for electronic timepiece
US4256954A (en) * 1977-04-01 1981-03-17 Texas Instruments Incorporated Fast binary coded decimal incrementing circuit
US4267587A (en) * 1978-02-17 1981-05-12 Casio Computer Co., Ltd. Electronic timepiece circuit
US4449196A (en) * 1979-04-27 1984-05-15 Pritchard Eric K Data processing system for multi-precision arithmetic
US20150253737A1 (en) * 2014-03-06 2015-09-10 Em Microelectronic-Marin Sa Time base including an oscillator, a frequency divider circuit and clocking pulse inhibition circuit

Citations (3)

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Publication number Priority date Publication date Assignee Title
US3656060A (en) * 1971-01-15 1972-04-11 Ibm Time interval measuring and accumulating device
US3656122A (en) * 1969-12-11 1972-04-11 Bell Telephone Labor Inc TIME-SHARED SHIFT REGISTER COUNTER WITH COUNT MODIFIED EACH Nth RECIRCULATION
US3664117A (en) * 1970-06-05 1972-05-23 Gen Electric Non-time indicating number correction circuit

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US3521036A (en) * 1966-11-01 1970-07-21 Stromberg Carlson Corp Binary coded decimal counter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3656122A (en) * 1969-12-11 1972-04-11 Bell Telephone Labor Inc TIME-SHARED SHIFT REGISTER COUNTER WITH COUNT MODIFIED EACH Nth RECIRCULATION
US3664117A (en) * 1970-06-05 1972-05-23 Gen Electric Non-time indicating number correction circuit
US3656060A (en) * 1971-01-15 1972-04-11 Ibm Time interval measuring and accumulating device

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3916612A (en) * 1972-10-02 1975-11-04 Citizen Watch Co Ltd Electronic timepiece
US3988886A (en) * 1973-08-14 1976-11-02 Casio Computer Co., Ltd. Time setting device for an electronic watch
US3940595A (en) * 1974-05-30 1976-02-24 American Medical Electronics Corporation Electronic thermometer decoder and display system
US4236241A (en) * 1974-10-31 1980-11-25 Citizen Watch Company Limited Electronic timepiece
US4302828A (en) * 1974-10-31 1981-11-24 Citizen Watch Company Limited Electronic timepiece
US4150535A (en) * 1974-10-31 1979-04-24 Citizen Watch Company Limited Electronic timepiece
US4025774A (en) * 1975-06-16 1977-05-24 American Hospital Supply Corporation Timing apparatus including electronic calculator circuits
US4092819A (en) * 1975-07-02 1978-06-06 Tokyo Shibaura Electric Co., Ltd. Electronic timepiece circuit
US4250370A (en) * 1975-10-31 1981-02-10 Tokyo Shibaura Electric Co., Ltd. Digital control for a cooking time and power of an electric cooking device
US4078375A (en) * 1975-12-26 1978-03-14 Casio Computer Co., Ltd. Electronic timepiece
US4132060A (en) * 1976-06-24 1979-01-02 Casio Computer Co., Ltd. Electronic timepiece
US4146779A (en) * 1977-02-28 1979-03-27 Osborne-Hoffman, Inc. Display controller for time recorders and time actuators
US4256954A (en) * 1977-04-01 1981-03-17 Texas Instruments Incorporated Fast binary coded decimal incrementing circuit
US4267587A (en) * 1978-02-17 1981-05-12 Casio Computer Co., Ltd. Electronic timepiece circuit
US4242728A (en) * 1978-02-27 1980-12-30 The Bendix Corporation Input/output electronic for microprocessor-based engine control system
US4253175A (en) * 1978-03-16 1981-02-24 Tokyo Shibaura Denki Kabushiki Kaisha Time data processing circuit for electronic timepiece
US4449196A (en) * 1979-04-27 1984-05-15 Pritchard Eric K Data processing system for multi-precision arithmetic
US20150253737A1 (en) * 2014-03-06 2015-09-10 Em Microelectronic-Marin Sa Time base including an oscillator, a frequency divider circuit and clocking pulse inhibition circuit
US9671759B2 (en) * 2014-03-06 2017-06-06 Em Microelectronic-Marin Sa Time base including an oscillator, a frequency divider circuit and clocking pulse inhibition circuit

Also Published As

Publication number Publication date
JPS5327630B1 (enrdf_load_stackoverflow) 1978-08-09
DE2213460A1 (de) 1972-12-21
FR2130450A1 (enrdf_load_stackoverflow) 1972-11-03
DE2213460B2 (de) 1976-06-16
FR2130450B1 (enrdf_load_stackoverflow) 1976-10-29
GB1354231A (en) 1974-06-05

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