US3786625A - Arrangement for correcting of seconds indication of a timepiece - Google Patents

Arrangement for correcting of seconds indication of a timepiece Download PDF

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Publication number
US3786625A
US3786625A US00312328A US3786625DA US3786625A US 3786625 A US3786625 A US 3786625A US 00312328 A US00312328 A US 00312328A US 3786625D A US3786625D A US 3786625DA US 3786625 A US3786625 A US 3786625A
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Prior art keywords
flop
output
storage means
reset
stage
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US00312328A
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English (en)
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P Sauthier
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Soc Suisse Pour Ind Horlogere Management Services Sa ch
SUISSE POUR IND HORLOGERE MANA
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SUISSE POUR IND HORLOGERE MANA
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G9/00—Visual time or date indication means
    • G04G9/0005—Transmission of control signals
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G5/00—Setting, i.e. correcting or changing, the time-indication
    • G04G5/02—Setting, i.e. correcting or changing, the time-indication by temporarily changing the number of pulses per unit time, e.g. quick-feed method

Definitions

  • a correction circuit for a timepiece is driven by digital pulses to advance the timepiece display by one second [52] US. Cl. 58/23 R, 58/85.5 in response to each pulse.
  • a first push button switch is [5 1] Int. Cl G04c 3/00 provided for eliminating one pulse, and a second push 1 Field of Search 53/23 50 button switch is provided for inserting an additional 328/44, 48; 307/222, 225 R pulse into the sequence of pulses applied to the display, to thereby provide correction of the time dis- [56] References Cited played by the timepiece.
  • the present invention concerns timepieces of the type in which a high frequency oscillating circuit stabilized for example by a quartz crystal, has its output transformed to a low' frequency through a chain of dividers and such low frequency is utilized to excite a display unit.
  • the display unit may be in the form of a stepping motor used to drive a conventional timepiece display utilizing second, minute or hour hands, but could equally well drive a digital display formed by solid state elements or liquid crystals, or an analogue type of display likewise using solid state or liquid crystal elements.
  • timepieces of this nature A problem arising in timepieces of this nature is that of setting time exactly in accordance with some external time indication and one of the principal features in favor of such timepieces is the fact that they normally will be very stable and exact so that the tendency to vary from the external standard will be at aminimum over a long period of time. Normally therefore, the only resetting necessary is that of the seconds indicator since the display unit of such a timepiece is driven through a succession of pulses. It is obvious in the case, for example, of a stepping motor that in order to advance the seconds indication, it will be necessary to introduce supplemental pulses, thereby effecting additional steps of the motor. Similarily, if one wishes to retard the display it will be necessary to suppress one or more pulses driving the display unit.
  • timing'Thus for example, it is necessary that one be able to actuate the corrector at any given instant and thereby control precisely the number of seconds which one either adds to, or subtracts from, the visible display.
  • timepieces which should be capable of being made in wrist watch sizes, it is obvious that any arrangement provided must be simple and reliable and must keep the number of additional circuits and parts down to a minimum.
  • An object of the present invention is to provide correction circuit means normally producing a sequence of pulses of predetermined frequency for driving a timepiece display, said correction circuit means including first means for inserting an additional pulse into said sequence of pulses, and second means for eliminating a pulse from said sequence of pulses.
  • a further object of the present invention is to provide a correction circuit as described in the preceding paragraph wherein said first means comprises a manually actuated switch, each actuation of which will add one pulse to said sequence, regardless of when said actuation takes place, and said second means comprises a second manually actuated switch, each actuation of which will eliminate one pulse from said sequence regardless of when said actuation takes place.
  • a timepiece in which a time standard provides signals at a predetermined frequency, said frequency being reduced through a sequence of bistable devices to a desired lower frequency and the lower frequency signals serve to control a display arrangement, and wherein means are provided to set the display exactly through the addition or subtraction of one signal at a time said means including a Reset output terminal on at least one of the bistable devices in the sequence, at least one bistable storage device arranged to be set manually and to be reset from said Reset output terminal and a display control toggle provided with two set inputs one of which receives signals from the lowest frequency one of said sequence of bistable devices and the other of which receives signals from the Set output terminal of the bistable storage device so that coincidence is prevented between signals to the motor control toggle which are manually originated and signals to the motor control toggle originating from the sequence of bistable devices.
  • a second bistable storage device is arranged to be set manually and reset from a Reset output terminal on the display control toggle, an output terminal of said second bistable storage device being arranged to control the conductivity of at least one transistor whereby each setting of said second bistable storage device eliminates a single signal from the sequence of display control signals.
  • FIG. 1 is a block diagram of the logic used for the correctors
  • FIG. 2 is a timing diagram of the operation when it is desired to add pulses to the display.
  • FIG. 3 is a timing diagram of the operation when it is desired to subtract pulses from the display.
  • Such counter stage is chosen in a manner such that the duration of the output pulses fromflip-flop CM will be sufficient to actuate the display.
  • the 8th stage in the binary counter has been chosen thereby to give a duration of about 8 MS to the output pulses from CM.
  • a further set input to flip-flop CM is labelled S 2 and is connected to the reset output Q of a bistable storage device 16.
  • the storage device 16 is set by means of a push-button P l and is reset from the reset output Q of the counter stage 14. As shall be subsequently explained, depression of push-button P 1 will add one pulse to the output of motor control flip-flop CM.
  • the output Q of flip-flop CM is connected to the base of a transistor T 2 and the collector of a transistor T l.
  • Transistor T 2 serves to actuate the display device M which may, for example, be a standard display device actuated by a stepping motor, or one of the solid or liquid crystal display devices.
  • Transistor T 1 has its base connected to the output terminal Q of a bistable storage device 17.
  • the set input of storage device 17 is actuated by a push-button P 2 and the reset input is actuated by the reset output of the motor control flip-flop CM.
  • depression of push-button P 2 suppresses one pulse from the output Q of flip-flop CM.
  • the output of counter stage 14 is shown as a series of pulses and the output of counter stage is shown as a further series of pulses having twice the duration of the pulses from stage 14.
  • the output from flip-flop CM is controlled as to its duration by the reset input R and as to its timing and frequency by the set inputs S l and S 2.
  • S 2 will have no effect since the input thereto will remain at 1 so long as storage device 16 is not set by push-button P 1.
  • the inputs S l and S 2 to flip-flop CM are in the nature of a capacitive coupled OR gate whereby an input in the form of a positive-going pulse applied to either one, will set the flip-flop. However, setting is possible only by means of a rising pulse. A steady state high level input has no effect on the flip-flop.
  • a pulse arrives at input S 1 from counter stage 15 each second to set flipflop CM and the flip-flop is subsequently reset at a time determined by the requirements of the display unit or, as illustrated in FIG. 1, when the 8th counter stage applies a pulse to the reset input R.
  • ti shows the instant at which a correction will be effective if P 1 has been depressed in the one-half second which precedes t
  • the instant t never coincides with the normal driving pulses.
  • the user may have to wait as much as one-half a second before pushing the correction button P l a second time.
  • This difficulty may be overcome, at least in part, by the expedient of choosing the reset output from a counte stage higher up in the chain, as for instance Q 13 or Q 12 (not shown). This would reduce the waiting time necessary between the two corrections to one-fourth or one-eighth of a second.
  • push-button P 2 controls bistable storage device 17. It will be evident that actuation of push-button P 2 sets storage device 17, so that Q 1. Accordingly NPN transistor T 1 becomes conductive and point B is at 0. Since point B will be at 0 between two output pulses from flip-flop CM, this would have no effect. At the moment however when the gem input signal S l arrives at flip-flop CM, the output Q changes to l and Q changes to However, point B remains at 0, since the change of Q from 1 to 0 does not change the state of storage device 17. Next following the delay, as determined by timing of the input pulse R to the flip-flop, the flip-flop CM returns to its reset state whereby QCM changes to 1.
  • the positive-going signal Qcu resets storage device 17 (Q 0, Q l).
  • Transistor Tl accordingly cuts off until such time as push-button P 2 has been again depressed.
  • one pulse and only one pulse has been eliminated.
  • the pushbutton P 2 will not be effective if operated at the same moment as the normal pulse being fed to the display unit. Since the duration of such a pulse however represents only about 6 percent of the duty cycle, this is thought to be of small importance.
  • the same difficulty may arise in respect of the possible rebounding tendency of push-button P 2 as was the case of pushbutton P l and the same solution may be used to alleviate the difficulty.
  • a display control flip-flop having set and reset outputs and a set input responsive to one of said counter stages for producing a sequence of signals at said set output;
  • bistable storage means having set and reset inputs and an output
  • second bistable storage means having set and reset inputs and an output
  • a correction circuit as claimed in claim 6 wherein the means connecting the output of said bistable storage means of said circuit means includes a second transistor responsive to the output of said bistable storage means for disabling said first transistor.
  • a timepiece wherein a time standard provides signals at a predetermined frequency and said frequency is reduced by a sequence of bistable counter stages, each having a reset output, to control a display means, the improvement comprising:
  • a display control flip-flop having a set input connected to one of said counter stages for producing a sequence of pulses at a set output
  • bistable storage means having set and reset inputs, and a set output connected to the set input of said display control flip-flop
  • a correction circuit as claimed in claim 8 wherein said display control flip-flop has a reset input, and means connecting said reset input to a counter stage of a frequency greater than said next to lowest frequency stage whereby the stage selected determines the duration of each pulse in said sequence.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
US00312328A 1971-12-16 1972-12-05 Arrangement for correcting of seconds indication of a timepiece Expired - Lifetime US3786625A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB5847071A GB1385890A (en) 1971-12-16 1971-12-16 Arrangement for correcting of seconds indication of a timepiece

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US3786625A true US3786625A (en) 1974-01-22

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US (1) US3786625A (enrdf_load_stackoverflow)
CH (2) CH578208B5 (enrdf_load_stackoverflow)
GB (1) GB1385890A (enrdf_load_stackoverflow)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3916612A (en) * 1972-10-02 1975-11-04 Citizen Watch Co Ltd Electronic timepiece
US3931703A (en) * 1973-02-27 1976-01-13 Ebauches S.A. Correcting device for an electronic watch
US3988597A (en) * 1975-01-31 1976-10-26 Tokyo Shibaura Electric Co., Ltd. Time correction circuits for electronic timepieces
US4150536A (en) * 1976-01-28 1979-04-24 Citizen Watch Company Limited Electronic timepiece
US4176515A (en) * 1976-10-09 1979-12-04 Quarz-Zeit Ag Electronic clock, particularly a quartz clock

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105116712A (zh) * 2015-08-03 2015-12-02 深圳市芯海科技有限公司 一种内置晶振自动校准方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3530663A (en) * 1967-09-01 1970-09-29 Patek Philippe Sa Automatic and continuous time adjusting device for a clock
US3643419A (en) * 1969-07-14 1972-02-22 California Inst Of Techn Apparatus for fine adjustment of signal frequency
US3668859A (en) * 1969-07-03 1972-06-13 Vogel Paul Time setting device for an electronic clock
US3672155A (en) * 1970-05-06 1972-06-27 Hamilton Watch Co Solid state watch

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3530663A (en) * 1967-09-01 1970-09-29 Patek Philippe Sa Automatic and continuous time adjusting device for a clock
US3668859A (en) * 1969-07-03 1972-06-13 Vogel Paul Time setting device for an electronic clock
US3643419A (en) * 1969-07-14 1972-02-22 California Inst Of Techn Apparatus for fine adjustment of signal frequency
US3672155A (en) * 1970-05-06 1972-06-27 Hamilton Watch Co Solid state watch

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3916612A (en) * 1972-10-02 1975-11-04 Citizen Watch Co Ltd Electronic timepiece
US3931703A (en) * 1973-02-27 1976-01-13 Ebauches S.A. Correcting device for an electronic watch
US3988597A (en) * 1975-01-31 1976-10-26 Tokyo Shibaura Electric Co., Ltd. Time correction circuits for electronic timepieces
US4150536A (en) * 1976-01-28 1979-04-24 Citizen Watch Company Limited Electronic timepiece
US4176515A (en) * 1976-10-09 1979-12-04 Quarz-Zeit Ag Electronic clock, particularly a quartz clock

Also Published As

Publication number Publication date
CH1827472A4 (enrdf_load_stackoverflow) 1976-02-27
CH578208B5 (enrdf_load_stackoverflow) 1976-07-30
GB1385890A (en) 1975-03-05

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