US3756011A

US3756011A - Time correcting device for electronic timepieces

Info

Publication number: US3756011A
Application number: US00287200A
Authority: US
Inventors: I Nishimura; A Shimoi
Original assignee: Suwa Seikosha KK
Current assignee: Suwa Seikosha KK
Priority date: 1971-09-13
Filing date: 1972-09-07
Publication date: 1973-09-04
Anticipated expiration: 1990-09-04
Also published as: HK51577A; DE2244942B2; DE2244942A1; GB1401775A

Abstract

An electronic timepiece is provided with a plurality of display elements for the digital display of time driven by time keeping circuitry. A time correcting device coupled to said time keeping circuitry is provided for independently correcting each of said display elements other than the second display elements, said time-correcting device including means for correcting the second display elements by returning same to zero. In another embodiment each of the digits are separately correctable, a carry suppression gate being interposed between the time-keeping circuitry for certain of the display elements actuated by a correction mode signal to permit independent correction of at least minutes and hours. Time correction may be either by the one-step method or the quick feed method.

Description

United States Patent 1 1 Nishimura et al.

[ TIME CORRECTING DEVICE FOR ELECTRONIC TIMEPIECES [75] Inventors: lzuhiko Nishimura; Akio Shimoi,

both of Nagano-ken, Suwa, Japan [73] Assignee: Kabushiki Kaisha Suwa Seikosha,

Tokyo, Japan [22] Filed: Sept. 7, 1972 [21] Appl. No.: 287,200

[30] Foreign Application Priority Data 14 1 Sept. 4, 1973 Primary Examiner-Richard B. Wilkinson, Assistant Examiner-Edith C. Simmons Jackmon Attorney-Alex Friedman et al.

[57] ABSTRACT An electronic timepiece is provided with a plurality of display elements for the digital display of time driven by time keeping circuitry. A time correcting device coupled to said time keeping circuitry is provided for independently correcting each of said display elements other than the second display elements, said timecorrecting device including means for correcting the second display elements by returning same to zero. In another embodiment each of the digits are separately correctable, a carry suppression gate being interposed between the time-keeping circuitry for certain of the display elements actuated by a correction mode signal to permit independent correction of at least minutes and hours. Time correction may be either by the onestep method or the quick feed method.

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TIME CORRECTING DEVICE FOR ELECTRONIC TIMEPIECES BACKGROUND OF THE INVENTION This invention relates to electronic timepieces having digital display systems, wherein the time indicated by said digital display system is manually correctable. Such digital display systems are generally provided with separate displays for at least 1-minute, -minute and lhour digits and require means for independently correcting each of said digits and for the simultaneous return-to-zero correction of all of the digits. Electronic timepieces of this type are generally formed from solid state devices and do not include mechanical or movable members in their functional components. Such watches are driven solely by electronic circuitry. Substantial effort has been devoted to improving such digital display electronic timepieces, with most of the effort being devoted to accuracy, energy source, life and the like. However, little effort has been devoted to the ease of use of the timepiece and the accuracy and quickness with which setting and correction can be achieved.

SUMMARY OF THE INVENTION Generally speaking, in accordance with the invention, an electronic timepiece in accordance with the invention may be provided having oscillator circuit -means for producing a-high frequency time standard signal and frequency divider circuit means consisting of a plurality of stages for sequentially dividing said high frequency time standard signal to low frequency time keeping signals, each of said low frequency time keeping signals being produced at a selected one of said Each of said selected stages of said frequency divider circuit means is coupled to a separate display element through driving circuit means. Time correcting means is provided including correction switch means for selectively and individually applying a time correction signal to each of the divider stages associated with the display elements for displaying minutes and hours, and reset switch means for separately and selectively applying a reset signal to the divider stages associated with said second display elements for selectively returning said second display elements to The time correcting means may include carry suppression gate means between certain of the divider stages producing said time keeping signals for selectively'blocking transmission between said stages in response to a correction mode signal for isolating the respective display elements during time correction. Means may be provided for providing said correction signal as an intermediate frequency signal from-an intermediate one of said divider stages to permit rapid correction. Selected switch means may be provided for the selective application of either said intermediate frequency signal or a DC signal as said correction signal.

Each of the divider stages producing said time keeping signals may be provided with a corresponding auxiliary divider circuit, means including setting switch means for selectively applying a setting signal to said auxiliary divider circuits for permitting the setting of each of said auxiliary divider circuits at a selected value by the manual manipulation of said setting switch means, and gate means coupled to said divider stage and its associated auxiliary divider circuit for detecting the respective states thereof and connected to receive the signal from the prior divider stage, said intermediate frequency signal and a correction mode signal. The gate means is adapted, in response to said correction mode signal, to apply said intermediate frequency signal to said divider stage until said divider stage and the associated auxiliary divider circuit are in the same state, and to thereafter prevent the application of said intennediate frequency signal and the signal from the prior stage to said divider stage. Said gate means is also adapted to permit said divider stage to return to normal operation upon opening of said switch means applying said intermediate frequency signal and the removal of said correction mode signal.

Accordingly, it is an object of this invention to provide means for improving the operability of the time correction devices for electronic timepieces.

A further object of the invention is to provide a time correcting device for an electronic watch which permits accurate quick-feed correction, as well as permitting periodic automatic correction.

Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification and drawings.

The invention accordingly comprises the features of construction, combinations of elements, and arrangement of parts which will be exemplified in the constructions hereinafter set forth, and the scope of the invention will be indicated in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS For a fuller understanding of the invention, reference is had to the following description taken in connection with the accompanying drawings, in which:

FIG. 1 is a block diagram of an embodiment of an electronic timepiece incorporating a conventional push button time correcting arrangement;

FIG. 2 is a detailed circuit diagram of the dividing circuit, decoder circuit, driver circuit and display element of one stage of the electronic watch of FIG. 1;

FIG. 3 is a top plan view of a display element in accordance with the invention formed from a seven bar array;

FIGS. 4, 5 and 6 are each block diagrams of embodiments of an electronic watch in accordance with the invention;

FIG. 7 is a block diagram of a circuit for preventing over count during time correction;

FIG. 8 is a block diagram of an electronic timepiece incorporating the circuit for preventing over count of FIG. 7;

FIG. 9 is a sectional view of a portion of a switch member in accordance with the invention; and

FIG. 10 is a partially perspective partially sectioned view of further components of the switch member of FIG. 10.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. I, an electronic timepiece including a time correcting circuit based on the one-step method utilizing conventional push-button switches is depicted. In said electronic watch, a high frequency time standard signal is generated by a high precision standard oscillator (OSC) which may be formed from a crystal vibrator, a tuning fork vibrator or the like. Said high frequency time standard signalis converted into a pulse signal of one second frequency by divider circuit DIV formed from a plurality of flip-flop stages.

, The l-second signal thus produced is applied to a decionce every 10 minutes. The 10 minute signal is applied to a 1/6 divider circuit 4 which produces a pulse signal once every hour. The 1 hour signal is applied to a onetwelfth divider circuit 5 which produces a pulse signal once every 12 hours. The respective 1 second, second, 1 minute, 10 minute and 1 hour signals enter a decoder, driver and display circuit module 7-0. Said module includes display elements 7-1, 7-2, 7-3, 7-4 and 7-5, each representative of a single digit of digital time indication, and each being driven by one of the respective 1 second, 10 second, 1 minute, 10 minute and 1 hour signals. Said display elements are preferably of the seven bar array type and may be formed from luminous diodes, liquid crystal materials or the like. The respective display elements are driven by decoder and driver circuits in accordance with the state of the

respective divider circuits

1, 2, 3, 4 and 5.

One column of the decoder, driver and display circuitry associated with one digit, specifically with the one second digit, is illustrated in FIGS. 2 and 3. The seven bar display, which permits digital display of numbers from 0 to 9 in accordance with input signals applied thereto is depicted in FIG. 3. The numeral 2 is displayed in the drawing. The decoder circuit selects the segments to which voltage is applied to render them visible in response to the state of the associated divider stage, the voltage being applied to the selected segments by the driver circuit. The output of each divider stage is a binary coded signal, which is decoded by said decoder circuit. In FIG. 2, gate circuit 7-a represents a decoder circuit, switch circuit 7-b represents the driver circuit, while block 7-c represents the display element consisting of segments L,,, L, L,., L L,, L, and L,, as further illustrated in FIG. 3. Block l-! of FIG. 2 represents the decimal decoder stage which receives the I second signal and produces the 10 second signal at the last 0 output thereof. Said decimal divider stage consists of four binary circuits FF,, FF}, FF and FF,. The binary coded output from said decimal divider circuit enters the decoder circuit 7-a. Each of the binary circuits FF FF,, FF,,, and FF, is a delay flip-flop having a logical expression Q,, =D,, ,-1=D,, where n represents the operating condition of the circuit before the input pulse (time signal P enters, and n+1 represents the operating condition after the input pulse enters. Accordingly, each binary flip-flop circuit is constructed by connecting the Q and D terminals together. Gate circuit G, transforms each output of the binary circuits FF,, FF,, FF,, and FF, into 0, O, 0, 0 (0 in decimal numeration) when each output is l, 0, 1, 0 (10 in decimal numeration) as a resetting operation, thereby also producing the 10 second signal. 7

R is a reset signal which resets dividing circuit l-l. S is a correcting signal which sets the display element at a desired time indication. G, is an exclusive type gate for receiving correcting signal S and time signal P,,,.

At normal operating conditions, correcting signal S is set at a low (0) and input signal P is applied to the divider circuit without modification. When the time is to be corrected, the number of input pulses increases by the number of pulses of the correcting signal S, each additional pulse indexing the divider circuit to permit time correction. Each of the divider stages receiving the 10 second, 1 minute, 10 minute and 1 hour signals can similarly be corrected.

Referring again to FIG. 1, the time correction portion of the electronic timepiece depicted is designated as S As used herein, the term correct refers to both the return-to-zero correction of all of the columns (1 second, 10 second, 1 minute, 10 minutes and 1 hour) and the separate and individual setting of each column to a desired time indication. R is the reset signal for resetting all of the columns simultaneously, and further resets the divider circuit DIV when push-button switch R, is closed, thereby performing return-to-zero correction.

To set each display element to a desired time, the push-button switch 8,, S S S or 8,, coupling the correcting signal S to the respective one of

divider circuits

1, 2, 3, 4 or 5 is closed once for each pulse to be added to the respective divider circuit. Thus, the user operates each of the switches S S S S and S, until all of the display elements display the desired time. This time correction approach is called the one-step" method and is sufficient if only small corrections are required. However, when large time corrections are required, the large number of times each of switches S 8,, S S and 8, have to be switched poses a substantial disadvantage. Further, the correction technique tends to lead to errors in correction.

An electronic timepiece in accordance with the invention utilizing the one step method of time correction is depicted in FIG. 4. As in the case of the circuit of FIG. 1, a precision standard oscillator OSC produces a high frequency time standard signal which is applied to a dividing circuit DIV, said dividing circuit producing a signal every second. Divider stages 11, 12, l3, l4 and 15 are respectively decimal, one-sixth, decimal, one-sixth and one-twelfth divider circuit for respectively driving 1 second, 10 second, 1 minute, 10 minute and 1 hour digits of a digital display. The decoder, driver and display circuits 7-00 corresponds in construction to the corresponding elements depicted in FIGS. 2 and 3. The time correction device of the circuit of FIG. 4 includes a reset signal R which is simultaneously applied to each of the divider stages ll, l2, 13, 14 and 15 so as to retum-to-zero the corresponding display segments representative of the 1 second, 10 second, 1 minute, 10 minute and 1 hour digits of the digital display. A reset signal SEC-ADJ is applied through OR gate G to divider stages 1 l and 12 associated with the 1 second and 10 second display elements. This signal serves to reset only the second indication, without regard to the settings of the minute and hour indications. Note that reset signal R is also applied to divider stages 11 and 12 through OR gate G A setting signal O- S is applied through manually operable switches S,,, S,,, S, to divider

stages

13, 14 and 15 respectively. By manually opening and closing selected ones of said switches, the selected digits of the minute and hour indication may be corrected one number at a time in accordance with the one-step method.

To set the watch of FIG. 4, for example, to 12:00:00, first the hour digit is manually corrected to read 12 by means of switch 8, the 10 minute and 1 minute digits are respectively set to zero by manually opening and closing switches 8,, and 8,, once for each number that each digit is to be advanced, and then, when the actual time becomes 12:00:00, reset signal SED-ADJ is applied to divider stages 11 and 12 to reset said divider stages to zero. Referring now to FIG. 5, an electronic timepiece incorporating the quick-feed method of time correction is depicted. As in the case of the circuit of FIG. I, a precision standard oscillator OSC provides a high frequency time standard signal which is applied to a dividing circuit DIV and which produces a signal every second. Divider stages 21, 22, 23, 24 and 25 are respectively decimal, one-sixth, decimal, one-sixth and one-twelfth divider circuits for respectively driving 1 second, second, 1 minute, 10 minute and 1 hour digits of a digital display. The decoder, divider and display circuits 7-000 corresponds in construction to the corresponding elements depicted in FIGS. 2 and 3. The time correction device of the circuit of FIG. 4 includes the switch structure S, and carry suppression gates G G and G Gate 6,, is interposed between divider stages 22 and 23, betweenthe 10 second divider stage and the 1 minute stage. Gate G is interposed between divider stages 23 and 24, between the 1 minute divider stage and the 10 minute divider stage. Gate G is interposed between divider stages 24 and 25, between the 10 minute and 1 hour stages. During normal operating conditions, said carry suppression gate merely transmits the signals from the previous stage therethrough. During time correction, they serve as carry suppression gates, preventing the transmission of signals between the adjacent divider stages.

The correction device includes reset switches R R R,, R, and R, connected respectively to divider stages 21, 22, 23, and 25 for the selective application of a reset signal to each of said divider stages. These reset switches perform return-to-zero correction. Time correction switches S S, and S, are connected respectively to divider stages 23, 24 and 25 on one side thereof, and are connected in common on the other side thereof. Said common connection is connected through a mode switch to either of fixed terminals S, and 8,. Fixed terminal S is connected to a stage of divider DIV and receives an intermediate frequency signal therefrom. Fixed terminal S, receives a DC signal S. Switches 5,, S and S, permit the selection of the 1 minute, 10 minute and 1 hour digits to be corrected. The mode switch permits the selection of either the quick-feed method when the switch is connected to terminal S or the one-step method when the switch is connected to terminal S. When the common switch is connected to terminal 8,, the pulses of the intermediate frequency signal correct the selected divider stage. The opening and closing of the switch against terminal S, applies individual pulses to the selected stage for fine setting.

The foregoing arrangement is particularly useful where large settings are required, as where the watch is to be reset from 1:00:00 to 12:00:00. In such a case, the time would be advanced by the quick-feed method through closing switch 8,, and setting the mode switch to terminal S, until the desired time is nearly reached. At this time, the mode switch is switched to terminal 8, and the l hour digit is precisely set to the desired value. If only the quick-feed method is provided, it is possible that the desired time will be passed due to the speed with which the changes are made. A correction mode signal K is applied to each of the carry suppression gates G G and G During time correction, said carry suppression signal is applied to said gates, thereby preventing the carrying over of an undesired digit from the prior stage. The carry suppression gates make the setting of the 1 minute, 10 minute, 1 hour digits independent of each other and of the setting of the 1 second digit. This approach avoids unnecessary time correction.

Still a further embodiment of the time correction device in accordance with the invention is depicted in FIG. 6. In the circuit of FIG. 6, an oscillator-divider chain represented by oscillator OSC, divider DIV and divider stages 51, 52, 53, 54 and 55 is provided, corresponding in structure and function to the oscillatordivider chain of FIG. 1. Similarly, the decoder, driver and display circuits 7-0000, having separate display segments 7-51, 7-52, 7-53, 7-54 and 7-55 corresponding in structure and operation to the decoder, driver and display circuits of FIG. l. The time correcting arrangement of the circuit of FIG. 6 includes a reset switch R, which serves to simultaneously reset each of divider stages 51, 52, 53, 54 and 55 by application of reset signal R when said reset switch is turned on. In this manner, retum-to-zero correction is achieved. Switch 8,, is provided for second correction and serves to reset only the I second and 10

second stages

51 and 52 without regard to the setting of the 1 minute, 10 minute and 1 hour stages 43, 44, and 45. Switch S, applies a reset signal SEC-ADJ to divider

stages

51 and 52 through OR gate G the reset signal R from switch R, also being passed through said OR gate. It is noted that retum-to-zero operations are performed since setnsthcqssirssttimsis msrssasily swamnli after such a retum-to-zero operation. Switches S S and S are respectively coupled to the 1 minute, 10 minute and 1 hour divider stages 53, 54 and 55 for selectively applying a correction signal S of an intermediate frequency derived from a stage of divider circuit DIV. The time on the 1 minute, 10 minute and 1 hour display elements can be separately corrected by quickfeed when the switch associated with the display elements to be corrected is turned on.

However, one difficulty with the circuit of FIG. 6 is the danger that the time indication at a particular digit may be advanced beyond the desired time if a hand operated quick-feed device is utilized. For example, the time may be set to 12:20:00 when the desired time is 12:00:00. This possible defect is eliminated in the embodiment of FIGS. 7 and 8 wherein the intermediate frequency signal stops automatically at the moment that the desired time is displayed. Referring first to FIG. 8, the electronic watch depicted is provided with an oscillator-divider chain including oscillator OSC, divider DIV and divider stages 811, 82, 83, 84 and 85 corresponding to the oscillator-divider chain of FIG. I in function, but differing in structure as will more particularly be described below. The decoder, driver and display circuit 7-00000 incorporating display elements 7-81, 7-82, 7-83, 7-74 and 7-85 correspond in structure and operation to the decoder, driver and display circuits of FIG. ll. The electronic circuit of FIG. 8 includes a time correction device K. Referring now to FIG. 7,

'the structure of the in I second divider stage is depicted. A, B, C and D represent a binary flip-flop chain representative of the main decimal divider stage. An auxiliary decimal divider consisting of flip-flop chain a,

' b, c and d is also provided, structured to correspond to the main divider stage chain. When the I second digit is to be corrected separately, the desired figure is set in the auxiliary divider circuit a, b, c and d by a one-step process by the pulsing of correcting signal 8,. Thus, if a reading of seconds is desired, the output of flipflops a, b, c and d must be respectively set to O,1,0,I (Sin decimal numeration). A correcting signal S, is then applied to the main dividing chain A, B, C, D through gate G,,. When each output of flip-flops A, B, C and D corresponds to the corresponding outputs of flip-flops a, b, c and d as previously set, the respective outputs of gates G,,G,, G and G, become high and the output of AND gate G becomes high. A correction mode signal S, representative of the performance of the time correction function is applied to a gate G, so that when signal S, is high, the output of gate G, is high and the output of gate G is low regardless of the other input signal to said gate, said other input signal being the output of gate G,,. The other input to gate G, is from the output of AND gate G and is high when the states of the auxiliary and main divider circuits are identical.

To render divider stage 81 operational again, the correcting signal S is first turned off, and next, the correcting mode signal S, is turned off to show the end of the correction operation. Due to the presence of the gate G when the correcting mode signal S, is turned off, gate G, is rendered conductive and the main divider stage A, B, C and D is rendered responsive to the input signal P from the previous stage. The decoder, driver and display element circuits depicted in FIG. 2 would be connected to the main divider stage A, B, C, D.

Referring again to F 16.8, switches 8b,. 5b,, S113, So. and S couple the correcting signal S selectively to the corresponding auxiliary divider circuits of divider stages 81, 82, 83, 84 and 85 for setting said auxiliary divider circuit. Correction mode signal S, is made high during the correction process. Switches S S S8,, Sc and S are quick-feed correction switches for selectively applying the intermediate frequency correction signal S from divider circuit DIV and the corresponding divider stages 81, 82, 83, 8d and 35. The provision of the circuit of FIGS. 7 and 8 avoids over counting due to the presetting provision of the auxiliary divider circuits. Signals S 8,, and S of FIG. 8 correspond to signals 8,, 8,, and S, of FIG. 7.

The circuit of FIGS. 7 and 8 permit automatic time correction by means of using a correct-time broadcasting signal as the correction signal 8,, applied to the auxiliary divider circuit. Furthermore, the circuit of FIGS. 7 and 8 can be used in a stop watch to measure lap time since the output of the main divider stage always changes coincidently with the output of the auxiliary divider if a clock pulse is used as the 8,, input and only switch 8,, is turned on.

A time correction switching arrangement for application to the time correction devices in accordance with the invention is depicted in FIGS. 9 and 10. In said arrangement, a winding crown 117 is provided with a rotary switching mechanism depicted in FIG. 9, and a push-button type switch mechanism as depicted in FIG. 10. Winding crown 117 is provided with a squared portion 1 16 which is received within a square window 110 in the rotary switch element. A movable contact 124 is displaced relative to circumferentially spaced fixed

contacts

111, 112, 113, 114 and 115 by rotating winding crown 117 in the direction of arrow 123.

Fixed contact

111, 112, 113, 114 and 115 may correspond, for example, to switches S1,,,Sb,,Sb,,Sb,, and Sb, of FIG. 8. When crown 117 is longitudinally displaced in the direction of arrow 122, after a desired column is selected by rotating the crown, end member 121 engages movable contact against fixed contact 1 19 to close an electrical circuit. Movable contact 120 and fixed contact 119 are mounted on insulating base 118 and would have leads connected thereto. The switch defined by

contacts

119 and 120 may be connected to divider DIV to provide the quick-feed correction signal S to the switches represented by fixed

contacts

111, 112, 113, 114 and 115.

The arrangement of FIGS. 9 and it) permits the selective correction of each display element through the use of only one winding crown. At one rotary position of the winding crown all of the display elements may be reset to zero, while at other rotary positions of the winding crown, separate display elements may be separately corrected, with the respective display elements being quickly corrected in a step wise manner. Two separate crowns may be utilized if desired.

The arrangement in accordance with the invention reduces erroneous time correction and simplifies the performance of the time correction functions.

It will thus be seen that the objects set forth above, and those made apparent from the preceding descprition, are efficiently attained and, since certain changes may be made in the above constructions without departing from the spirit and scope of the invention, it is intended that all matter contained in the above description or shown in the accompnaying drawings shall be interpreted as illustrative and not in a limiting sense.

It is also to be understood that the following claims are intended to cover all of the generic and specific features of the invention herein described, and all statements of the scope of the invention which, as a matter of language, might be said to fall therebetween.

What is claimed is:

1. An electronic timepiece comprising an oscillator circuit means for producing a high frequency time standard signal; multi-stage frequency divider circuit means for sequentially dividing said high frequency time standard signal to produce a low frequency time keeping signal at each of a selected group of divider stages; display means including a plurality of display elements for the digital display of time; means for driving each of said display elements in response to the time deeping signal of one of said selected divider stages; and time correcting means including correction switch means coupled to each of the divider stages producing the 1 minute, l0 minute and l hour time keeping signal for selectively and individually applying a correction signal to each of said divider stages producing said 1 minute, 10 minute and 1 hour time keeping signals to correct the associated display elements, and reset switch means for separately and selectively applying a reset signal to the divider stages producing the I second and 10 second time keeping signals for returning to zero both of the display elements associated with said divider stages for producing said 1 second and 10 second time keeping signals.

2. An electronic timepiece as recited in claim 1, including means for interconnecting said correction switch means and an intermediate divider stage producing an intermediate frequency signal, said intermediate frequency signal serving as said correction signal.

3. An electronic timepiece comprising oscillator circuit means for producing a high frequency time standard signal; multistage frequency divider circuit means for dividing said high frequency time standard signal and producing a time keeping signal at each of a plurality of said divider stages; display means for the digital display of time including a plurality of display elements; means for driving each of said display elements in response to a time keeping signal produced by one of said divider stages; and time correcting means including a carry suppression gate between selected ones of the divider stages producing said time keeping signals; means for selectively applying a correction mode signal to said carry suppression gates, said carry suppression gates being adapted to permit the passage of signals between adjacent stages of said frequency divider circuit means in the absence of said correction mode signal but to prevent the transmission of signals between adjacent stages in the presence of said correction mode signal, and correction switch means for selectively applying a correction signal to each of a plurality of said divider stages producing said time keeping signals for selectively setting each of the display elements associated with the divider stages to which said switch means is connected, whereby a plurality of said display elements may be individually and independently corrected.

4. An electronic timepiece as recited in claim 3, wherein said switch means includes means for separately applying said correction signal to each of the divider stages producing the 1 second, 10 second, 1 minute, 10 minute and 1 hour time keeping signals.

5. An electronic timepiece as recited in claim 4, including means for interconnecting said switch means and an intermediate divider stage for applying an intermediate freuency signal to said switch means for selective application to each of the divider stages to which said switch means is connected.

6. An electronic timepiece as recited in claim 5, wherein said interconnecting means includes a source of a DC correction signal, and a selection switch for selectively connecting said switch means to one of said intermediate divider stage for application of said intermediate frequency signal, an open circuit, to said source of DC. correction signal whereby each of said divider stages connected to said switch means may be selectively corrected by either the one-time method or the quick-feed method.

7. An electronic timepiece comprising oscillator circuit means for producing a high frequency time standard signal; multistage frequency divider means for dividing said high frequency time standard signal to produce a low frequency time keeping signal at each of said plurality of said divider stages; display means for the digital display of time including a display element for each digit of time to be displayed; means driving each of said display elements in response to a time ill keeping signal of one of said divider stages; and time correction means including switch means for selectively and individually applying a correction signal to each of a plurality of said divider stages for producing said time keeping signals, and means interconnecting said switch means and an intermediate divider stage producing an intermediate frequency signal, said intermediate frequency signal defining said correction signal.

8. An electronic timepiece as recited in claim 7, wherein said interconnecting means includes a source of a DC. correction signal, and a selection switch for selectively connecting said switch means to one of said intermediate divider stages for application of said intermediate frequency signal, an open circuit, or said source of said D.C. correction signal whereby each of said divider stages connected to said switch means may be selectively corrected by either the one-time method or the quick-feed method.

9. An electronic timepiece as recited in claim 7, wherein at least one of the divider stages producing said time keeping signals includes a corresponding auxiliary divider circuit, said time correcting means includ ing setting switch means for selectively applying a setting signal to each of said auxiliary divider circuits for permitting the setting of each of said auxiliary divider circuits to a selected value by the manual opening and closing of said setting switch means, and a gate means coupled to each divider stage having an auxiliary divider circuit and to said auxiliary divider circuit for detecting the respective states thereof and connected to receive the signal from the prior divider stage of said frequency divider circuit means, said intermediate frequency correction signal and a correction mode signal, said gate means being adapted to apply said intermediate frequency signal to said divider stage in response to said correction mode signal until said divider stage and associated auxiliary divider circuit are in the same state, and to thereafter prevent the application of said intermediate frequency signal and the signal from the prior stage to said divider stage, said gate means being further adapted to permit said divider stage to return to normal operation upon removal of said intermediate frequency signal and correction mode signal.

10. An electronic timepiece as recited in claim 9, wherein said gate means includes comparison gate means for producing an output signal when each divider stage and its associated auxiliary divider circuit are in the same state, a first AND gate means receiving the output signal of said comparison gate means and said correction mode signal; and a transmission gate means for transmitting the signal from the prior stage or said intermediate frequency correction signal to said divider stage in the absence of an output signal from said first AND gate means.

1 t i i

Claims

1. An electronic timepiece comprising an oscillator circuit means for producing a high frequency time standard signal; multistage frequency divider circuit means for sequentially dividing said high frequency time standard signal to produce a low frequency time keeping signal at each of a selected group of divider stages; display means including a plurality of display elements for the digital display of time; means for driving each of said display elements in response to the time deeping signal of one of said selected divider stages; and time correcting means including correction switch means coupled to each of the divider stages producing the 1 minute, 10 minute and 1 hour time keeping signal for selectively and individually applying a correction signal to each of said divider stages producing said 1 minute, 10 minute and 1 hour time keeping signals to correct the associated display elements, and reset switch means for separately and selectively applying a reset signal to the divider stages producing the 1 second and 10 second time keeping signals for returning to zero both of the display elements associated with said divider stages for producing said 1 second and 10 second time keeping signals.

6. An electronic timepiece as recited in claim 5, wherein said interconnecting means includes a source of a D.C. correction signal, and a selection switch for selectively connecting said switch means to one of said intermediate divider stage for application of said intermediate frequency signal, an open circuit, to said source of D.C. correction signal whereby each of said divider stages connected to said switch means may be selectively corrected by either the one-time method or the quick-feed method.

7. An electronic timepiece comprising oscillator circuit means for producing a high frequency time standard signal; multistage frequency divider means for dividing said high frequency time standard signal to produce a low frequency time keeping signal at each of said plurality of said divider stages; display means for the digital display of time including a display element for each digit of time to be displayed; means driving each of said display elements in response to a time keeping signal of one of said divider stages; and time correction means including switch means for selectively and individually applying a correction signal to each of a plurality of said divider stages for producing said time keeping signals, and means interconnecting said switch means and an intermediate divider stage producing an intermediate frequency signal, said intermediate frequency signal defining said correction signal.

8. An electronic timepiece as recited in claim 7, wherein said interconnecting means includes a source of a D.C. correction signal, and a selection switch for selectively connecting said switch means to one of said intermediate divider stages for application of said intermediate frequency signal, an open circuit, or said source of said D.C. correction signal whereby each of said divider stages connected to said switch means may be selectively corrected by either the one-time method or the quick-feed method.

9. An electronic timepiece as recited in claim 7, wherein at least one of the divider stages producing said time keeping signals includes a corresponding auxiliary divider circuit, said time correcting means including setting switch means for selectively applying a setting signal to each of said auxiliary divider circuits for permitting the setting of each of said auxiliary divider circuits to a selected value by the manual opening and closing of said setting switch means, and a gate mEans coupled to each divider stage having an auxiliary divider circuit and to said auxiliary divider circuit for detecting the respective states thereof and connected to receive the signal from the prior divider stage of said frequency divider circuit means, said intermediate frequency correction signal and a correction mode signal, said gate means being adapted to apply said intermediate frequency signal to said divider stage in response to said correction mode signal until said divider stage and associated auxiliary divider circuit are in the same state, and to thereafter prevent the application of said intermediate frequency signal and the signal from the prior stage to said divider stage, said gate means being further adapted to permit said divider stage to return to normal operation upon removal of said intermediate frequency signal and correction mode signal.