US3778629A

US3778629A - Jamming detection

Info

Publication number: US3778629A
Application number: US00229373A
Authority: US
Inventors: R Terryn
Original assignee: International Standard Electric Corp
Current assignee: Alcatel Lucent NV
Priority date: 1971-03-17
Filing date: 1972-02-25
Publication date: 1973-12-11
Anticipated expiration: 1990-12-11
Also published as: AU3936472A; CA958095A; CH561449A5; NL7103555A; AU464961B2; BE780668A; DE2212541A1

Abstract

THIS SUPERVISORY DETECTION ARRANGEMENT FOR A DOCUMENT HANDLING SYSTEM PARTICULARLY PROVIDES FOR AN ALARM CONDITION WHENEVER DOCUMENTS ARE LOST FROM THE CONVEYING PATH AND WHEN THEY ARE JAMMED UP OR OTHERWISE ABNORMALLY DELAYED. A DOCUMENT PASSING IN FRONT OF A FIRST PHOTOCELL A THE ENTRANCE OF A DOCUMENT CONVEYOR PATH STARTS A SHIFT REGISTER SHIFTING A 1STATE THROUGH IT AT A MAIN CLOCK PULSE RATE. A NUMBER OF REGISTERING BISTABLE DEVICES CORRESPONDING WITH A SAME NUMBER OF PHOTOCELLS, PLACED ALONG THE CONVEYOR PATH ARE SET BY AN INTERMEDIATE CLOCK PULSE PHASE-SHIFTED WITH RESPECT TO THE MAIN CLOCK PULSE WHEN A CORRESPONDING SHIFT REGISTER STAGE IS SET. EACH REGISTERING BISTABLE DEVICE IS RESET BY A DOCUMENT PASSING IN FRONT OF A CORRESPONDING PHOTOCELL AND ITS CONDITION IS TESTED WHEN THE SAME OR ONE OF THE FOLLOWING SHIFT REGISTER BISTABLE DEVICES IS IN THE 1-STATE AND AT THE OCCURENCE OF A SECOND INTERMEDIATE CLOCK PULSE. ALARM CONDITIONS ARE THUS DETECTED WHEN THE REGISTERING BISTABLE HAS NOT BEEN RESET.

D R A W I N G

Description

United States Patent 1 91 Terryn Dec. 11, 1973 1 JAMMING DETECTION [75] inventor: Raymond M. F. Terryn,

Borgerhout, Belgium [73] Assignee: International Standard Electric Corporation, New York, N.Y.

[22] Filed: Feb. 25, 1972 [21] Appl. No.: 229,373

[30] Foreign Application l riority Data Primary ExaminerJames W. Lawrence Assistant ExaminerT. N. Grigsby Attorney-C; Cornell Remsen, Jr. et al.

[5 7] ABSTRACT This supervisory detection arrangement for a document handling system particularly provides for an alarm condition whenever documents are lost from the conveying path and when they are jammed up or otherwise abnormally delayed. A document passing in front of a first photocell at the entrance of a document conveyor path starts a shift register shifting a l-state through it at a main clock pulse rate. A number of registering bistable devices corresponding with a same number of photocells, placed along the conveyor path are set by an intermediate clock pulse phase-shifted with respect to the main clock pulse when a corresponding shift register stage is set. Each registering bistable device is reset by a document passing in front of a corresponding photocell and its condition is tested when the same or one of the following shift register bistabledevices is in the l-state and at the occurrence of a second intermediate clock pulse. Alarm conditions are thus detected when the registering bistable has not been reset.

6 Claims, 10 Drawing Figures PATENIED DEC 1 1 I913 sum 55; 5

AHH

JAMMING DETECTION The present invention relates to a document handling system including: I

a conveyor means to convey documents along a conveyor path; bistate registering means which are normally in a first of two conditions; signal generator means to generate at least one first signal and at least one second signal, said second signal following said first signal by a predetermined time interval; detection means generating a third signal upon the passage of each of said documents at a predetermined position of said conveyor path and being adapted to reset said registering means in said first condition depending upon the occurrence of said third signal; setting means cooperating with said signal generator means to set said registering means in the second of said two conditions depending on the occurrence of said first signal; and control means cooperating with said signal generator means to control the condition of said registering means depending on the occurrence of said second signal and to generate an output signal upon said registering means being found in a predetermined one of its said first and second condition. Such a document handling system is already known from Belgian Pat. No. 614,430 (G. DELPLACE et al. 2-1).

ln this known document handling system there are provided a number of bistable devices (registering means) the O-inputs of which are each connected to the output of a corresponding AND-gate. One of the inputs of each of these AND-gates is connected to the output of a corresponding photocell (detection means). These photocells are arranged in predetermined positions along the conveyor path and each generate an output signal when illuminated by an associated lamp. This means that no output signal is produced when a document is situated in front of a photocell. The other inputs of the AND-gates are connected in common to the output of a trigger pulse generator so that each of the bistable devices is put in its -state when the output of the corresponding AND-gate is activated (third signal) i.e., by a trigger pulse allowed through the gate when the corresponding photocell is illuminated. On the contrary, if a document is situated in front of any one of the photocells the corresponding bistable device cannot be brought in its O-state. The l-inputs of all bistable devices are connected in common to the output of a clock pulse generator delivering clock pulses (first signals). Controlling means control the O-state of the bistable devices in principle by means of clock pulses hereinafter called control pulses (second signals) each produced just before the end of a period of the first clock pulses. An alarm signal indicating a possibility of jamming is produced when at least one of the bistable devices is still in its l-state at the moment a control pulse is generated thus indicating that a document has remaine'd an abnormal long time in front of the corresponding photocell or that the distance between two consecutive documents has become so small that during the corresponding illumination of the photocell no trigger pulse is generated.

The system as described in the above mentioned Belgian patent has the disadvantage that it is'not able to detect documents which for instance have been ejected out of the conveyor path. Indeed, in this case no alarm signal will be produced since the bistable devices, corresponding to the photocells following the place of ejection, will be put in their O-state after these photocells have been illuminated. For the same reason erroneously formed stacks of documents on the conveyor path between two consecutive photocell positions will not be detected.

It is therefore an object of the present invention to provide a document handling system of the above type which eliminates the above mentioned drawbacks and hence, which is adapted to detect ejected and erroneously stacked documents.

The present document handling system is particularly characterized in that said signal generator means are constituted by a shift register provided with a plurality of stages and in which, for each document handled, means are provided to place the first of said stages in a predetermined condition driving means being provided for said shift register to shift said predetermined condition through said stages that said first and second signals are generated when said predetermined condition is registered in a second and in a third stage of said shift register respectively and that said detection means generate said third signal upon the arrival of said document at said predetermined position along said conveyor path.

The present document handling system is able to detect that a document has been ejected out of the conveyor path or that a stack of documents has been formed on the conveyor path at the left of the second position. Indeed when this happens the bistable registering means previously set in its second condition will remain in this condition due to the fact that the resetting means do not generate a resetting third signal since no document arrives in front of the mentioned second position.

In a preferred embodiment, as a result of a document passing in front of the first photocell at the entrance of the conveyor, the first stage of a shift register will be put in the l-state by a clock pulse of period T. This 1- state is carried through-the shift register at the clock pulse rate. Once the shift register has been started, the movement of the l-state along the shift register is independent of the real movement of the documents along its path. Thus, the shift register pattern represents the theoretical propagation of the documents along the conveyor path apart from the delay and jamming which may occur. Registering means constituted by a number of bistable devices are associated with a same number of photocells, the latter being placed along the conveyor at certain intervals. These bistable devices are set when a corresponding shift register bistable device is in the l-state by an intermediate clock pulse phase shifted with respect to the main clock pulse. They are reset by a document passing in front of the corresponding photocell and are controlled by the same or one of the following bistable devices of the shift register together with a second intermediate clock pulse. When the registering bistable device has not been able to be reset by the position determining photocell, thus remaining in its operative state, the output of this bistable device together with the controlling signal and this second intermediate pulse pass through an AND-gate and thus detect a jamming, an abnormal delay or a missing document and this may eventually act upon a machine stopping device.

The above mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of embodiments taken in conjunction with the accompanying drawings in which FIG. I is a schematic view of a shift register and associated circuitry forming part of a document handling system according to the present invention;

FIG. 2 represents pulses appearing during the operation of this shift register;

FIGS. 3, 4 and 5 represent relative positions of clock pulses and of documents processed by a document handling system according to the invention;

FIG. 6 is a schematic view of a first embodiment of a document handling system according to the invention;

FIG. 7 represents pulses appearing during the operation of the system of FIG. 6;

FIG. 8 is a schematic view of a second embodiment of a document handling system according to the invention;

FIGS. 9 and 10 show other pulses appearing during the operation of the system of FIG. 8.

Principally referring to FIG. 1, PHI represents a photocell, and its associated circuitry, in front of which a light source (not shown) is mounted at the entrance of a document conveyor (not shown) in order to detect the introduction of documents in said conveyor by a feeding mechanism (not shown). The output signal PHI of the photocell PHl is activated when darkened and de-activated when illuminated by the associated light source. The output of this photocell is connected via amplifier A to the l-input of a monostable device MS having a time constant t and which is adapted to be triggered into its unstable condition by the leading edge of the output signal of the photocell. The l-output of this monostable device MS is connected to the l-input of a buffer bistable device FFB, the l-output of which is connected to the l-input of the first bistable device FFI of a shift-register, constituted by n interconnected bistable devices FFl to FFn. The O-output of the bufier bistable device FFB is connected to the 0 -input of the bistable device FFl, the l-output of which is connected on the one hand to the O-input of the buffer bistable device FFB and on the other hand to the l-input of the second bistable device FF2 of the shift register. The land O-outputs of each of the bistable devices FFZ to FFn-l of the shift register are further connected to the land O-inputs of the immediately following bistable devices FF3 to FFn respectively. The common inputs of all the bistable devices FFl to FFn are connected to the output CP of a clock pulse generator (not shown).

It should be noted that the above bistable devices are normally in their O-condition with their 0- and loutputs activated and de-activated respectively. These bistable devices are of the so called master-slave type well known in the art e.g., the Texas Instruments type SN 7472. Each of these bistable devices can only change its stage when a clock pulse is applied to its common input, this change of state occurring more particularly during the trailing edge of this clock pulse. For example, when the bistable device FFl is in its 0- state, it can only be brought in its l-state when simultaneously its l-input is activated and a clock pulse is applied to its common input.

The operation of the shift register and associated circuitry represented on FIG. I is described hereinafter, reference being made to FIG. 2 wherein the abscis represents time. When a document entering the conveyor intercepts the light beam emitted by the light source mounted in front of the photocell PHI, the latter produces an output signal represented by PI-I'l. After amplification in the amplifier A, the resulting signal output is applied to the l-input of the monostable device MS, which is triggered to its l-condition for a period t. The resultant output 21 is applied to the l-input of the bistable device FFB which is thus set to its l-condition, hereby producing pulse FFBl at its I-output. Upon the occurrence of the clock pulse CP'l of a series of clock pulses CP' having a period T, the first bistable device FFl of the shift register is set to its l-state due to which the buffer bistable device FFB is reset to its O-state. By the immediately following clock pulse CP2 the second bistable device FF2 of the shift register is set to its 1- condition and the first one FF] is reset to its 0- condition when the bistable device FFB is still in the 0- condition i.e., when no new document has entered the conveyor. At the arrival of a following document the bistable device FFB is again set to its l-condition and upon the occurrence of the third clock pulse CP3 the first bistable device FFl of the shift register is set, so that the buffer bistable device FFB is reset. Simultaneously, the shift register information is shifted one stage further. If however a new document had produced the setting of the bistable device FFB before the occurrence of the clock pulse CP'Z, the first bistable device FFl is set by this clock pulse CP'2.

From the above it follows that every time a document is introduced in the conveyor a l-state is registered in the first bistable device FFl of the shift register, this 1- state being shifted through the register at the clock pulse rate. The pulses FF'I, FF'2 FF'n on FIG. 2 represent the shift of such a l-state through the stages of the shift register.

Before describing a document handling system according to the invention, the following should be noted: when L represents the total length of the conveyor, T the period of the clock pulses, v the velocity of travel of the documents, n the number of flip-flops, which may be said to cover the total conveyor length and since the shift of a l-state through the shift register represents the theoretical movement of the corresponding document along the conveyor path, one may write vnT L. The conveyor length covered by one flip-flop is hence L/n vT so that L/n can be expressed in equivalent time or alternatively T can be expressed in equivalent length, the factor of equivalence being v. In the same way, if D is the distance between documents and tD the time needed by a document to travel over this distance, one has D t v and t D/v. The time t will be called equivalent document distance and is represented by D Likewise, the equivalent time T, l v is the distance between documents D.

Principally referring to FIGS. 3 to 5, the influence on the shift register configuration of the equivalent distance D, between successive documents as compared with the period T of the clock pulses CP' is considered.

FIG. 3 represents the relative positions of 15 clock pulses CP'l to CP'15 and of seven documents I, 2 7. Each of the arrows associating a clock pulse and a document indicates the clock pulse by which the first bistable device FFl of the shift register is set to its 1- condition i.e., by which the presence of a document is registered in the shift register. The equivalent document distance D, is supposed to be larger than 2T so that as follows from FIG. 3 the configuration of the information stored in the last to first bistable device of the shift register is 100101010100101 after the presence of all the seven documents has been registered in this shift register. From this configuration it follows that at regular intervals, depending on the relative value of D,,-2T and T, there appears a 1001 configuration, whilst otherwise the configuration 101 is prevailing. It should be noted that in FIG. 3 the first document 1 is considered to be in phase with the clock pulse CP'l, but if this clock pulse is lagging or leading with respect to this first document the above reasoning remains valid.

FIG. 4 represents the situation when T D 2T. From this figure it follows that the final configuration of the information stored in the shift register is 10101011 for the documents represented in full lines and 101 1 l 101 for the documents represented in dotted lines. Hence, depending on the relative value of,2TD and T, there appears a 11 or a 101 configuration whilst otherwise the configuration 101 or 11 is prevailing.

From the description of the first embodiment of a document handling system (FIG. 6) given hereinafter it will become apparent that a configuration where several 1 states are following each other is to be rejected.

In FIG. 5 the case has been considered where D, T. In this case the first bistable device FFl of the shift register is set only once for two documents e.g., by clock pulse CP'4 for the documents 4 and and by clock pulse CP'7 for the

documents

8 and 9. Therefore, a system where 0 D, T is also to be rejected. The cases D, T and D 2T are limit ones.

Principally referring to FIG. 6 a first embodiment of a document handling system according to the invention is described hereinafter. Hereby it should be noted that only the case D 2T is considered so that the shift register configuration can be derived from FIG. 3.

Asfollows from the above there is nonnally a correspondence between the real movement of the document along the conveyor and the speed by which the corresponding l-information is shifted through the shift register. But the moving document may be subjected to a retarding effect giving rise to document jamming or to document stacking or the document may leave the conveyor and thus be lost. The document handling system shown is able to detect these defects, as will become clear from the following.

This system includes a photocell and associated circuitry Pl-Il mounted at the entrance of a document conveyor in front of a light source (not shown);

other photocells and associated circuitry, mounted along the conveyor path and serving as document posi- 1 tion detecting means. On FIG. 6 only another photocell PI-l2 and associated circuitry is represented. This photocell PH2 is situated in the part of the conveyor having a length covered by flip-flop FF3 of the shift register and x denotes the equivalent distance from the photocell PH2 to the origin of the conveyor length covered by the immediately following shift register flip-flop FF4;

a shift register constituted by n flip-flops FFl to FFn interconnected and controlled in the same way as shown in FIG. 1 and therefore only represented in a schematic way;

a document registering and jamming detection flipflop JD;

an alann device C;

a clock pulse generator (not shown) with output CP;

two 2-input AND-gates Al and A2;

a delay circuit DC.

The l-output of flip-flop FF3 is connected to one of the inputs of the two-input AND gate Al the other input of which is connected to the clock pulse generator output CP. The output of the AND-gate Al is connected to the l-input of the jamming detection flip-flop JD via the delay circuit DC, whilst the output of the position detecting photocell Pl-I2 is connected to the 0- input of the same flip-flop JD. The l-output of this flipflop is connected to one of the inputs of the two-input AND-gate A2 the other input of which is connected to the l-output of the flip-flop FF4, which acts as a controlling means. The output of the AND-gate A2 is connected to the alarm device C.

The shift register flip-flops FF3 and FF4 are hereinafter called the setting and the controlling flip-flop respectively since they are used to perform the setting of the jamming detection flip-flop JD and to control the state of this flip-flop respectively. Indeed, when the setting flip-flop FF3 is in its l-state, the output of the AND-gate Al is activated upon the occurrence of a clock pulse due to which flip-flop JD is set to its 1- condition via delay circuit DC. On the other hand the output of the AND-gate A2 is activated when both the flip-flops JD and FF4 are in their l-condition.

It has to be noted that the flip-flops FF3 and FF4 are taken as an example and that every two immediately following shift register flip-flops may be used, the choice of the setting flip-flop depending on the place of the position detecting photocell PH2.

This and other considerations will become clear by considering FIG. 7, wherein the horizontal scale is a time scale.

CP represents the clock pulses of period T. These pulses are not drawn "to scale, the pulse width and the clock pulse period being of the order of l microsecond and of several milliseconds respectively;

The pulses FF'3 represent the state of the flip-flop FF3 for a document processed (full line 1) and for a document immediately following the latter (dashed line 2). As already mentioned, only the case D 2T is considered. This implies that only the shift register configuration of the form 10101 100101 is considered. Only the configuration 101 has been represented;

Pl-I'2 represent the output pulses of the photocell PHZ for

successive documents

1 and 2, the first of which is leadinga time interval T T with respect to the corresponding clock pulse. The pulses l and 2 are separated by an equivalent distance D larger than 2T.

JD represents the state of the jamming detection flip-flop JD for these two followingdocuments;

PI-I"2 represents the output pulses of the photocell PI-IZ for two

successive documents

1 and 2, which are in phase with the corresponding clock pulse and which are separated by the equivalent distance D,

JD" represents the state of the jamming detection flip-flop JD for these two following documents;

FF'4 represents the state of the control flip-flop FF4 for the two documents;

PHS represents the output signal of the photocell PH2 for a document, which entered the conveyor in phase with the corresponding clock pulse.

Considering first the pulses CP, FFS, PH2, JD and FF4, the circuit represented in FIG. 6 operates as follows When the flip-flop FFS has been set (pulses FF'S) for a document, a delay time interval later the jamming detection flip-flop JD is set via the delay circuit DC if at that moment no document is intercepting the light beam emitted by the light source mounted in front of the photocell PH2. This is the case for document 2 (pulses PH2 dashed line), but not for the immediately preceding document 1 (pulses PI-I2 full line), so that the jamming detection flip-flop JD remains in its O-state for the first document 1, whilst it is set to its 1- state for the following one 2 (see pulses JD dashed line). The jamming detection flip-flop JD is reset when the leading edge of document 2 arrives in front of the photocell PH2. The controlling flip-flop FF4, when in its l-state controls the condition of the jamming detection flip-flop JD.lf at the moment the flip-flop FF4 is brought in its l-condition the flip-flop JD is still in its l-state, i.e. when no new document has arrived yet to reset this jamming detection flip-flop or when a document stack has been formed or when a document has been ejected out of the conveyor path before the position determined by the photocell PI-I2 has been reached, an alarm signal is produced by C, due to the fact that both inputs of the AND-gate A2 are activated.

Considering next the pulses CP, PI-I"2, JD" and FF4, the jamming detection flip-flop JD is set and afterwards reset for the document 1 and the immediately following document 2 respectively.

The aim of the delay circuit DC inserted between the output of the AND-gate Al and the input of the jamming detection flip-flop JD is to prevent an alarm signal from being produced when the setting flip-flop FFS is brought in its l-state for a given document (2) before the control flip-flop FF4 is reset for an immediately preceding (1) document.

In the above, the setting and control flip-flops are two immediately following flip-flops FFS and FF4. This is absolutely necessary since when these flip-flops are for instance FPS and FFS an alarm signal may be generated due to the shift register configuration being mainly l 1 although the two l-information belong to two following documents.

If the shift register configuration is of the 111 type, i.e., for an equivalent document distance D of less than 2T, the setting and control flip-flops may neither be immediately following ones, nor may they be not immediately following ones so that such a system has to be rejected. Indeed, it is sufficient that three l-states follow each other in the shift-register to have a coincidence between the l-state of the control and setting flip-flop and to consequently generate an alarm signal in C.

From FIG. 7 it can be derived that the time delay or the detection delay DDL between the moment of detection of a document by the photocell Pl-I2 and the moment of control by the control flip-flop FF4 is x-s, s being the retarding slip of a document and x being the equivalent distance defined earlier. This detection delay DDL is maximum for s minimum and x maximum i.e. for s 0 and x T in which case DDL T. Obviously x s since when x s no resetting of the jamming detection flip-flop JD is possible before the control is carried out. If a document is leading by T with respect to the corresponding clock pulse a supplementary delay equal to T is produced so that the total maximum detection delay then becomes equal to 2T.

It should further be noted that the jamming detection flip-flop JD has to be set before the moment the trailing edge of a document has passed in front of the photocell PH2, since otherwise no resetting would be possible and that the control flip-flop FF4 has to be set later than the moment the leading edge of the document passes in front of the photocell PHZ, since otherwise the jam detection flip-flop JD is reset after the moment the control is carried out. If the movement of the documents along the conveyor path is such that the above mentioned conditions are satisfied no alarm signal will be produced. On the contrary, when a document moves so fast that its trailing edge has passed in front of the photocell PH2' before the moment the jamming detection flip-flop JD has been set or if a document moves so slow that the control flip-flop FF4 is set before it arrives in front of the photocell PI-I2, an alarm signal will be produced in both cases. Hence an alarm signal is produced when the speed of a document has a value which is smaller and larger than the one and the other of two speed limits respectively. Alternatively no alarm signal is produced when this speed value is comprised between these two limits. This maximum detection delay can be reduced by using intermediate pulses, as will be explained hereinafter In FIG. 9 the main clock pulses and these intermediate pulses are represented by GP and CPI, CP2 and CPS respectively, the pulses CP' and CPI to CPS being shifted with respect to each other by a time interval equal to T/4 and in general by T/k.

FIG. 8 is a schematic view of the shift register and associated circuitry. The differences with FIG. 6 are that one of the inputs of the AND-gate Al is now controlled by an intermediate pulse CPI, f.i. that the output of this AND-gate is directly connected to the input of the jamming detection flip-flop JD and that the l-input of the AND-gate A2 is now also controlled by another intermediate pulse CPS f.i. The pulse CPl can be consid ered as a setting pulse, while the pulse CPS can be considered as a controlling pulse. In this particular case the l-output of flip-flop FFS is connected to an input of both the gates Al and A2. The choice of this flip-flop and of the intermediate pulses used for setting and control depends on the position of the photocell PH2.

In FIG. 10 FFI to FFn represent the n flip-flops of the shift register shown in FIG. 8. The main clock pulses are represented by GP and CPI to CPS indicate the intermediate pulses. In this particular case there are three

intermediate pulses

1, 2 and S equal spaced by T/4. FF'S represents the state of the shift register flip-flop FFS for two

successive documents

1 and 2; PH'2 represents the output signal of the photocell PHZ for two

successive documents

1 and 2; JD indicates the state of the jamming detection flip-flop JD; and C indicates the result of an AND-gating of the control pulse CPS and the output of FFS. All the signals relative to the document 1 have been drawn in full lines, while the signals relative to the following document 2 are shown in dashed lines.

Although in the above embodiment of FIG. 8 flipflop FFS simultaneously constitutes the setting and the control flip-flop, the control may also be carried out by one of the main or intermediate clock pulses following the one used to set the setting flip-flop and with the help of one of the flip-flops FF4 to FFn. Also, in this embodiment the case T D 2'! is allowable when the same flip-flop is used for setting and control. In this case the configuration of the shift register is formed by I I I s interleaved by 101's.

The detection delay DDL may again be defined by the time interval elapsing between the detection of the document by the photocell and the control of the jamming detection flip-flop.

Indicating by qT/k the amount spacing the main clock pulse and the immediately following controlling intermediate pulse, by T the period of the main clock pulses CP' and by s the retarding slip, this detection delay may be written as follows The difference qT/k (T x) can always be chosen smaller than or equal to T/k, so that the maximum detection delay, which occurs when s is then at most equal to T/k.

If a document is leading by T with respect to the corresponding clock pulse, a supplementary delay of lTis produced so that the total maximum detection delay then becomes at most equal to T T/k.

It should be noted that in the claims the predetermined position corresponds with the position of the photocell Pl-I2;

the bistate registering means are constituted by the jamming detection flip-flop JD;

the first signal generator is constituted by the shift register;

the first signal is the one produced at the output of the delay circuit DC (FIG. 6) or the one produced at the output of the AND-gate Al (FIG. 8);

the second signal (FF'4) is the one produced at the output of the shift register bistable device FF4;

the detection means are constituted by the photocell Pl-l2 and associated light source;

the third signals are the output signals PH'2, PH2 (FIG. 7 FIG. 10) of the photocell PH2;

the setting means are'constituted by the AND-gate Al and the delay circuit DC (FIG. 6) or by the AND- gate Al (FIG. 8);

the control means are constituted by the AND-gate A2;

the fourth signal FF3 is the one produced at the output of the shift register bistable device FF3;

the source of clock pulses is the clock pulse generator generating clock pulses CP';

the second signal generator is constituted by the clock pulse generator generating the intermediate pulses CPI to CP3;

the fifth signals are the intermediate pulses CPI;

the sixth signals are the intermediate pulses CP3.

While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

I claim:

1. Document handling system including a conveyor means to convey documents along a conveyor path;

bistate registering means which are normally in a first of two conditions;

signal generator means to generate at least one first signal and at least one second signal, said second signal following said first signal by a predetermined time interval;

detection means generating a third signal upon the passage of each of said documents at a predetermined position of said conveyor path and being adapted to reset said registering means in said first condition depending upon the occurrence of said third signal;

setting means cooperating with said signal generator means to set said registering means in the second of said two conditions depending on the occurrence of said first signal;

and control means cooperating with said signal generator means to control the condition of said registering means depending on the occurrence of said second signal and to generate an output signal upon said registering means being found in a predetermined one of its said first and second condition, characterized in that said signal generator means are constituted by a shift register provided with a plurality of stages and in which, for each document handled, means are provided to place the first of said stages in a predetermined condition, driving means being provided for said shift register to shift said predetermined condition through said stages, that said first and second signals are generated when said predetermined condition is registered in a second (FF3) and in a third (FF4) stage of said shift register respectively.

2. Document handling system as claimed in claim 1, characterized in that said driving means are constituted by a source of clock pulses whose frequency is so chosen with respect to the speed of advancement of the documents through said conveyor path that said third signal is applied to said bistate registering means after said first and before said second signal as long as a document moves within prescribed speed limits.

3. Document handling system according to claim 2,

characterized in that said first signal is generated after the occurrence of a fourth signal (FF'3) and a clock pulse of said source of clock pulses, said'fourth signal being produced upon said predetermined condition being registered in said second stage of said shift'register.

4. Document handling system according to claim 3, characterized in that it further includes second signal generator means adapted to generate a fifth signal (CPI) during said fourth signal and that said setting means also cooperate with said second generator means to set said registering means in said second condition upon the occurrence of both said fourth and fifth signals.

5. Document handling system according to claim 4, characterized in that said second signal (FF4) is constituted by said fourth signal, that said second signal generator means are adapted to generate a sixth signal (CP3 during said fourth signal and after said fifth signal, said third (Pl-I'Z) signal being generated between said fifth and sixth signals, and that said control means also cooperate with said second generator means to control the condition of said registering means upon the occurrence of said fourth and sixth signal.

6. Document handling system according to claim 5, characterized in that said predetermined condition is shifted through said stages of said shift register by means of clock pulses of a predetermined frequency and that said fifth and sixth signals also have said predetermined frequency.