DE2212541A1 - Document processing system - Google Patents

Description

Patent attorney '' ^UJHI

Dipl, -Phys. Leo Thul

Stuttgart

R. Terryη -2

INTERNATIONAL STANDARD ELECTRIC CORPORATION, New York Document processing system

The invention relates to a document processing system with an arrangement for monitoring the transport of the documents within a transport route that is at certain intervals with light barriers (Light source photocell) is provided, each of which is assigned a bistable memory, each of which is one Input by trigger controlled impulses of the respective light barrier is influenced and the other input of which is under the influence of clock pulses that do not occur of the light barrier impulses the respective storage levels in set a switching state in which an alarm is issued.

Such a document processing system is already known from Belgian patent 614 430.

This known system sees a number of bistable storage stages before, whose O outputs are each connected to the output of a corresponding AND gate. One each The input of this AND gate is connected to the output of a corresponding photocell. These photocells are "on arranged predetermined locations along the transport route. Each of these photocells generates an output signal when they is illuminated by an associated lamp. This means that no output signal is generated whenever a

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Receipt is in front of the photocell. The second inputs of the AND gates are shared with the output of a trigger pulse generator connected, so that each of the bistable memory stages is toggled to the O state when the respective AND gate becomes conductive, i.e. a trigger pulse arrives the storage level if the associated photocell is illuminated. If, on the other hand, there is a receipt between a photocell and the associated lamp, the memory stage is not reset to the O state. The! Inputs of all bistable Storage stages are shared with the output of a clock pulse generator s connected. Control means monitor the O-state of the bistable memory stages mainly by means of clock pulses, which will continue to be referred to as control pulses and which each shortly before the end of a clock pulse period be generated. A possible malfunction is indicated by an alarm signal if at least one of the bistable Storage levels is still in the 1 state at the moment the control pulse is generated. This indicates that calibrated Receipt for a normal long time in front of the associated photocell or that the distance between two each other The following documents have become so small that no trigger pulse is generated during the corresponding illumination of the photocell became.

The disadvantage of the system described above is that it does not recognize when, for example, documents from the transport route be thrown out. Rather, the bistable storage stage, whose photocell is arranged downstream of the point,

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at which a document was thrown out, in the O-state resets. For the same reason, incorrectly forming document jams on the transport route between two successive potentiometer positions not recognized ι

The invention is therefore based on the object of a document processing system to create that is able to recognize ejected and accumulating documents.

This object is achieved according to the invention in that at the place of the bistable memory is a shift register with a large number of memory stages, the clock sequence of which occurs the document speed is adapted that with the entry of a document into the transport path over a first light barrier the first storage stage of the shift register is set that via a second or subsequent light barrier assigned memory stage in the course of the shifting process an error trigger stage is set that this is properly transported document by an impulse from the ^ second or following light barrier is switched back before a pulse from the following storage stage the switching state of the error flip-flop is checked and that if the error flip-flop is not reset an alarm is triggered.

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The invention is explained in more detail below using two exemplary embodiments in conjunction with the drawings. Show it:

Fig. 1 is a schematic representation of a shift register with associated circuit, the one Forms part of the document processing system according to the invention.

Fig. 2 pulse trains as they occur in the course of the operation of the shift register.

Fig. 3 »^ and 5 the relative timing of clock pulses to documents that are evaluated in connection with a document processing system according to the invention will.

6 shows a schematic illustration of a first embodiment of a document processing system according to the invention.

7 shows pulse sequences as they occur in the course of the operation of the system according to FIG.

8 shows a schematic representation of a second embodiment of a document processing system according to the invention.

9 and 10 pulse trains as they occur in the course of the operation of the system according to FIG.

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Pig. 1 shows a photocell PH1 which is arranged at the beginning of a document transport path (not shown) and serves to identify the documents fed to the transport path via a mechanism (not shown). A light source (not shown) is arranged opposite the photocell PH1 on the other side of the transport path. When the photo cell PH1 is illuminated by the light source, the photo cell always emits an output signal PH ¹ I when the lighting is interrupted. The output of this photocell is connected to the 1 input of a monostable multivibrator MS via an amplifier A. This trigger stage has a time constant t and is tipped into the unstable state by the leading edge of the photocell signal. The 1 output of this multivibrator MS is connected to the 1 input of a bistable buffer storage stage FFB. Its 1 output is connected to the 1 input of the first bistable storage stage FFl of a shift register which consists of η interconnected bistable storage stages FFl and FFn. The O output of the buffer storage stage FFB is connected to the O input of the storage stage FFl, the 1 output of this storage stage is connected on the one hand to the O input of the buffer storage stage FFB and on the other hand to the 1 input of the second storage stage FF2. The I and O outputs of each shift register storage stage FF2 to FFn-I are in turn connected to the I and O inputs of the respectively immediately following storage stage FF3 to FFn.

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The inputs of all memory levels PPI to PPn that trigger jointly are all not with the output CP of one clock shown connected.

It should be noted that the above-described bistable storage stages are in the starting position in the O state, in which their O and! outputs are in the conductive or »non-conductive state. These bistable storage stages are of the well-known type of the so-called master-slave type. Such storage levels can only be theirs Change the switching state if the jointly triggering input receives a pulse at the same time as the switching command 1st. In the present case, this change in the switching state takes place via the trailing edge of a clock pulse. For example, the storage stage PFl which is in the O state can only be switched to the 1 state, if, at the same time as the 1 input is activated, a clock pulse arrives at the jointly triggering input.

In connection with Flg. 2 the mode of operation of the shift register with the associated circuit according to Pig. I. described in more detail.

When a document is fed to the transport route, it interrupts the light beam directed from the light source onto the photocell PH1. The latter thus generates an output signal PH ¹ I. After an amplification in the amplifier A, the resulting signal arrives at the 1 input of the monostable multivibrator MS, which is thereupon for the time t

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is set to the 1 state. The resulting output pulse ti arrives at the 1 input of the buffer storage stage FPB, which is thereby also switched to the! State and in turn emits a pulse PPB1 via the 1 output. With the occurrence of the first clock pulse CP ¹ I of a sequence of clock pulses CP ¹ with a cycle time T the first memory stage PPI is tilted of the shift register in the 1 state · same time, the reset occurs, the buffer memory stage PPB in the O-state. The second storage stage FF2 is switched to the 1 state by the immediately following clock pulse CP ¹ 2, while the first storage stage PPI is reset to the O state, provided that the buffer storage stage PPB is still in the O state at this point in time, ie , The reset only takes place if no new receipt has been added to the transport route. When a subsequent document arrives, the buffer storage stage PPB is switched back to the 1 state, ^{the first storage stage PPI is then set again via the third clock pulse CP f} 3 and, at the same time, the buffer storage stage PFB is reset. At the same time, the information in the shift register is advanced by one level. However, if the next document causes the setting of the buffer storage stage FPB before the occurrence of the clock pulse CP >> 2, the storage stage PPI is set by the clock pulse CP * 2.

From the above it follows that every time the A document is fed to the transport route, the first storage

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stage PFl is toggled into the 1 state and this state is shifted through the register at the clock pulse rate. The pulses PP ¹ I, PP ^{>> 2 to PP 1} η of FIG. 2 represent the pushing pulses by which the prescribed pushing process is triggered.

Before describing a document processing system according to the invention, the following should be noted: If L is the total length the transport route, T the cycle time of the tent cycle pulses, ν is the transport speed of the documents and η is the number of storage levels that corresponds to the total length of the transport route correspond, where the shift speed with which a 1-state is advanced through the register corresponds to the theoretical movement of the associated document along the transport route, then the following applies Relationship:

ν η T = L

The section of the transport route assigned to a storage stage therefore

π = ν. τ

so that - can be expressed by an equivalent time or T by an equivalent length. The equivalence factor is v in both cases. The same relationships exist if D is the distance between two consecutive documents and t _{D represents} the time it takes for a document to overcome the distance D. Then the following relationship applies:

D = tjj ν or

t - ^D.

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The time t _D is referred to as the equivalent document distance and is represented by D _e . In the same way, the equivalent time T _e = t _D ν represents the distance D between the documents.

In connection with FIGS. 3 to 5, the influence of the equivalent document spacing D _e between two consecutive documents compared with the clock time T of the clock pulses CP 'on the occupancy of the shift register is considered in more detail.

Fig. 3 shows the relative position of fifteen clock pulses CP 1 I to CP ^{f 15 and seven documents 1,} 2 ... 7. Each of the arrows is used to assign a clock pulse to a document, which indicates the clock pulse through which the first storage stage FFl of the shift register is set to the 1 state, that is, is stored by the presence of a document in the shift register. The equivalent document spacing D _e is greater than 2T, so that when all seven documents are registered in the last to the first stage of the shift register according to FIG that of the relative value of D _e - 2T and T depend on the sequence 1001 arises, while otherwise the sequence 101 prevails. It should be noted that in Fig. 3, the first document 1 is shown in phase with the clock pulse CP ¹ I. Even if this clock pulse lags or leads with respect to the first document, what was said before remains valid «

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Pig. 4 shows the relationships when T <D _e <2T. It can be seen from this figure that the final assignment of the shift register results in the case of the solid documents shown as 10101011 and in the case of the documents shown in dashed lines as 10111101. Thus, depending on the relative values 2T - D _e and T, an 11 or 101 sequence occurs, while otherwise the sequence 101 or 11 predominates.

From the following description of the first exemplary embodiment of a document processing system (FIG. 6) it becomes understandable that a sequence of several consecutive 1-states is to be rejected.

In FIG. 5, the case is dealt with when 0 <D _e <T. Here the storage stage FFl of the shift register is set only once in two cases for two documents, ie by the clock pulse CP ¹ 4 for the documents 4 and 5 and by the clock pulse CP ^f 7 for the documents 8 and 9. A system is therefore to be rejected where 0 <D _e <T. A restriction must therefore be made to the cases in which D _e = T and D _e = 2T.

In connection with FIG. 6, a first embodiment of a document processing system according to the invention is described below. It should be noted here that only the case D _e = '2T comes into consideration, so that the shift register curve can be derived from FIG.

From the above it follows that between the actual movement of a document along the transport route and the speed at which the corresponding

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! Information normally passes through the shift register matches. However, the movement of the document can be subjected to a braking effect caused by jamming of the document or is caused by a jam or the document leaves the transport route and is thus lost. That The document processing system shown is able to recognize these errors, as can be seen from the explanations below emerges.

This system consists of:

a photocell with associated circuit PHl, which initially the document transport route is arranged opposite a light source (not shown),

further photocells with associated circuitry, which are arranged distributed along the document transport route and for Detection of the line items are used. In Fig. 6 only one of these photocells PH2 is shown with the associated circuit. This photocell PH2 is located in the part of the transport path that is assigned to the storage stage FF3 of the shift register, where χ is the distance from the photocell to the beginning indicates the transport leg that is assigned to the following storage level,

a shift register which comprises η storage stages FFl to FFn, which are linked and controlled according to FIG. 1 and are therefore only shown schematically,

from a tilting stage JD for document registration and deadlock detection,

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an alarm device C,

a clock generator (not shown) with the output CP,

two AND gates Al and A2,

a delay circuit DC,

The 1 output of the storage stage FF3 is connected to one of the two inputs of the AND gate A1. The second gate input, on the other hand, is connected to the output CP of the clock generator. The output of the AND gate A1 is connected to the 1 input of the trigger circuit JD via the delay circuit DC, while the photocell PH2 is connected on the output side to the O input of the same trigger circuit JD. The 1 output of this flip-flop is connected to one input of the AND gate A2, while the 1 output of the storage stage FF ¹ I is connected to the second input of the gate. The output of the AND gate A2 is finally connected to the alarm device C.

The storage stages FF3 and FF ¹ I of the shift register are referred to below as the setting or control stage, since they carry out the setting or the status control of the multivibrator JD. When the storage stage FF3 is toggled into the 1 state, the AND gate A1 becomes conductive with the occurrence of a clock pulse, as a result of which the multivibrator JD is put into the 1 state via the delay circuit DC.

It should be noted that the memory stages FF3 and FF ¹ I have only been selected as an example and that each

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other groups of two successive storage stages in the shift register can be used, with the choice the riser depends on the position of the detection photocell PH2 »

These and other considerations are discussed in connection with Pig. 7 clearly.

The pulses CP ¹ represent clock pulses with a clock time T. These pulses are not shown to scale. The pulse width and the cycle time are on the order of 1 microsecond or a few milliseconds.

The pulses PP'3 represent the state of the storage stage PP3 for a registered document (full line, 1) and for an immediately following document (dashed line _# 2). As already mentioned, only the case D _e > 2T is considered means that only a shift register assignment of the form 10101. ,, 100101 is taken into account, with only the sequence 101 being shown.

The pulses PH'2 represent the output pulses of the photocell PH2 caused by the successive documents 1 and 2, the first of which leads the associated clock pulse by a time interval T '<T. The pulses 1 and 2 are separated from one another _{by an equivalent distance D e> 2T.}

The pulse JD 'indicates the switching state of the trigger stage JD during of the two consecutive documents.

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The pulses PH ″ 2 represent the pulses caused by two consecutive documents 1 and 2, which are in phase with the associated clock pulses and which have an equivalent distance D _e from one another.

The pulses JD "represent the switching status of the trigger stage JD for these two consecutive documents.

The pulses PP ¹ 4 show the switching state of the control storage stage PP4 while the two documents are running through.

The pulse PH "3 represents the output signal of the photocell PH2 represents a document that arrives in phase with the associated clock pulse in the transport route.

With a preliminary consideration of the pulses CP *, PP * 3, PH ¹ 2, JD ¹ and PF'4, the circuit shown in Fig. 6 operates as follows:

If the storage stage FF3 has been set for a receipt (pulses FP ¹ 3), the toggle stage JD is set after the delay time given by the device DC if the light beam directed at the photocell PH2 is not interrupted by a receipt before this point in time would be the case, for example, with document 2 (pulse PH ¹ 2 - dashed line), but not with the immediately preceding document (pulse PH ¹ 2 - solid line). In this latter case, the toggle stage JD remains in the 0 state, while in the case of document 2 it switches to the 1 state. The toggle stage JD for detecting a jammed document is reset again,

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when the front edge of receipt 2 is in the area of the photocell PH2 reached. By tilting the storage level FFiI in the I-state is a check of the switching state of the flip-flop JD. Is the flip-flop JD in this Momentary still in the 1-state, i.e. no new document has arrived up to then that resets this flip-flop, e.g. if a document jam has formed or if a document has been thrown out of the transport route before he has reached the position marked by the photocell PH2, the AND gate A2 is via the simultaneous control controlled by the storage stage FF4 and the trigger stage JD * The alarm device C is thus excited and emits a corresponding signal.

Next, consider the pulses CP ¹ , PH "2, JD" and FF ^f 4. The toggle stage JD was set and subsequently reset for document 1 or the immediately following document 2.

The one between the exit of the And-Oatter Al and the flip-flop JD arranged delay circuit DC is used to prevent an alarm signal when the set memory stage FF3 through a receipt (2) is set to the 1-state before the control storage stage FF4 on the basis of the previous receipt (1) has not yet been reset.

According to the above, the setting and Control memory levels by two immediately following one another de memory elements. This is an imperative

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speed, since ζ, B, when using the memory stages FF3 and FF5 an alarm signal would have to be assigned to the shift register assignment sequence 101 for this purpose, although the information belongs to two consecutive documents.

If the shift register epimg has the sequence 111, that is, that an equivalent document spacing D _{e is} less than 2T, the setting and control storage stages can neither be storage elements that follow one another directly, nor can they be those that do not follow one another directly so that such a system must be excluded. However, the sequence of three 1 states in the shift register indicates that both the control and the set memory stage are in the! State, which generally results in an alarm being triggered.

7 results in -lir.lr un ^c - never delay time DDL between the determination · i; (■ -le ^ it is through the photocell PH2 and the moment of the Y ■ ■ .- · '·. ~ \ Astung by the storage stage FF ¹ I xs, Hi-- χ ίΜ "ε the slip of a document and χ the above er j rtu equivalent distance. This delay time DDL; - longest if s = 0 and χ = T »In this case ier. ό < jjDL = T, It is evident that χ> s must be, since b < 7 < It is no longer possible to reset the flip-flop JD prior to the verification process

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maximum total delay becomes 2T.

It should also be noted that the toggle stage JD must be set before the trailing edge of the document in question enters the effective range of the photo cell PH2, otherwise no resetting is possible, and that the control memory stage FF4 may only be set when the front edge of the receipt has passed photocell PH2, otherwise the JD flip-flop is only reset after the control keying has been carried out. If the receipts are in compliance move in the transport route under the above conditions, no alarm signal is triggered. If, on the other hand, a receipt is transported so quickly that its rear edge has already passed the photocell PH2 before the toggle stage JD is set has been, or if a document is transported so slowly that the control memory level FF4 has already been set has been before the receipt of light to the photocell PH2 has interrupted, an alarm signal is triggered in both cases. From this it follows that an over or Falling below a specified speed range leads to an alarm being issued.

The aforementioned maximum delay time can be set in the later described Way can be shortened by intermediate impulses:

9 shows the clock pulses CP ¹ and intermediate pulses CP1, CP2 and CP3 assigned to them. The time shift of the pulses to each other corresponds to a time interval of T / 4, in general terms T / k *

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Pig. 8 shows a schematic diagram of a shift register with the associated circuit. The differences to the embodiment according to FIG. 6 are that one input of the AND gate Al is now controlled by the intermediate pulses CPl. In this case, the AND gate Al is directly with on the output side connected to the 1 input of the flip-flop JD and the third input which in this case has three input lines AND gate A2 is controlled by the intermediate pulses CP3. The pulses CPl can be used as setting pulses and the pulses CP3 are referred to as control pulses. In this particular case, the 1 output of the storage stage is FF3 with each connected to an input of the AND gates A1 and A2. The choice of the storage stage and the intermediate pulses for the setting and Control processes depend on the position of the photo cells PH2.

In FIG. 10, the storage stages FF1 to FFn represent the shift register of FIG. 8. CP ¹ form the clock pulses, while CP1 to CP3 represent the intermediate pulses. In the present case, three intermediate pulses I ₁ 2 and 3 are provided with a spacing of T / 4. FF'3 shows the state of the shift register memory FF3 for two consecutive documents 1 and 2. PH ¹ 2 represents the output signals of the photocell PH2 for two consecutive documents 1 and 2. The pulses JD 'indicate the switching state of the flip-flop JD and C. indicates the time of an alarm when a simultaneous activation of the AND gate A2 by the control pulse CP3 and the memory stage FF3 takes place. All focus on receipt 1

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Related signals are shown in solid line, while the signals assigned to the following document 2 are shown in dashed lines are, .

Although in the above-described embodiment according to FIG. Din storage stage FP3 effects both the setting and the control function, the control can also be carried out by a Tak <™ or dual impulse that follows the one by which the setting storage stage is set and with the help of one of the memory levels FF4 to FFn. In this embodiment, T <D _ß <2T is also permissible if the same memory stage is used for the setting and control process. In this case, the shift register is occupied by alternating sequences 111 and 101.

The delay time DDL also represents the time interval in this case between the receipt recognition by the photocell PH2 and the activation of the JD flip-flop.

If one sets for the amount of time between the clock pulse and the next following intermediate pulse * ~ _t vreiterhin T for the clock pulse

Bl

time of the clock pulses CP ¹ and for the slip s _# , the following relationship results for the delay time:

DDL = Bl - (τ - χ) - s k

The value SL- (T - x) can always be less than or equal to k

2 can be chosen so that the maximum delay time that

until s = O occurs, then at most -.

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If a document is ahead of the clock pulse by a clock time T, a supplementary delay of a clock time T is effected, so that the total delay can be at most T + Σ .

1 claim
5 sheets of drawings

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Claims (1)

R. Terryn -2 - 21 - Claim Document processing system with an arrangement for monitoring the transport of the documents within a transport route, which is provided at certain intervals with light barriers (light source photocell), each of which is assigned a bistable memory, whose input is influenced by trigger-controlled pulses from the respective light barrier the other input in each case is under the influence of clock pulses which, if the light barrier pulses fail to occur, put the respective storage stages into a switching state in which an alarm is triggered, characterized in that . that the bistable memory is replaced by a shift register with a multitude of memory stages, the clock sequence of which is adapted to the speed of the document so that when a document enters the transport path via a first light barrier (PHl), the first memory stage (PPI) of the shift register is set, that an error toggle stage (JD) is set via the storage stage (PP3) assigned to a second or following light barrier (PH2) in the course of the shifting process, that this is switched back by a pulse from the second or »following light barrier (PH2) when the document is properly transported is before the switching state of the error flip-flop (JD) is checked via a pulse from the subsequent storage stage (FF4) and that an alarm (C) is triggered if the error flip-flop (JD) is not reset. March 13, 1972
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