US3712468A

US3712468A - Device which scans and detects for contents in a package

Info

Publication number: US3712468A
Application number: US00118369A
Authority: US
Inventors: W Wenner; B Stuhlmuller; A Bouloutian; P Zakarian
Original assignee: Individual
Current assignee: Individual
Priority date: 1971-02-24
Filing date: 1971-02-24
Publication date: 1973-01-23
Anticipated expiration: 1990-01-23

Abstract

There is disclosed herein a device that scans for contents or lack of contents in an enclosed package such as a postal envelope and separates those items which have contents from those which do not. Contents or lack of contents are determined by sensing the thickness of the package over a specified length. If the detection of thickness occurs over a distance less that that specified, it is determined that the package has no contents and therefore, the package is directed into the ''''normal'''' receptacle. Conversely, those packages with contents are directed into the ''''exception'''' receptacle. The disclosed device also provides for the use of multiple sensors so that various portions of the enclosed package may be simultaneously scanned for thickness. Unless one or more of the sensors provides a positive indication of contents over the specified length and distance of travel, the device will again place the package in the ''''normal'''' receptacle. There is also disclosed means of assuring that those packages which have been scanned for contents or lack of contents are correctly separated into the appropriate receptacle. If proper sorting does not occur, the device is automatically stopped. In addition, there is disclosed for inventory purposes an arrangement which counts the total pieces that are scanned by the device as well as those pieces which are sorted into the ''''exception'''' receptacle.

Description

United States Patent [1 1 Wenner et al.

[ 51 Jan.23, 1973 54] DEVICE WHICH SCANS AND DETECTS FOR CONTENTS IN A PACKAGE [76] Inventors: William Wenner, 608 Delaware Ave., Lansdale, Pa. 19446; Brian J. Stuhlmuller, 634 W. 70th St., Kansas City, Mo. 64l'l3; Ara Bouloutian, 2515 Turner Rd., Willow Grove, Pa. 19090; Paul Zakarian,

3302 Windsor Ave., Norristown, Pa.

221 Filed: Feb.24, 1971 211 Appl.No.: 118,369

UNITED STATES PATENTS 12/1967 Beert ..209/74 R X 6/1969 Murley ..209/82X Primary ExaminerRichard A. Schacher Attorney-Rene A. Kuypers ABSTRACT There is disclosed herein a device that scans for contents or lack of contents in an enclosed package such as a postal envelope and separates those items which have contents from those which do not. Contents or lack of contents are determined by sensing the thickness of the package over a specified length. lf the detection of thickness occurs over a distance less that that specified, it is determined that the package has no contents and therefore, the package is directed into the normal receptacle. Conversely, those packages with contents are directed into the exception receptacle. The disclosed device also provides for the use of multiple sensors so that various portions of the enclosed package may be simultaneously scanned for thickness. Unless one or more of the sensors provides a positive indication of contents over the specified length and distance of travel, the device will again place the package in the normal receptacle.

There is also disclosed means of assuring that those packages which have been scanned for contents or lack of contents are correctly separated into the appropriate receptacle. lf proper sorting does not occur, the device is automatically stopped.

In addition, there is disclosed for inventory purposes an arrangement which counts the total pieces that are scanned by the device as well as those pieces which are sorted into the exception receptacle.

10 Claims, 11 Drawing Figures PATENIEDJM423 1925 3,712 468 sum 1 0F 9 PATENTED JAN 2 3 I975 SHEET 3 [IF 9 THRESHOLD DETECTOR TIMER DETECTOR F L lP-FLOP DETECTOR SWI T C H 0G MP l 2 SHEET UF 9 DETECT FLIP-FLOP DE CODER INVERTER GATE SOLENOID PATENIEDJAN23 I975 3,712,468

SHEET 5 [IF 9 EXCEPTION FLIP-FLOP ACC WENTEnmzs ms 3.712.468

SHEET 6 0r 9 DELAY DETECT FLIP-FLOP DDET DET

PMENTEmma I973 3.712.468

SHEET 7 BF 9 ERVROR COMPARE STOP FL|P-FLOP AC C ERR

DDET

TR 4L ERROR OUT DDET cl EAR ACC +V ERROR ovERRTDE SWITCH PATENTEUJAII23I975 3.712.468

sum 9 [IF 9 TIMING CHAIN INVERTER INVERTER INVERTER I TOTAL COUNTER INVERTER DEVICE WHICH SCANS AND DETECTS FOR CONTENTS IN A PACKAGE BACKGROUND OF THE INVENTION foolproof device for determining whether contents still remain in an envelope after presumably they have been removed. This problem has become particularly acute since oftentimes ill will is created, for example,

between a department store and its customers for failure to remove a check or alternatively, a stub or computer data card so that credit is not given to the customers charge account. Accordingly, harsh feelings and poor public relations are engendered between the customer and the store,

A known system designed to solve the above stated problem has not been entirely satisfactory. The known system is based on the principle called candling and is accomplished through the use of a light beam and a photocell. In this system, if contents remain in an envelope after presumedremoval, the light beam will strike the opaque contents thereby affecting the light signal to the photocell. Theenvelope is then routed to the appropriate bin. One shortcoming of the optical system is that smudges, color, paper density, stamps and emblems, etc. give false readings. In addition to this, the optical system described above is deemed to be expensive and difficult to maintain.

Another recognized shortcoming of the known prior art is that these devices are not able to sort out items which have more than the prescribed contents. Such a situation might occur under the following circumstances. The dividend department of a corporation in disbursing the quarterly checks to the stockholders accidentally stuffs two checks into one item. The disbursing department does not become aware of this fact until an extra envelope is found at the end of the job. If the corporation is a large one and a large number of items is involved, the task of locating the extra check is a formidable one. The system based on the prior art candling principle cannot perform this task since differentiation is not possible between an item having more than the prescribed contents SUMMARY OF THE INVENTION The present invention utilizes multiple detectors which scan an item for thickness over a specified distance of travel. The detectors are pre-set so that a certain thickness item can pass through without being activated. If the item passing through the detectors is thicker than the maximum setting, the respectivedetector is activated, thereby setting as associated flipflop device which in turn initiates an associated timer circuit. The purpose of the timer is to determine the length of time that the detector is activated. The output of the various timers are fed into a decoder. The decoder provides an output signal which energizes a solenoid when one or more of the detectors is activated for the predetermined time, (i.e., over the specified distance of travel). The solenoid in turn moves a gate, which directs the item into the exception receptacle, (i.e., the receptacle receiving those items with contents).

Contrariwise, if no detectors are activated over the specified distance of travel, the solenoid and gate remain unaffected so that the item is directed into the normal receptacle, (i.e., the receptacle receiving those items without contents). Accordingly, the instant invention separates those items which have a certain thickness from those which do not.

The instant invention also assures that the scanned item enters the proper receptacle. Thus, four conditions are constantly monitored during the scanning operation, namely,

a. the item has contents and enters the exception receptacle.

b. the item has no contents and enters the normal" receptacle.

c. the item has contents and enters the normal receptacle.

d. the item has no contents and enters the exception receptacle.

This monitoring is accomplished by utilizing an error detector circuit which observes the state of two flipflops. One flip-flop is set by the activation of a photocell whenever an item enters the exception receptacle. The other flip-flop is set by the output of the above discussed decoder. The error detection circuit samples the state of the two flip-flops during a prescribed time period and automatically stops the further operation of the device for conditions c and d.

In order to enable proper inventory of items, a count,

is kept of the total items entering into the machine as well as those items entering the exception receptacle. This is accomplished by activating a photocell located immediately adjacent to the detection sensors. Each time that the photocell is activated by a single item, a signal is produced which in turn adds one count to a counter mechanism. A second photocell is activated each time that an item enters the exception" receptacle. In like manner, this photocell produces a signal which adds one count to the fexception counter.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. I depicts the mechanicalarrangement of the detection system used to scan the contents of an envelope. I

FIG. 2 illustrates an envelope wherein the paths traversed by the detectors are shown in dotted form.

FIG. 3 shows in'block form the electronics utilized with the mechanical arrangement of FIG. 1.

FIG. 4 represents the circuitry in block form required to develop the required timing pulses.

FIGS. 5, 5A, 5B, 5C, and 5D depict the circuit schematic of the block diagram of FIG. 3.

FIG. 6 shows the relationship of the various timing and function pulses with respect to one another.

FIG. 7 is the circuit schematic of the block diagram of FIG. 4.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the transport device of FIG. 1 in greater detail, respective envelopes (not shown) are separated from a stack in accordance with well known prior art arrangements and pass between the rollers 18 and 20. An example of a known prior art technique for separating and feeding envelopes from a stack is embodied in the prior art patent, U.S. Pat. No. 2,762,623 and its teaching is incorporated by reference herein. Accordingly, rollers 23 and 25 of the above cited patent correspond to rollers 20 and 18, respectively, in the instant invention. The rollers 18 rotate clockwise and the rollers 20 counterclockwise as viewed from the right.

It is also a required function of the prior art sheet feeding mechanism to insure a predetermined minimum time separation between consecutive en-.

velopes entering the transport device. The above cited patent inherently provides this required time separation. The transport device shown as well as the sheet feeding device of the prior art are driven by means of a motor, chain and gear drive which are not shown to simplify the drawing and for ease of understanding and furthermore, these devices are within the purview of those skilled in the art.

An envelope after passing through the rollers 18 and 20 traverses a path between the detector drive roller 22 and the three detector wheels 24, 25 and 26. The detector wheels rotate clockwise and the drive roller 22 counterclockwise as viewed from the right. Each of the detector wheels is coupled respectively by mechanical linkage 35 and pivot 33 to a detection switch 28. Only one linkage, pivot andv switch is shown to simplify the drawing. The detection switch 28 comprises what is commonly referred to as a Micro Switch. The mechanical detection arrangement just described is exemplary only and other types may be readily used without departing from the spirit of the invention.

Each detector roller is pre-set for a given thickness by means of the micro adjustment 34. The purpose of the micro adjustment 34 is to control the position of the Micro Switch 28 relative to the linkage 35. The position of the linkage with respect to the Micro Switch 28 determines the amount of rotation about pivot 33 necessary to activate (i.e., depress) the button 30 when an envelope with contents passes under the detector wheels 24, 25 and 26. Each switch is adjusted and operates independently of any other.

' Referring now briefly to FIG. 2, an envelope 32 is depicted with-contents 31 (in rectangular outline form) remaining therein after supposed removal. Also shown with dotted lines is the path 24', 25' and 26' covered by the respective detector wheels 24, 25 and 26 as en velope 32 passes through the device. The contents 3] are only scanned by two of the detector wheels 25 and 26, as can be readily observed by viewing their respective tracks 25 and 26'.Therefore, the detector wheels 25 and 26will activate their respective switches. Onthe other hand, the detector wheel 24 does not scan the contents 31 as can be'observed by viewing the track 24. However, since the detector wheel 24 detects a portion of the seam of the envelope, it will also activate the associated switch. The switches associated with wheels 25 and 26 will be activated over a longer distance of travel (i.e., period of time) than will the switch associated with detector wheel 24. The significance of this fact will be discussed in greater detail hereinafter.

To develop a positive indication that contents 31 are contained in the envelope 32, it is required that one of more detector wheels (e.g., two out of three) scan for thickness over an adjustable minimum distance of travel (e.g., 3 inches). Referring to FIG. 2, assuming that the contents are longer than three inches, a positive indication is obtained that contents 31 are present in the envelope 32 since in this example two detectors, 25 and 26, scan for thickness over the predetermined minimum distance of travel of three inches. It was previously noted that the detector wheel 24 detects thickness because of the seam of the envelope. However, since the thickness does not occur over the predetermineddistance of travel of three inches, no meaningful signal is developed by detector wheel 24. This aspect of the invention will be further explored with respect to the accompanying electronic circuitry.

it should be observed that were contents 31 positioned in the upper portion of envelope 32, the aforementioned example, namely, that two out of three detector wheels are activated to provide a positive indication, would be satisfied since the tracks 24 and 25' would fall directly over the contents 31. Therefore, even though the contents 31 are in different locations, nevertheless a positive indication is produced by the system disclosed.

As the envelope passes by the detector wheels 24, 25 and 26, it causes the activation of the photocell 36. In other words, as the envelope passes over the photocell 36, it breaks a light beam (not shown) so that the photocell fails to pick up a light signal until after the envelope completely passes by. The change of light intensity sensed by the photocell is utilized as a signal for stepping a counter device (not shown) as well as providing timing signals for the electronic circuitry. Each envelope is therefore counted as it passes over the photocell 36.

When a positive determination of contents is made, a signal will be generated to energize a solenoid 40. The energized solenoid 40 causes the gate axle'4l to pivot so that the gate 44 rotates clockwise looking from the right. Simultaneously, the envelope traverses a measured distance between the detector drive roller 22 and the

ejector rollers

46 and 48. The ejector drive roller 48 and the ejector idler 46 accelerate the envelope into the -exceptionreceptacle 50 through gate 44 which has been preset according to the above description. Acceleration of the envelope is necessary to provide sufficient time to allow the gate 44 to return to its quiescent state. After the envelope with contents has traversed to the exception" receptacle 50, the solenoid is de-energized by means of a timing signal and the gate 44 returns counterclockwise under spring tension to .its quiescent state. The quiescent state is the orientation of the gate as depicted in the drawing.

in the event that no contents are detected, the solenoid 40 is not energized. The gate 44 therefore directs the envelope into the normal" receptacle 10.

Jam detector switches (notshown) are strategically located throughout the machine to stop the machine in the event of any improper flow of materials.

Photocell 52, which detects light rays from a source (not shown) is located immediately adjacent to gate 44 to monitor the passage of envelopes into the exception receptacle for the purpose of counting exceptions and providing information to the error detection circuitry described below.

Referring now to FIG. 3, there is shown in block diagram form the circuitry utilized with the mechanical structure of FIG. 1 for scanning, detecting and then sorting envelopes which have contents from those which do not have contents. Three signal channels are depicted, each of which is associated with a respective detector wheel 24, 25 and 26 (see FIG. 1).

As was discussed with respect to FIG. 1, the purpose of the detector wheels 24, 25 and 26 is to detect whether there are contents in an envelope. The

switches 28, 28' and 28" (FIG. 3) are set so that a certain thickness item can pass through without activating them. If a portion of the item passing through the detector wheels is thicker that the minimum setting of the switches, the latter will be activated.

Each

detector switch

28, 28 and 28" is connected to a respective detector flip-

flop

51, 55 and 58. When any detector switch is activated, it will set the associated flip-flop and will re-set the flip-flop when the detector switch is not activated.

The output of each flip-flop is fed to an associated

timer circuit

54, 56 and 59. The set side of the flip-flop initiates the timer circuit. The purpose of the timer is to determine the length of time that the detector switches 28, 28' or 28" are activated.

The output of the timer circuits 54, S6 and 59 are directed to

respective threshold detectors

53, 57 and 60. The

respective threshold detectors

53, 57 and 60, will have an output only if the timer has been activated for a specified period of time. Accordingly, the'length determine the time that the respective timers are activated. I

The threshold detector outputs are fed into

respective inverters

70, 71 and 72 and thence to a decoder 61. The latter operates tO 'dCCOdC I out of X, 2 out of X, or 3 out of X whereX is the number of detector switches, (i.e., three). In other words, the device shown in FIG. 3 can operate in three distinct modes as will be discussed in detail in a later part of the text.

In the I out of X mode, when the item activates one of the

detectors

28, 28' and 28" for a predetermined length of time, the detect flip-flop is set which in turn activates the solenoid 40 (see FIG. 1). The gate 44 steers the item into the exception" receptacle. If the item does not activate the detector switches 28, 28 and 28", the solenoid gate 44 is not activated by the detect flip-flop 62 and consequently the item is steered into the normal" receptacle.

An error detector circuit is also provided in the block diagram of FIG. 3. The error detector circuit assures that the following conditions take place:

a. those items which activate the detector switches 28, 28' and 28". for the predetermined length of time go into the exception" receptacle, and

b. those items which do not activate the detectors for the predetermined length of time go into the normal receptacle.

The machine is automatically stopped if the above conditions are not met.

The above conditions are met in the following manner. Whenever an item goes into the exception" bin, its presence is detected thereat (in a manner to be described in greater detail hereinafter) and the exception flip-flop is set. Furthermore, whenever the detect flip-flop 62 is set, this in turn sets the delay detect flipflop 67.

The output of the exception and delay detect

flipl'lops

63 and 67 are fed into an error compare circuit 64 in conjunction with a timing signal. The error compare circuit 64 is an AND-OR circuit which produces an output signal to set the stop flip-flop 65 and energize the stop solenoid 66, which turns the machine off when the conditions a and b are not met. Conversely, the AND-0R circuit does not produce an output signal to set the stop flip-flop 65 if the conditions a and b are met.

Referring briefly to FIG. 4, there is depicted in block diagram form, the arrangement for developing timing signals TF1 through TF7 utilized throughout the circuitry of FIG. 3. Furthermore, the activation of the pho'tocellsNo. '1 and No. 2 while aiding in the production of the various timing signals also respectively activate the total counter 68 and the exception counter 69.

Referring now to FIG. 5 and 5A, there is depicted the circuit schematic utilized in the

respective channel

1, 2 or 3 of FIG. 3. As is understood, each respective signal channel is associated with a respective detector wheel 24, 25 and 26 (see FIG. 1). Each detector wheel is coupled in the manner described in FIG. 1 to a

corresponding detector switch

28, 28 and 28" depicted in block form in' FIG. 3.

. Referring again to FIG. 5, switch 28 comprises a single-pole, doublethrow Micro Switch wherein the pole is grounded. In the quiescent state (i.e., the button is not depressed by the linkage in FIG. 1) the detector switch is in position B. The A and B output terminals of detector 28 are connected to the detector flip-flop circuit. The flip-flop comprises a combination of circuits known as a TTL or a TL circuit. T L circuits willbe utilized as basic logic building blocks throughout the ensuing discussion and therefore the operation will be reviewed for various terminal conditions.

The basic logic building block is made up of transistors T1, T2, T3, T4, T5 and T6. This building block is used for the following applications: I) to invert a signal, 2) to construct a flip-flop by utilizing two interconnected building blocks, 3) to decode signals, and 4) to perform logic. The operation of the building block circuit in general is as follows: The input requirements are that the emitters of TI must be either at zero voltage or at +3 volt level. The output (terminal D) which normally ties the emitter of T5 to the collector of T6 will be either at zero voltage or at +3 volts. When all emitters of T1 are at the +3 volt level the output (terminal D) is at zero volts. If any emitter of T1 is at zero volts, terminal D is at +3 volts. If we establish the logic notation that +3 volts is equal to a I and zero volts is equal to a 0 then this circuit is a NAND gate for l s and a NOR gate for 0s". For example, if all inputs are 1" the circuit inverts and gives a 0" output. If either of the inputs are 0" the circuit inverts and gives a l output. Tl can have as, many emitters as technology permits.

To explain the operation of the basic building block with more specificity, refer now to the lower building block or T'L circuit of the detector flip-flop in FIG. 5. Assume that any one or all input emitters are at zero potential (hereinafter referred to as L). The current I5 is established from source +V to ground via the resistor R6 and the base-emitter junction Bl-El. Therefore, since all of the current 15 is diverted through Bl-El, no current flows through Bl-Cl. Since no current flows through B2-E2, transistor T2 does not conduct. Also, since no current flows through T2, transistors T4 and T6 do not conduct.

Thecurrent i7 is established however through the PN junction B3.-E3 thereby turning on transistor T3. A portion of the emitter current of transistor T3 comprising its base and collector currents flows through resistor R8 to ground. The remainder flows through the base-emitter junction BS-ES turning on T5. The emitter current 110 of transistor T5 flows to ground via the distributed capacity Cd and leakage path. The collector current [9 flows to ground through the junction CS-ES and the distributed capacitance Cd. Current is conducted through transistor T5 until the capacitance Cd is charged up to approximately 3 volts (hereinafter referred to as H) after which the current i9 is terminated. The charge remains on the capacitance Cd (i.e., terminal D) until the conditions change at the input emitters. (i.e., E1 and B1 are both H.)

In summary, when at least one of the input emitters E1 or E1 is L, the output terminal D will be H.

Let us assume that both of the inputs of the basic building block are H. A current path cannot be established through either of the base-emitter junctions 81-51 and B1'El'. Therefore, the current i5 is diverted through the base-collector junction Bl-Cl and turns on the junction 82432 of transistor T2. The current l7 now flows through the collector-emitter junction C2-E2 of transistor T2. The emitter current of transistor T2 also now flows through the base-emitter 84-134 of transistor T4 and the base-emitter B6-E6of transistor T6. Transistors T4 and T6 are turned on and part of the emitter current of transistor T2 also flows through the collector-emitter of T4. The path of these currents is shown by the

currents

10, 11,13, and [6 in the upper portion of the detect flip-flop. Any external load current can now flow through the low impedance collector-emitter path C6-E6 so that the collector of T6 is at or ground potential.

It should be noted that very little current flows through the PN junction B3-E3 since this path is of a higher impedance than the path through transistors T2, T4 and T6. Accordingly, the PN junctions B3-E3 and BS-ES do not conduct and therefore transistors T3 and T are turned off.

In summary, when all of the inputs of the basic building block are H, the output terminal D is L.-

Reference will now be made to the operation of the detector flip-flop circuit. it should be observed that two basic building blocks (one above the other) are utilized for this purpose. However, the output of the upper circuit is modified (i.e., the emitter of Z5 and the collector of Z6 are split) to accommodate the operation of the following timer circuit.

in the quiescent state, the detector switch 28 is in the position B. Therefore, terminal D is H. Both inputs of transistor. 21 and H causing terminal C to become L.

The state of terminal C is fed back to one of the inputs circuit connectedto the output of the flip-flop as well as to the remaining circuitry.

Continuing with the discussion of the quiescent state of the circuitry, diodes D1 and D4 are forward biased thus discharging capacitor Ct and D2 is non-conducting. The current lll flows during the quiescent state from the supply +V to ground via resistor R12, diodes D1 and D4 and through the conducting transistor Z6. A current also flows through Z6 via resistors R11, R, and R and diode D4. Diode D2 and the base-emitter junctions of transistors T7 and T8 are also non-conducting. Therefore, the current [12 flows through the diode D3 and the base-emitter junction of transistor T8 from +V. Diode D3 and transistor T8 are in FIG. 5A. Transistor T8 conducts causing the junction G to be L.

'One of the inputs to the basic building block circuit T9 being L thereby causesjunction J to be H.

Referring to the detect flip-flop, its quiescent state is established by the momentary L signals TF5. or Clear applied to transistor T12. These signals cause terminal K to be L. This signal is in turn fed back to the input of T12 thereby keeping terminal M in a H condition and the detect flip-flop in its quiescent state. The stated conditions enable the diode D5 to be forward biased since, the anode is connected via resistor R13 to the positive supply +V and the cathode is L. When D5 is forward biased, D6 and transistor T1 1 are back biased. Therefore, the gate solenoid coil is not activated.

Let us now assume that one of the three detector switches 28 is activated by sensing contents in an envelope. In other words, let us assume that the system is to detect contents if only one out of three detector switches is activated. Accordingly, thedetector switch 28 is switched to the position A. The input emitter ell is therefore switched from H to L or ground causing terminal C to become H.This voltage switching at the terminal C is due to the turn-off of transistor Z6. Therefore, the current [11 through diode D4 is terminated. However, since the capacitor Ct was completely discharged by the turn-on of transistor Z6, the current Ill now flows (as shown by the dotted line) as a charging current. The current lll' also flows to ground to charge the capacitor Ct via the fixedresistor R and-the variable resistor R. It should be noted that by changing the value of the variable resistor R, the charging rate of capacitor Ct can be varied. Therefore, the charging of the capacitor Ct constitutes the initiating of a timer circuit. lf detector switch .28 is at ,position A long enough (i.e.,if contents are actually present in the envelope) capacitor Ct will charge to a valuewhich will reverse bias diode D1 thereby stopping the flow of current Ill through this path. Furthermore, when the capacitor Ct becomes fully charged, the current lll is also terminated. When capacitor Ct is,charged to a value to turn-off conduction through diode D1, it nevertheless has a value greater than the conducting voltage of diode D2, and the base-emitter junctions of transistors T7 and T8. If detector switch 28 returns to position B (i.e., if the seam of an envelope were being momentarily detected) capacitor Ct discharges through transistor Z6 which is turned on. The charging of capacitor Ct will begin over again when detector switch 28 returns to position A. It should be noted that the discharge time constant of Ct, through D4 and Z6 is very short; hence, whenever switch 28 is in position B, the timer circuit immediately becomes ready for a new timing sequence.

As discussed above, the purpose of the capacitor timer is to determine the length of time that the detector switch 28 is activated. Any item which activates the switch 28 will do so in accordance with the following relationship:

Time detector activated speed X length of item activating detector.

The time for the capacitor Ct to reach a steady state condition is determined by its RC time constant which is determined essentially by the value of the resistance R and R as well as that of the capacitor Ct. By changing the value of the. variable resistor R, the rate of charge on capacitor Ct and the RC time constant can be varied. Hence, assuming that the speed of the machine is constant for a given RC time constant, the length of the item in the envelope which activates the detector 28 will determine when the capacitor Ct will be charged to the value which will activate the threshold detector.

It should be observed that the use ofthe detector switch 28 in conjunction with the T L flip-flop circuit significantly improves this portion of the circuit operation since contact bounce does not affect circuit operation. Thus a bouncing switch is in an indeterminate position between terminals A and B. Bounce results from the fact that the grounded pole may bounce on terminal B, for example, since it is mechanically coupled to the detector wheel 24 (see FIG. 1) and, therefore any rough surface traversing the wheel 24 would be coupled to the switch 28. The flip-flop however will remain in a quiescent condition since the output C of the upper T L circuit will always be L, causing terminal D of the lower TL circuit to remain H. Therefore, even though terminal B is at some intermediate position the flip-flop comprising these two interconnected TL circuits will not alter its condition.

' If the switch 28 is in position A for a long enough period (e.g., the minimum distance of "3 inches) the charge on capacitor Ct causes the diode D2 and transistors T7 and T8'to conduct as discussed above. The conduction of current through the collectoremitter junctions of transistors T7 and T8 cause junction F to be at approximately ground potential or L.

The grounding switch SW2 is inserted in the circuit between diodes D1 and D2 so that transistors T7 and T8 remain in the off or quiescent state while permitting micrometer positions of the detector switch 28 (see FIG. 1).

As junction F goes to ground or L, the diode D3 and the base-emitter junction of transistor T8 become back biased and the junction Gswitches to H. Ac-

cordingly, the transistor T8 performs an inverting function.

When junction G switches terminal S of decoder gate T9 to the state H, the decoder output terminal J switches to L. The decoder is made of a number of basic building blocks hereinafter called decoder gates T9, T9A and T9X. The decoder determines the number and combination of detector switches required to simultaneously be in position A before allowing the detection process to continue. If each detector switch is to operate independently, or in thejone out of three mode, then each channel (see FIG. 1) will have its own decoder gate T9, T9A and T9X and the other inputs P-Q, P-Q', and P"-Q can be returned to +3 volts or H. In this particular arrangement, the corresponding J output terminals of these three decoders are connected to the respective input emitters of the basic building block comprising a portion of the detect flip-flop. The operation of the circuit is then as follows in accordance with our stated example. Since only detector switch 28 has detected thickness over the specified length, then all of the inputs are-H to decoder gate T9 and its output J is L. One of the inputs to the detect flip-flop being L causes its output terminal K to become H.

When the output K becomes H, diode D5 is non-conducting. This voltage switching causes diode D6 and thebase-emitter junction of transistor T11 to be forward biased. The emitter-collector junction of transistor T1 1 therefore conducts and allows current to flow from +V to ground via the solenoid gate coil. The gate axle 41 (see FIG. 1) therefore pivots so that the envelope with its contents has been routed to the exception receptacle.

It should be noted here that if detector switches 28' and 28" had also been activated in conjunction with switch 28, the results would have been the same so that decoding can be performed to satisfy the operating state of 1 out of X switches where X is three in the example under discussion. This results from the fact that only one of the input emitters of transistor T10 is required to become L for terminal .I( to become H. Consequently, if the output signals produced by decoder T9A and/or T9X are L because their inputs are all -H it will have no additional effect on the detect flip-flop. This results-from the operation of the basic building block circuit previously described.

For the condition of decoding for the 2 out of X mode, the following is provided. Q, Q and Q" are all returned toH'. It should be noted that the respective outputs of the inverters associated with

switches

28, 28 and 28" are identified as G, G and G. In order to detect the 2 out of X mode, the respective inputs to the decoder gates must have some combination of G, G and o". i

For example, G and G must be present at decoder gate T9; G and G" must be present at gate T9A and G and G must bepresent at gate T9X. Now the output .I of the respective decoder gates will go L when the inverter outputs of any two inverters are simultaneously not utilized. By connecting

channels

1, 2 and 3 in this manner to the decoder gate T9, all three signals to the input emitters must be H for the output terminal J to be L, which is required to activate the gate solenoid. In other words, the decoder connection as just described requires that each

detector switch

28, 28 and 28" scan and detect thickness over the required length before the gate solenoid will be activated. It can therefore be seen that the instant invention can operate in three modes of operation by a mere modificationof the decoder. 4

After the item or envelope has traversed 'the scanning mechanism and has been gated to either the normal or the "exception" receptacle, the system is ready to scan the next item. Before this can be accomplished the detector and detect flipflops must be re- I set.

The detector flip-flops are automatically re-set as soon as the detector switch 28 returns to terminal B. When the detector switch 28 returns to terminal B, all input emitters of Z1 to the basic building block are H and thus, as previously described, the detector flip-flop is returned to the quiescent state. Terminal J of the decoder now switches back to H. In the event that three decoders are utilized, three of the four input emitters to transistor T will be H. The fourth input emitter of T10 is also H since the timing signal TPS will be L, causing terminal M. to be H. Hence, the detect flip-flop is also returned to the quiescent state so that the next envelope can be scanned for contents.

Referring again to FIG. 3, there is further disclosed an arrangement for monitoring or assuring that the scanned item enters the proper receptacle. This monitoring is accomplished by utilizing an error compare circuit 64 which observes the state of the exception flip-flop 63 and the delay detect flip-flop 67. The delay detect flip-flop 67 is set whenever the detect flip-flop 62 is set or when contents are detected in an envelope thereby activating the solenoid gate 44. The exception flip-flop 63 is set by the timing signal T6. The timing signal T6 is produced by the activation of a photocell located near the exception receptacle (see FIG. 1). The error compare circuit 64-samples the state of flipflops 63 and 67 at time TF3.

The purpose and necessity of the error detection circuitis two fold:

a. that an item which has activated the detector switches for a predetermined time goes into the exception" receptacle.

b. that items not activating the detector switches for a predetermined time do not needlessly go into the two TL basic building block circuits in the manner previously described.

In the quiescent state, the ohtputls ACC nd ACC L and H, respectively. The input signals TF4 anglP6 are both H- in the quie scent or'r e-set state. TP6 is generated whenever the envelope or item enters the The delay detect flip-flop .67 (see FIG. 3 is con- 'nected to the output of the detect flip-flop 62 and the purpose of the delay flip-flop is to store the information as to whether the envelope had contents or not. The detect flip-flop 62 after performing the detect function (i.e., after being set) must be cleared or re-set to the quiescent state in order to be ready for the next envelope. to be scarm. The detect flip-flop is re-set by the timing signal TF5. The delay detect flip-flop therefore retains the information which was stored in the dctect flip-flop after the latter has been re-set.

In the quiescent state of the delay detect flip-flop, which is shown in detail in FIG. Sb, the terminal characteristics DDET (Delay Detect) and DDET are L and H, respectively. The delay detect flip-flop is re t to the above stated conditions by the timing signal TP4 or the ,Clear signal which are both L upon being generated.

One of the input signals to the upper T'L circuit of the delay detect flip-flop is provided by another TL circuit which is utilized as a NAND gate. In the quiescent state of this building block, the timing signal TP2 is L as is the signal DET from the detect flip-flop. Accordingly, the output terminal of the NAND gate, which is connected to one of the input emitters of the upper building block of the delay detect flip-flop, is H. The second input emitter of the upper building block is also H as above stated since the output terminalDDET is connected thereto.

The NAND gate compares theoutput of the detect flip-flop information (i.e., DET) at the time TP2. If the into the error compare circuit 64. The error compare circuit comprises in essence an AND-OR inverter circuit. The AND-OR is essentially a TL basic'building block circuit and slightly modified to handle the AND OR logic function. This is shown in detail in FIG. 5D.

In the quiescent state of the delay detect and exception flip-flops, the output signals ACC and AC C are L andH,'respectively. In-additiorr, the signals DDET and DDET are Land H, respectively. This causes the error out terminal to bev H at time TP3. I. i

In the quiescent state of the AND -QR error compar circuit, the terminals ERR and ERR are L and H, respectively. This results from the above states H output of the ERROR OUT terminal of error compare cir cuit as well as the fact that the Clear signal had gone L and caused the ERR terminal signal to be H. Since the ERROR OUT and the ERR terminals are both H, the ERR signal is L. When the ERR signal is L'it does not allow the STOP solenoid 66 (see FIG. 3) to de-energize and cause the machine to turn off.

As above discussed, four conditions are constantly monitored during the course of operation of; the machine, namely:

l. envelope has contents and goes into the exception bin.

2. envelope has no contents and goes into the normal bin.

3. envelope has contents and goes into the "normal bin. I 4. envelope has no contents and goes into the exception bin. The operation of this function will be discussed in greater detail below.

Let us first assume the conditions wherein the envelope has contents and goes into the exception bin. For the exception flip-flop, terminal ACC is H (i.e.,

T6 is L because the photocell is activated) and ACC is" L, whereas for the delay detect flip-flop, the terminal DDET is H (since the detect flip-flop was set) and DDET is L. The error compare function is performed at time TF3 which signal is H. Under the conditions just stated at time TF3, the AND condition (all emitters H) is not met for either transistor gates T13 or T14 so that the ERROR OUT terminal is H. Since the ERR terminal remains in a L condition, the stop solenoid is not de-energized indicating that contents have been detected and they have entered the proper receptacle.

The second condition above stated is monitored in the following way. If the envelope has no contents, the terminals of the exception flip-flop are such that ACC is L (since Tfi is H) and A C Gis H. Furthermore, the terminal DDET and DDET of the delay detect flipflop are respectively L (since the detect flip-flop is reset) and H. Therefore, at time TF3, the AND condition is not met for either transistor gate T13 or T14 and the ERROR OUT terminal is H. Therefore, the ERR terminal is L and the stop solenoid is not de-energized indicating that the envelope has no contents and has been placed in the normal or correct receptacle.

The third condition that is monitored is that the envelope has contents and goes into the normal receptacle. The output terminal Ag is L (since the photocell is n'ot activated) and ACC is H, whereas the output terminal DDET is H and DDET is L. At time TF3, the AND condition is met for transistor gate T13 and the ERROR OUT terminal goes L. This causes terminal ERR to become H thereby de-energizing the stop solenoid. The system therefore is turned off so that the malfunction can be investigated and corrected.

Under the fourth condition that is mon i to red, the exception" flip-flop terminals'ACC and ACC are H and L, respectively, since the envelope has activated the second photoceli even though it has no contents. However, the terminals DDET and DDET are L and H, respectively, since no contents have been detected in the envelope by the detector switch.

In, view of the above states signals which are developed at time TF3 the AND condition is met for gate T14 (i.e., all its emitters are H) so that the ERROR 921 terminal goes L. Hence, the terminals ERR and ERR are H and L, respectively, thereby de-energizing the stop solenoid and stopping all further motion so that the error can be corrected.

The error override switch is utilized to maintain the error stop flip-flop in the re-set state thus preventing the machine from stopping due to error. In other words, a L signal is continuously applied to the lower TL circuit of the error stop flip-flop thus preventing the machine from stopping due to error. This is used during machine maintenance.

Returning now to FIG. 4, there is shown in block diagram form the timing signals TF1-TF7 which are developed by the timing chain for use throughout the above described logic. The'timing chain signals are initiated when the leading edge of the scanned envelope passes by the first photocell 36 (see FIG. 1) thereby interrupting a light beam. The timing signal TF1 is generated by this action. The signal TF2 is produced by the trailing edge of the envelope passing by the photocell thereby allowing the light beam to be reinstated. The counter 68 for inventory purposes is initiated each time that the leading edge of an envelope.

turns off the light beam impinging on a phototransistor.

Timing pulses TF3-TF5 are initiated by the timing signal TF2 and are delayed to occur at specific times after TF2. Timing pulse TF6 is generated by the leading edge of the envelope passing by the second photocell 52 located adjacent to gate 44 (see FIG. 1) and signal TF7 is generated by the envelopes trailing edge. This is accomplished in the same way with respect to photocell 52 as the pulses TF1 and TF2 were generated with respectto photocell 36.

Referring now to FIG. 6, the actual signals utilized for timing purposes are depicted in relationship to one another. The timing chart is based on the envelope traveling 1 inch/ 10 milliseconds past the first photocell 36. The envelope travels 2'inches/ 10 milliseconds past photocell 52. The timing chart is based on a 6 inchenvelope although any envelope between 6 and 9 inches may be used without changing any timing or physical dimensions. Furthermore, the machine can be changed physically to accept any size envelope. The timing chart is based on detecting an item 3 inches long with a 20 millisecond minimum separation between successive envelopes.

In FIG. 6, line a, there is shown the 60 milliseconds time span that is produced as each 6 inch envelope passes before the first photocell 36 and the 20 millisecond separation between successive envelopes. The timing signals TF1 (line 0) and TF2 (line d) are produced by the leading and trailing edge of photocell No.1 signal (line a).

Assuming that the envelope has contents, then 30 milliseconds after the turn-off of the signal produced by photocell No. 1, the envelope is transported past photocell No. 2 to generate the signal shown on line b. It should be noted that the time span of this latter signal is only 30.milliseconds since the speed of the envelope moves past photocell No. 2twice as fast as it moves past photocell No. 1. The timing pulses TF6 (line h) and TF7 (line i) are produced by the leading and trailing edge of photocell No. 2 signal (line b).

The timing pulses TF3, TF4 and TF5 are initiated by TF2 and are delayed to occur at'specific times after TF2. Accordingly, it can be seen that seven timing pulses are generated; however all seven are not used in the instant embodiment.

Referring to line j of FIG. 6, there is depicted the time period during which the detect flip-flop 62 (see FIG. 1) is set. The delay detect flip-flop 67 is shown on line k as being set in overlapping relationship with the setting of the detect flip-flop.

The setting of exception flip-flop 63 (see FIG. 1) is depicted on line I and overlaps the setting of the delay detect flip-flop.

Referring now to FIG. 7, the additional circuitry to develop the timing signals TF1-TF2, including their inversions, aswell as timing pulses TF3-TF5 are shown. Thus, as the envelope 32 passes before the light to break the beam directed to the phototransistor Fl, a H signal is developed at its collector electrode. This is the signal shown on line a of FIG. 6. This H signal forward biases the diode as well as the base-emitter junction of transistor T15. Therefore, the collector of transistor T15 goes L. This L signal is differentiated by the capacitor and resistance connected to the base electrode of transistor T16. The negative portion of the differentiated signal is applied to the base of transistor Tl6 which causes the latter to assume the high impedance state and its collector terminal becomes H and therefore, the timing signal TF1 is developed. By applying this positive signal through an inverter, a negative signal is developed which becomes the negative timing signal TF1. TF1 and W are developed during the leading edge of the signal at the collector ofTl.

In like manner, the signals TF2 and TF2 are developed. Thus, the negative going pulse developed at the collector of transistor T15 is inverted to a positive going pulse and then differentiated by the series RC circuit connected to the base of transistor T17. In all other aspects, the operation is the same as that described above for the development of TF1 and TF1. TF2 and w are developed during the trailing edge of the signal at the collector ofT15.

An electro-mechanical total counter is also activated each time that a positive pulse is generated at the collector of phototransistor F1. The output of phototransistor F1 is inverted twice and differentiated. Therefore, when phototransistor F1 is turned off, transistors T18 and T19 are turned on to activate the total counter. Accordingly, every time that an item passes the phototransistor Fl, the total counter is increased by one. The total counter is used for inventory purposes. The length of time that transistors T18 and T19 are on is determined by the time constant of the differentiating network.

Three additional timing pulses, TP3-TF5 are generated by circuitry which in turn is initiated by timing pulse TF2. Thus, timing pulse TF2 is fed into three different delay flops or one-shot multivibrators only one of which is shown in FIG. 7. As is well understood, a one-shot multivibrator is a multivibrator which has a preferred stable state. Upon being triggered, the multivibrator switches to the opposite-state for a fixed time which is determined by the discharge time constant of an RC network.

In the quiescent state, transistor T20 is non-conducting whereas transistor T21 is conducting. The applica-,- tion of the positive going pulse TF2 makes'transistor T20 conduct and transistor T21 non-conducting. The time constant of' RlCl and the value of sources +V1 and +V2 determine the'length of time that transistor T21 is turned off. The circuit then returns to its normal state. The pulse is then fed into a differentiating network. After the pulse is differentiated, the trailing edge produces a negative going pulse which turns off transistor T22, generating the timing-pulse TF3. By using two similar delay flop circuits and respectively applying the signalTFZ to their input terminals, the timing pulses TF4 and TF5 are developed. Therefore, by adjusting the value of RICI, the timing of the respective delay flop circuits can be varied to produce the varied timing signals TF3-TF5 shown in sequence in FIG. 6. The timing signals TF4 and T F5 are obtained by inverting TF4 and TF5 by means not shown.

The timing signals TF6-TF7, including W and T F7,

and the exception counter are respectively generated and activated only when the second phototransistor 52 (see FIG. 1) is activated and the pulse shown in FIG. 6, line b, is produced. The circuitry utilized toproduce the timing signals TF6,W6 ,'TF7, and Wis identical to that just described to generate TFL-Tfi, TF2 and IF2 as shown in FIG. 7. Also, the same circuitry is utilized to activate the exception counter 69 (see FIG. 4).

Assume firstly that the item has no contents. Therefore, after the phototransistor No. l is activated (FIG. 6, line a) and pulses TFl-TFS are generated, the item is transported to the normal" receptacle. Since the detect flip-flop was not set by the no contents item, the pulse TF5 produced by pulse TF2 is ineffectual and hence the circuitry is in a condition to perform the next cycle of operation.

Assuming that the item has contents, the detect flipflop 62 (see FIG. 3) is set for the time period shown in FIG. 6, line j. It will be recalled that it was stated in the instant embodiment that detection .was based on a three inch contents within a 6 inch envelope. By referring to the timing chart of FIG. 6 and in particular to line j, it can be readily seen that it is immaterial as to where the contents are located in the envelope. Thus, if the contents are in the extreme forward part of the envelope as it is transported through the micro-scanner, the output signal of the detect flip-flop will be as shown in line j. The detect flip-flop is set for a period of time A B such that the detect flip-flop signal in conjunction with the timing pulse TF2 causes the setting of the delay detect flip-flop 67.

In the event that the 3 inch contents are positioned in the back of the. envelope, then the detect flip-flop would be set for the time period B (see dotted line) only. The delay detect flip-flop will again be set by the combination of signals TF2 and the output of the detect flip-flop. The detect flip-flop is re-set by means of timing pulse TF5.

As previously discussed, the detection of contents in an envelope activates phototransistor No. 2 which'in turn generates'timing signals TF6 and TF7.

The exception flip-flop (FIG. 6, line I) is set at the time when pulse TF6 occurs (i.e.,by TR). The outputs of the delay detect flip-flop (line k) and the exception flip-flop (line I) in conjunction with the pulse occurring at time TF3 are fed into the error compare circuit 64 (see FIG. 3) in order to monitor whether the envelope is routed to the correct exception receptacle.

The exception and delay detect flip-flops are re-set at time TF4 (i.e., by TF4). It should be noted that pulses TP! and TP7 although generated by the circuitry disclosed are not utilized in the present embodiment.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows.

We claim:

1. A sorting device comprising:

a. a package means for carrying contents, said package means having a varying thickness;

b. a scanning means for detecting contents as well as the lack of contents within said package, said package means moving relative to said scanning means at a pre-determined speed;

c. means coupled to said scanning means to produce a first signal determined by said speed and the length of said relative movement to indicate the presence of said contents, said coupled means producing a second signal determined by said speed and relative movement to indicate the absence of contents;

d. means to receive said first signal for diverting said package with contents into a first receptacle, means-to receive said second signal for diverting said package without contents into a second receptacle.

2. The sorting device in accordance with claim 1 wherein said scanning means includes pre-set switching means to pass a minimum thickness package,

whereas, said pre-set means upon exceeding said minimum thickness producing a switching signal.

3. The sorting device in accordance with claim 2 wherein said coupled means includes a resistancecapacitance timing circuit.

4. The sorting device in accordance with claim 3 wherein said switching means is connected to a flip-flop circuit,

said switching signal causing said flip-flop circuit to beactivated to a set condition,

the set condition of said flip-flop initiating said timing circuit, whereas the termination of said switching signal causes said flip-flop and said timing circuit to be re-set.

5. The sorting device in accordance with claim 2 wherein said scanning means further includes a roller means which passes over a discrete area of said package means,

said roller means activating said switching device to produce said switching signal when said package means exceeds said pre-set minimum thickness for a pre-determined length.

6. The sorting device in accordance with claim 5 wherein error checking means are connected to said coupled means,

said error checking means generating an error signal when said package with contents enters said second receptacle and said package means without contents enters said first receptacle.

7. The sorting device in accordance with claim 6 wherein a circuit breaker means is coupled to said error checking means,

said error signal when applied to said circuit breaker means causing saidsorting device to become inoperative.

8. The sortingdevice in accordance with claim 7 wherein a first photocell is located near said scannin means and a second photocell is located near said firs receptacle.

9. The sorting device in accordance with claim 8 wherein first and second counting means are coupled to said respective first and second photocells,

said first counting means determining the number of package means being scanned and said second counting means determining the number of package means entering said first receptacle.

10. A sorting device comprising:

a. a package means for carrying contents;

b. a plurality of scanning means for detecting said contents as well as the lack of contents within said package, said last mentioned means scanning discrete areas of said package means;

c. means coupled to said scanning means to generate respective first signals to indicate that contents are present in said discrete areas, said coupled means producing respective second signals to indicate the lack of contents in said discrete areas;

d. means for decoding said respective first signals, said decoding means decoding X out of Y wherein X represents any number other than zero of first signals which are generated and Y represents the total number of scanning means;

e. means for diverting said envelope into a first receptacle after said decoding means has decoded X out of Y. said means for diverting directing said package into a second receptacle when all of the signals decoded by said decoder means are said second signals.

Claims

1. A sorting device comprising: a. a package means for carrying contents, said package means having a varying thickness; b. a scanning means for detecting contents as well as the lack of contents within said package, said package means moving relative to said scanning means at a pre-determined speed; c. means coupled to said scanning means to produce a first signal determined by said speed and the length of said relative movement to indicate the presence of said contents, said coupled means producing a second signal determined by said speed and relative movement to indicate the absence of contents; d. means to receive said first signal for diverting said package with contents into a first receptacle, means to receive said second signal for diverting said package without contents into a second receptacle.

2. The sorting device in accordance with claim 1 wherein said scanning means includes pre-set switching means to pass a minimum thickness package, whereas, said pre-set means upon exceeding said minimum thickness producing a switching signal.

3. The sorting device in accordance with claim 2 wherein said coupled means includes a resistance-capacitance timing circuit.

4. The sorting device in accordance with claim 3 wherein said switching means is connected to a flip-flop circuit, said switching signal causing said flip-flop circuit to be activated to a set condition, the set condition of said flip-flop initiating said timing circuit, whereas the termination of said switching signal causes said flip-flop and said timing circuit to be re-set.

5. The sorting device in accordance with claim 2 wherein said scanning means further includes a roller means which passes over a discrete area of said package means, said roller means activating said switching device to produce said switching signal when said package means exceeds said pre-set minimum thickness for a pre-determined length.

6. The sorting device in accordance with claim 5 wherein error checking means are connected to said coupled means, said error checking means generating an error signal when said package with contents enters said second receptacle and said package means without contents enters said first receptacle.

7. The sortinG device in accordance with claim 6 wherein a circuit breaker means is coupled to said error checking means, said error signal when applied to said circuit breaker means causing said sorting device to become inoperative.

8. The sorting device in accordance with claim 7 wherein a first photocell is located near said scanning means and a second photocell is located near said first receptacle.

9. The sorting device in accordance with claim 8 wherein first and second counting means are coupled to said respective first and second photocells, said first counting means determining the number of package means being scanned and said second counting means determining the number of package means entering said first receptacle.

10. A sorting device comprising: a. a package means for carrying contents; b. a plurality of scanning means for detecting said contents as well as the lack of contents within said package, said last mentioned means scanning discrete areas of said package means; c. means coupled to said scanning means to generate respective first signals to indicate that contents are present in said discrete areas, said coupled means producing respective second signals to indicate the lack of contents in said discrete areas; d. means for decoding said respective first signals, said decoding means decoding X out of Y wherein X represents any number other than zero of first signals which are generated and Y represents the total number of scanning means; e. means for diverting said envelope into a first receptacle after said decoding means has decoded X out of Y, said means for diverting directing said package into a second receptacle when all of the signals decoded by said decoder means are said second signals.