US3651460A - Fixed rate integral controller - Google Patents

Fixed rate integral controller Download PDF

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Publication number
US3651460A
US3651460A US39431A US3651460DA US3651460A US 3651460 A US3651460 A US 3651460A US 39431 A US39431 A US 39431A US 3651460D A US3651460D A US 3651460DA US 3651460 A US3651460 A US 3651460A
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Prior art keywords
counter
gate
input signal
pulses
commensurate
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US39431A
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Edward F Gebelein Jr
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Colt Industries Operating Corp
Colt Industries Inc
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Chandler Evans Inc
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Assigned to COLT INDUSTRIES OPERATING CORPORATION, A CORP. OF DE reassignment COLT INDUSTRIES OPERATING CORPORATION, A CORP. OF DE MERGER (SEE DOCUMENT FOR DETAILS). EFFECTIVE ON 10/24/1986 DELAWARE Assignors: CHANDLER EVANS INC., A DE CORP., HOLLEY BOWLING GREEN INC., A DE CORP., LEWIS ENGINEERING COMPANY, THE, A CT CORP.
Assigned to COLT INDUSTRIES INC., A PA CORP. reassignment COLT INDUSTRIES INC., A PA CORP. MERGER (SEE DOCUMENT FOR DETAILS). EFFECTIVE ON 10/28/1986 PENNSYLVANIA Assignors: CENTRAL MOLONEY INC., A DE CORP., COLT INDUSTRIES OPERATING CORP., A DE CORP.
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B1/00—Comparing elements, i.e. elements for effecting comparison directly or indirectly between a desired value and existing or anticipated values
    • G05B1/01—Comparing elements, i.e. elements for effecting comparison directly or indirectly between a desired value and existing or anticipated values electric
    • G05B1/03—Comparing elements, i.e. elements for effecting comparison directly or indirectly between a desired value and existing or anticipated values electric for comparing digital signals
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
    • H02P23/16—Controlling the angular speed of one shaft

Definitions

  • Decision gates suitably interconnected with the counter detect when numbers commensurate with the upper and lower limits of the nominal range of the monitored parameter are counted and, depending upon the number loaded into the counter during each pulse commensurate with the input signal, the decision gates will control the generation of steady-state output signals which may be employed to control a mechanism which adjusts the monitored parameter in the proper direction.
  • DIGITAL COUNTER OGIC (DECISION GATES) TRIM DJ in DOW DRIVE ACTUATOR PAIENTEnIIIIRzI I972 3.651.460
  • the present invention relates to the control of machinery and particularly to controlling the speed of rotating mechanisms. More specifically, the present invention is directed to fixed rate integral speed controllers. Accordingly, the general objects of the present invention are to provide novel and improved methods and apparatus of such character.
  • the typical prior art electronic or electromechanical speed controller requires, for operation, the computation of actual speed and the comparison of the thus computed speed with a reference speed in order to enable the further computation of speed error. That is, prior art speed controllers measure speed and then compute error. As is well know, when speed is computed the computer must be able to determine the speed to some desired resolution and within some desired range. Accordingly, since both speed and speed error have a large number of possible states, the accuracy of the controller must necessarily be limited in order to accommodate all these possible states. Further, while the typical prior art controller is an analog device, it is well know that digital control systems provide for a greater degree of accuracy than analog systems.
  • the present invention overcomes the above and other limitations and disadvantages of the prior art by providing a constant integral rate control which may be utilized as an electronic discrete controller.
  • the present invention employs digital logic techniques and circuitry to achieve, within the I frequency clock signal into a counter.
  • the clock signal is commensurate with the desired speed of the mechanism being controlled and in a preferred embodiment may be adjusted to a number of preselected frequencies.
  • the counter is interrogated and filled at the same time and, through logic circuitry properly interconnected with certain stages of the counter, the actual speed is classified in one of three states; above, below or within a predetermined deadband.
  • the logic circuitry will command appropriate energization of the actuator means which controls the speed of the mechanism. In this manner, a correction signal is generated only when a significant error exists and the control signal will be of sufficient magnitude to cause appropriate correction.
  • the actual speed of the mechanism being controlled may be sampled several times a second and each sampling compared with the preselected or set speed to determine if correction is necessary.
  • the actuator on the mechanism being controlled may be operated at a rate which is independent of the sampling and which will permit the system to remain stable throughout its operating range.
  • Accuracy of the present invention is limited only by hysteresis and other nonlinearities in the mechanism being controlled and its existing hydromechanical control system and the present invention may be reprogrammed quickly and easily.
  • the present invention affords maximum dependability through elimination of all low reliability components and may be made of small size and light weight through the elimination of such devices as analog to digital converters.
  • digital circuit techniques have been employed in the present invention, the invention may take advantage of integrated circuit developments and thus is virtually unaffected by changes in ambient temperature, pressure, altitude, humidity and vibration.
  • FIG. 1 is a functional block diagram of a preferred embodiment of the invention.
  • FIG. 2 is a circuit block diagram of the embodiment of FIG. 1.
  • FIG. 1 a functional block diagram of a preferred embodiment of the present invention is presented. Presuming for purposes of explanation that the invention is employed to control the speed of rotating member such as a combustion engine, an input signal, as generated by a tachometer or other suitable speed sensor device coupled to the rotating member, is delivered to a signal conditioning circuit 10.
  • the output of circuit 10 will be a pulse train having pulse widths commensurate with the actual instantaneous speed of the rotating member.
  • the pulses from circuit 10 will be applied as the gating control input to an AND-gate 12.
  • the second input to gate 12 comprises a train of high-frequency pulses from a speed reference or clock pulse source 14.
  • Speed command signals may be applied to clock pulse source 14 if the particular apparatus being controlled is to be operated at a plurality of precisely controlled speeds.
  • the means whereby the speed reference signal frequency may be varied will be briefly discussed below.
  • this signal is inversely proportional to speed.
  • this signal inversely proportional to speed is applied to gate 12 and is thus used to gate the constant frequency clock pulses from reference source 14 into a digital counter 16.
  • the speed reference or clock pulses are thus gated into the counter for a period of time which is inversely proportional to the actual instantaneous speed of the apparatus being controlled.
  • the clock pulses will fill the counter to a number which is proportional to the reciprocal of actual speed.
  • the counting and subsequent clearing of counter 16 will occur with each cycle of the input signal and the speed of the rotating member will thus be sampled many times per second.
  • counter 16 As counter 16 is filling, it is interrogated by a logic circuit 18 which, as will be described in detail below in the discussion of FIG. 2, comprises plurality of decision gates. It is significant to note that the counter 16 is interrogated and filled at the same time. Thus, rather than measuring speed and then computing error as has been the practice in the prior art, the present invention immediately establishes both the presence and sign of the error, if any error is present, with respect to a predetermined deadband.
  • the decision gates comprising logic unit 18 are connected to counter 16 in such a way that each of the gates will detect a predetermined binary member. The numbers thus detected will correspond to a specific speed or speeds.
  • the logic circuit will detect numbers corresponding to the end points of a permissible speed range; there being an acceptable error or deadband between the detected speeds.
  • the actual speed is immediately classified in one of three states; above, below, or within a predetermined deadband; and it becomes unnecessary to actually compute speed or speed error.
  • the classifying of speed in one of three states may be contrasted to the prior art technique where speed error is actually computed.
  • a down trim gate 20, and up trim gate 22 or neither gate will be enabled by a signal provided by the logic unit 18.
  • an actuator drive signal will be passed from circuit 24 to a suitable electromechanical control mechanism.
  • the signals passed by gates 20 and 22 may be applied to solenoids which move the fuel flow regulating mechanism respectively to the increased and decreased fuel flow conditions to thereby adjust the speed of the rotating member.
  • FIG. 2 is a circuit block diagram of a preferred embodiment of the invention shown in the form of a functional diagram in FIG. 1.
  • the signal conditioning circuit 10 which has the speed sensor device output signal applied as an input thereto, comprises a series connected filter 40, squaring circuit 42, and averaging circuit 44.
  • the purpose of the signal conditioning circuit is to convert the cyclic and variable frequency input speed signal to a waveform suitable for controlling gate 12.
  • Filter 40 will typically be a low pass filter which removes noise from the input signal.
  • the output of filter 40 is applied to squarer circuit 42.
  • Circuit 42 will comprise a high gain amplifier which is permitted to go into saturation in response to the filtered input signal thereby generating a substantially square-wave signal.
  • Averaging circuit 44 will typically comprise a bistable multivibrator which is responsive to the trailing edges of the applied square wave signal. Since the averaging circuit 42 is actuated by a nonsymmetricalbut continuous signal, it is considered desirable to employ an averaging circuit in order to provide a signal commensurate with the sensed quantity; the averaged signal having precisely a 50 percent duty cycle.
  • circuit 42 is not perfectly square thereby requiring averaging in the interest of system accuracy.
  • the output of signal conditioning circuit 10 is also applied to a one shot multivibrator 46.
  • Astable multivibrator 46 is switched by the trailing edge of each pulse provided by conditioning circuit 10.
  • the output pulses provided by multivibrator 46 are of short duration and, in the manner to be described below, control the transfer of speed error state information to the up" and down" trim gates.
  • Multivibrator 46 may, therefore, be considered a transfer strobe pulse source.
  • multivibrator 46 also causes the generation of negative pulses which are applied to the reset input of counter 16 thereby causing the counter to be resequenced before the next sampling period as determined by the application of the next succeeding positive pulse to gate 12 from conditioning circuit 10.
  • the speed reference signal generation circuit 14 will comprise a crystal oscillator and suitable pulse shaping circuitry whereby the output of the oscillator is a series of pulses at a preselected frequency substantially above the highest expected input signal frequency.
  • FIG. 1 depicts a speed command input to the speed reference circuit 14. This input has been omitted from FIG. 2 in the interest of facilitating understanding of the invention.
  • the apparatus being controlled may be operated at a plurality of speeds and these speeds may be remotely selected by changing the frequency of the speed reference input to gate 12 by several well known techniques.
  • the count points of counter 16 may be varied to achieve the same result.
  • counter 16 comprised an ll-bit binary counter.
  • a typical I l-bit counter which may be employed in the present invention comprises three Signetics Corporation type SS828I binary counters suitably interconnected.
  • a pair of NAND gates, typically Signetics type S84 l 7 50 and 52 are connected to preselected stages of counter 16. As a result of the selection of which counter stages are connected to the inputs of gates 50 and 52, these gates respectively sense when the counter has been filled short of or beyond a preselected number. As shown in FIG.
  • counter 50 will sense a lower number than counter 52 and the difference between the numbers sensed by counters 52 and 50 will comprise a deadband.
  • the high" I speed decision gate 50 sensed the binary number while the low" speed decision gate 52-was responsive to the binary number 78. If the number loaded into counter 16 during each sampling of the input speed signal falls within the deadband, the region between 75 and 78 in the example given, the speed of the apparatus being controlled will be sufficiently close'to the desired speed so that corrective action will be deemed to be unnecessary.
  • Gates 50 and 52 will, in the manner known in the art, provide output signals which are respectively applied to the count inputs of binary gates 54 and 56.
  • Gates 54 and 56 may comprise Signetics type S8424A RST multivibrators.
  • multivibrator 54 Upon receipt of a signal from gate 50, multivibrator 54 will be switched whereby the binary one" initially applied to the first input of transfer ANDgate 60 will be switched to the first input of transfer AND-gate 62.
  • multivibrator 56 upon receipt of a signal from gate 52, multivibrator 56 will be switched whereby the binary one initially applied at a first input of transfer AND-gate 64 will be switched to the first input of transfer AND-gate 66.
  • Gates 54 and 56 are reset, after each sampling of the input signal by a negative reset pulse generated by differentiator 68 and simultaneously applied to the reset inputs of both multivibrators.
  • Differentiator 68 is responsive to the trailing edge of the pulse provided by astable multivibrator 46.
  • the output pulses from multivibrator 46 are also employed as transfer or strobe pulses and thus are applied as second inputs to transfer gates 60, 62, 64, and 66. Signals passed by either of transfer gates 60 and 62, in response to a strobe pulse, are applied to the opposite inputs of down bistable multivibrator 70. Signals similarly passed by transfer gates 64 and 66 are applied to the opposite inputs of up bistable multivibrator 72.
  • a first output of down" multivibrator 70 is applied as the control input to the down trim gate 20.
  • the first output of up multivibrator 72 is employed as the control signal for the up" trim gate 22.
  • the other inputs to gates and 22 are connected to actuator drive or modulator circuit 24 which may be a source of variable frequency, variable duty cycle modulation. Depending on which of gates 20 or 22 is enabled, the energizing signal from circuit 24 will be applied to the speed adjustment actuator by one of driver amplifiers 74 and 76. It is to be understood that modulator 24 and gates 20 and 22 are not necessary for operation and the outputs of multivibrators 70 and 72 may be applied directly to respective driver amplifiers 74 and 76.
  • modulator 24 does not comprise part of the present invention and will not be described herein.
  • modulator 24 may be considered to be any device which will provide an electrical signal suitable, after amplification, for energizing the electromechanical actuator connected to the outputs of amplifiers 74 and 76.
  • counter 16 will count a number of pulses sufficient to enable gate 50 but insufficient to enable gate 52 during each sampling of the input signal applied to signal conditioning circuit 10. Accordingly, multivibrator 54 will be switched while multivibrator 56 will remain in its initial or reset condition. Accordingly, the one signal normally applied from multivibrator 54 to the input of transfer gate 60 will be switched to the input of transfer gate 62. However, the one signal normally applied by multivibrator 56 to the input of transfer gate 64 will not be switched to the input of transfer gate 66. it is significant that the switching of one or both of multivibrators 54 and 56, as results from the filling of counter 16, occurs simultaneously with the sampling of the input signal.
  • multivibrator 46 Immediately upon termination of each period of sampling of the input, multivibrator 46 will generate a transfer pulse which will cause the signals applied at the inputs of transfer gates 60, 62, 64, and 66 to be applied to the up and down multivibrators 72 and 70.
  • no signal or a binary zero will be applied to the input to multivibrator 70 which is connected to gate 60 while a one will be applied to the multivibrator input which is connected to gate 62.
  • a binary zero will be transferred to the input of multivibrator 72 which is connected to gate 64 while a one will be coupled to the multivibrator input which is connected to gate 66.
  • Multivibrator 70 will initially have a one appearing at the output connected to gate 20 whereas multivibrator 72 will normally have a zero appearing at its output which is connected to gate 22. Accordingly, upon delivery of a strobe pulse to the transfer gates, multivibrator 70 will be caused to switch whereas multivibrator 72 will remain in its initial state. The switching of multivibrator 70 will cause a zero to be applied to trim gate 20 and thus this gate will not be enabled. Since a zero" initially appeared at the output of multivibrator 72 which is connected to gate 22, gate 22 will similarly not be enabled. Accordingly, neither of gates 20 or 22 will pass a drive signal and the speed of the mechanism being controlled will not be adjusted.
  • both of gates 50 and 52 When the speed of the mechanism being controlled is too low, both of gates 50 and 52 will be enabled by the filling of counter 16 to a number greater than that to which gate 50 is responsive. Accordingly, both of multivibrators 54 and 56 will be switched thereby resulting in application of a zero to the input to transfer gate 60, a one to the input of transfer gate 62, a zero to the input of transfer gate 64 and a one" to the input of transfer gate 66.
  • the generation of a strobe pulse by multivibrator 46 will transfer the signals applied at the inputs of transfer gates 60 and 64 to the inputs of multivibrator 70 thereby causing multivibrator 72 to change state and provide a zero" at the output connected to down" trim gate 20.
  • the signals appearing at the inputs to transfer gates 64 and 66 will be coupled to the inputs to multivibrator 72 causing multivibrator 72 to change state and one to appear at the output which is connected to up trim gate 22.
  • Gate 22 will thus be enabled and will pass drive signals from modulator 24 to amplifier 76 and thereby causing the speed of the mechanism being controlled to be increased.
  • multivibrators 54 and 56 upon termination of the strobe pulse provided by one shot multivibrator 46, through the action of differentiator 68, multivibrators 54 and 56 will return to their initial states. However, since there will be no signal applied by multivibrator 46 to the transfer gates until termination of the next sampling period, multivibrators 70 and 72 will remain in their last commanded state and corrective action will continue if necessary. However, if the last sampling of the input signal produced an indication that the speed of the mechanism being controlled was within the established deadband, multivibrator 72 will remain in its initial state whereas multivibrator 70 will remain in the switched state; in this condition both multivibrators providing a binary zero" output at the terminal which is connected to their respective trim gates.
  • Control signal generating means comprising:
  • gate means connected between said clock pulse source and said counter means, said gate means being responsive to an input signal commensurate with the instantaneous value of a monitored parameter for controlling the delivery of clock pulses to said counter means;
  • control signal generating means connected to said classifying means and responsive to said classification signals for providing output signals which may be employed to adjust the monitored parameter.
  • said classifying means comprises:
  • first decision gate means interconnected with said counter means for detecting the filling of said counter to a first number
  • second decision gate means interconnected with said counter means for detecting the filling of said counter means to a second number which is greater than said first number, the range of the monitored parameter commensurate with the interval between said first and second numbers defining a normal range of values of the monitored parameter.
  • said classifying means means connected to said signal conditioning means and further comprises: responsive to the pulses provided thereby for generating first bistable circuit means responsive to the detection of transfer pulses at the termination of each pulse commensaid first and second numbers by said decision gate means surfite W the input g and for providing steady-state output signals commensurate means for applying said transfer pulses to said transfer gate with the classification of the input signal; and means whereby said steady-state signals commensurate transfer gate means for delivering said steady-state signals th th Classification of the input signal will be applied to to said control signal generating means.
  • said control signal generating means immediately follow-v 4.
  • the apparatus of claim 3 further comprising: s each classification of the input signalsignal conditioning means responsive to said input signals 'f apparatus of F 5 wherein Said comm] Signal commensurate with the monitored parameter for generatgenerating means compnsesi second bistable circuit means.
  • pulses having widths proportional to the instantaneous value of the monitored parameter, said pulses being applied to said gate means and controlling the delivery of clock pulses to said counter means. 5.
  • the apparatus of claim 4 further comprising:

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Power Engineering (AREA)
  • Feedback Control In General (AREA)
  • Control Of Velocity Or Acceleration (AREA)
  • Combined Controls Of Internal Combustion Engines (AREA)
  • Electrical Control Of Air Or Fuel Supplied To Internal-Combustion Engine (AREA)
US39431A 1970-05-21 1970-05-21 Fixed rate integral controller Expired - Lifetime US3651460A (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3724433A (en) * 1971-08-13 1973-04-03 Ambac Ind Engine governor system with signal-loss protection and controlled oscillator circuit suitable for use therein
US3757750A (en) * 1970-09-17 1973-09-11 Diesel Kiki Co Electronic governor for injection-type internal combustion engines
US3766895A (en) * 1971-08-13 1973-10-23 Ambac Ind Electric speed control system and more-than-two-state phase detector suitable for use therein
US3889647A (en) * 1973-07-02 1975-06-17 Bendix Corp Speed governor for an engine having an electronic fuel injection system
US4321460A (en) * 1977-01-03 1982-03-23 Lanier Business Products, Inc. Digital control apparatus
US4393845A (en) * 1978-04-03 1983-07-19 The Bendix Corporation Means for improving the efficiency of an internal combustion engine
US6674962B2 (en) 2002-01-29 2004-01-06 Siemens Vdo Automotive, Inc. Limited-pool random frequency for DC brush motor low frequency PWM speed control
US20080000478A1 (en) * 2006-07-01 2008-01-03 Draeger Medical Ag & Co. Kg Device for supplying a patient with breathing gas and process for regulating a respirator

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2816879C2 (de) * 1978-04-18 1986-11-20 German Ing.(Grad.) 8060 Dachau Grimm Schaltung zur Frequenzregelung in elektrischen Energieverteilungsnetzen
GB2136164B (en) * 1983-03-01 1987-03-25 Aisin Seiki Automobile speed control systems
EP0236685B1 (de) * 1986-02-11 1991-09-04 Studer Revox Ag Verfahren und Vorrichtung zur Regelung der Drehzahl eines Elektromotors im Vierquadrantenbetrieb

Citations (8)

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US3176208A (en) * 1962-07-02 1965-03-30 North American Aviation Inc Phase locking control device
US3246249A (en) * 1962-03-09 1966-04-12 Philco Corp Programmable digital high and low limit detector system
US3281607A (en) * 1963-08-29 1966-10-25 Int Resistance Co Nand nor logic circuit for use in a binary comparator
US3290647A (en) * 1962-05-01 1966-12-06 Sperry Rand Corp Within-limits comparator
US3420989A (en) * 1965-07-16 1969-01-07 Us Navy Synchronizer for digital counters
US3437894A (en) * 1966-03-29 1969-04-08 Us Navy Multiple speed servomechanism drive system for positioning an antenna in direct response to digital signals
US3465326A (en) * 1965-07-26 1969-09-02 Ici Ltd Speed detection
US3525044A (en) * 1968-02-28 1970-08-18 Vapor Corp Digital speed and control system

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3246249A (en) * 1962-03-09 1966-04-12 Philco Corp Programmable digital high and low limit detector system
US3290647A (en) * 1962-05-01 1966-12-06 Sperry Rand Corp Within-limits comparator
US3176208A (en) * 1962-07-02 1965-03-30 North American Aviation Inc Phase locking control device
US3281607A (en) * 1963-08-29 1966-10-25 Int Resistance Co Nand nor logic circuit for use in a binary comparator
US3420989A (en) * 1965-07-16 1969-01-07 Us Navy Synchronizer for digital counters
US3465326A (en) * 1965-07-26 1969-09-02 Ici Ltd Speed detection
US3437894A (en) * 1966-03-29 1969-04-08 Us Navy Multiple speed servomechanism drive system for positioning an antenna in direct response to digital signals
US3525044A (en) * 1968-02-28 1970-08-18 Vapor Corp Digital speed and control system

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3757750A (en) * 1970-09-17 1973-09-11 Diesel Kiki Co Electronic governor for injection-type internal combustion engines
US3724433A (en) * 1971-08-13 1973-04-03 Ambac Ind Engine governor system with signal-loss protection and controlled oscillator circuit suitable for use therein
US3766895A (en) * 1971-08-13 1973-10-23 Ambac Ind Electric speed control system and more-than-two-state phase detector suitable for use therein
US3889647A (en) * 1973-07-02 1975-06-17 Bendix Corp Speed governor for an engine having an electronic fuel injection system
US4321460A (en) * 1977-01-03 1982-03-23 Lanier Business Products, Inc. Digital control apparatus
US4393845A (en) * 1978-04-03 1983-07-19 The Bendix Corporation Means for improving the efficiency of an internal combustion engine
US6674962B2 (en) 2002-01-29 2004-01-06 Siemens Vdo Automotive, Inc. Limited-pool random frequency for DC brush motor low frequency PWM speed control
US20080000478A1 (en) * 2006-07-01 2008-01-03 Draeger Medical Ag & Co. Kg Device for supplying a patient with breathing gas and process for regulating a respirator
US8627820B2 (en) * 2006-07-01 2014-01-14 Draeger Medical Gmbh Device for supplying a patient with breathing gas and process for regulating a respirator

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CA936258A (en) 1973-10-30
GB1309711A (en) 1973-03-14
DE2125093A1 (it) 1971-12-02

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Owner name: COLT INDUSTRIES INC., A PA CORP.

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Effective date: 19870706