US3651460A

US3651460A - Fixed rate integral controller

Info

Publication number: US3651460A
Application number: US39431A
Authority: US
Inventors: Edward F Gebelein Jr
Original assignee: Chandler Evans Inc
Current assignee: Colt Industries Operating Corp; Colt Industries Inc
Priority date: 1970-05-21
Filing date: 1970-05-21
Publication date: 1972-03-21
Anticipated expiration: 1989-03-21
Also published as: DE2125093A1; GB1309711A; CA936258A

Abstract

A control signal generator which employs digital logic techniques to classify an input signal commensurate with a monitored parameter as being either above, below, or within a nominal range of the parameter. The input signal is converted to a pulse train and the pulses are employed to gate high-frequency clock pulses to a counter which is interrogated and filled at the same time. Decision gates suitably interconnected with the counter detect when numbers commensurate with the upper and lower limits of the nominal range of the monitored parameter are counted and, depending upon the number loaded into the counter during each pulse commensurate with the input signal, the decision gates will control the generation of steady-state output signals which may be employed to control a mechanism which adjusts the monitored parameter in the proper direction.

Description

United States Patent Gebelein, Jr.

[451 Mar. 21, 1972 FIXED RATE INTEGRAL CONTROLLER Inventor:

Conn.

Chandler Evans Inc., West Hartford, Conn.

Filed: May 21, 1970 App1.No.: 39,431

Assignee:

References Cited UNITED STATES PATENTS 3/1965 Gifft ..318/3l4 9/1969 Weir et al. ....324/16l 4/1966 Boscia ....328/l46 Joseph et al.. .....340/146.2 Gariano .340/l46.2 X Sapp ..235/92 llllll REFERENCE SPEED COMMAND Edward F. Gebelein, Jr., Harwinton,

3,525,044 8/1970 Richmond. 3,437,894 4/1969 ABSTRACT Primary Examiner-Malcolm A. Morrison Assistant Examiner-Edward .1. Wise Attorney-Fishman and Van Kirk ..324/ 173 Pohl ..318/603 A control signal generator which employs digital logic techniques to classify an input signal commensurate with a monitored parameter as being either above, below, or within a nominal range of the parameter. The input signal is converted to a pulse train and the pulses are employed to gate high frequency clock pulses to a counter which is interrogated and filled at the same time. Decision gates suitably interconnected with the counter detect when numbers commensurate with the upper and lower limits of the nominal range of the monitored parameter are counted and, depending upon the number loaded into the counter during each pulse commensurate with the input signal, the decision gates will control the generation of steady-state output signals which may be employed to control a mechanism which adjusts the monitored parameter in the proper direction.

DIGITAL COUNTER OGIC (DECISION GATES) TRIM DJ in DOW DRIVE ACTUATOR PAIENTEnIIIIRzI I972 3.651.460

sum 1 [IF 2 FIG. I

CONDITIONING I2 r 6 DIGITAL COUNTER SPEED l8 REFERENCE LOGIC (DECISION GATES) SPEED COMMAND 20f DOWN TRIM I f ACTUATOR "uP" DRIVE TRIM INVENTOR EDWARD F GEBELEIN,JR.

ATTORNEYS FIXED RATE INTEGRAL CONTROLLER BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the control of machinery and particularly to controlling the speed of rotating mechanisms. More specifically, the present invention is directed to fixed rate integral speed controllers. Accordingly, the general objects of the present invention are to provide novel and improved methods and apparatus of such character.

2. Description of the Prior Art While not limited thereto in its utility, the present invention has been found to be particularly desirable for employment as a fixed rate integral controller with deadband for incorporation in apparatus which exercises control over the speed of acombustion engine through adjustment of the means for delivering fuel to the engine. Speed controllers or governors are, of course, well known in the art. The present invention relates to an electronic control and the present discussion will accordingly be limited to circuitry which, in response to input signals commensurate with actual and desired speed, provides an output which will operate an actuator in the appropriate direction to null any speed error which may be present. The present discussion will also be restricted to devices which maintain one or a plurality of preselected speeds regardless of load changes imposed upon the mechanism being controlled.

The typical prior art electronic or electromechanical speed controller requires, for operation, the computation of actual speed and the comparison of the thus computed speed with a reference speed in order to enable the further computation of speed error. That is, prior art speed controllers measure speed and then compute error. As is well know, when speed is computed the computer must be able to determine the speed to some desired resolution and within some desired range. Accordingly, since both speed and speed error have a large number of possible states, the accuracy of the controller must necessarily be limited in order to accommodate all these possible states. Further, while the typical prior art controller is an analog device, it is well know that digital control systems provide for a greater degree of accuracy than analog systems. While it may be noted there have been prior art speed controllers which were either digital in nature or provided a digital output signal, such prior art systems universally employed analog to digital converters and thus were characterized by relatively great expense, size, weight, and complexity incident to and inherent in the use of such converters.

Additional disadvantages of prior art electronic controllers are many and diverse. Perhaps the most significant of these additional limitations is the inability to retrofit existing systems, and particularly those presently employing electromechanical controls, with high speed and high reliability electronic control systems. A further limitation is the inability to rapidly and easily reprogram prior art controls whereby the single or plural preselected reference speeds may be varied without major circuit changes and/or without operating on the actual mechanism being controlled.

Considered from the standpoint of control system reliability, prior art devices have not achieved the maximum dependability inherent in elimination of low reliability components such as otentiometers, trimmers, variable capacitors and other moving parts. Similarly, the typical prior art electrical speed controller does not provide for operation of the actuator means, which is coupled to the mechanism being controlled, in a normally deenergized mode and thus the prior art controllers have had a tendency to reduce the life expectancy of these actuators.

SUMMARY OF THE INVENTION The present invention overcomes the above and other limitations and disadvantages of the prior art by providing a constant integral rate control which may be utilized as an electronic discrete controller. The present invention employs digital logic techniques and circuitry to achieve, within the I frequency clock signal into a counter. The clock signal is commensurate with the desired speed of the mechanism being controlled and in a preferred embodiment may be adjusted to a number of preselected frequencies. The counter is interrogated and filled at the same time and, through logic circuitry properly interconnected with certain stages of the counter, the actual speed is classified in one of three states; above, below or within a predetermined deadband. Depending upon the classification of the speed, the logic circuitry will command appropriate energization of the actuator means which controls the speed of the mechanism. In this manner, a correction signal is generated only when a significant error exists and the control signal will be of sufficient magnitude to cause appropriate correction.

Also in accordance with the present invention, the actual speed of the mechanism being controlled may be sampled several times a second and each sampling compared with the preselected or set speed to determine if correction is necessary. Through the use of appropriate logic circuitry, the actuator on the mechanism being controlled may be operated at a rate which is independent of the sampling and which will permit the system to remain stable throughout its operating range. Accuracy of the present invention is limited only by hysteresis and other nonlinearities in the mechanism being controlled and its existing hydromechanical control system and the present invention may be reprogrammed quickly and easily. It is also to be noted that the present invention affords maximum dependability through elimination of all low reliability components and may be made of small size and light weight through the elimination of such devices as analog to digital converters. It is also to be noted that, since digital circuit techniques have been employed in the present invention, the invention may take advantage of integrated circuit developments and thus is virtually unaffected by changes in ambient temperature, pressure, altitude, humidity and vibration.

BRIEF DESCRIPTION OF THE DRAWING The present invention may be better understood and its numerous objects and advantages will become apparent to those skilledin the art by reference to the accompanying drawing wherein like reference numerals refer to like elements in the two figures and wherein:

FIG. 1 is a functional block diagram of a preferred embodiment of the invention; and

FIG. 2 is a circuit block diagram of the embodiment of FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENT With reference now to FIG. 1, a functional block diagram of a preferred embodiment of the present invention is presented. Presuming for purposes of explanation that the invention is employed to control the speed of rotating member such as a combustion engine, an input signal, as generated by a tachometer or other suitable speed sensor device coupled to the rotating member, is delivered to a signal conditioning circuit 10. The output of circuit 10 will be a pulse train having pulse widths commensurate with the actual instantaneous speed of the rotating member. The pulses from circuit 10 will be applied as the gating control input to an AND-gate 12. The second input to gate 12 comprises a train of high-frequency pulses from a speed reference or clock pulse source 14. Speed command signals may be applied to clock pulse source 14 if the particular apparatus being controlled is to be operated at a plurality of precisely controlled speeds. The means whereby the speed reference signal frequency may be varied will be briefly discussed below.

Since the input signal from the speed sensing device is cyclic in nature and of a frequency proportional to actual speed of the apparatus to be controlled, the period of this signal is inversely proportional to speed. As noted above, and after suitable conditioning in circuit 10, this signal inversely proportional to speed is applied to gate 12 and is thus used to gate the constant frequency clock pulses from reference source 14 into a digital counter 16. The speed reference or clock pulses are thus gated into the counter for a period of time which is inversely proportional to the actual instantaneous speed of the apparatus being controlled. The clock pulses will fill the counter to a number which is proportional to the reciprocal of actual speed. The counting and subsequent clearing of counter 16 will occur with each cycle of the input signal and the speed of the rotating member will thus be sampled many times per second.

As counter 16 is filling, it is interrogated by a logic circuit 18 which, as will be described in detail below in the discussion of FIG. 2, comprises plurality of decision gates. It is significant to note that the counter 16 is interrogated and filled at the same time. Thus, rather than measuring speed and then computing error as has been the practice in the prior art, the present invention immediately establishes both the presence and sign of the error, if any error is present, with respect to a predetermined deadband. In order to accomplish the foregoing, the decision gates comprising logic unit 18 are connected to counter 16 in such a way that each of the gates will detect a predetermined binary member. The numbers thus detected will correspond to a specific speed or speeds. Considering the condition where the device being controlled is to be held at a single speed only regardless of the conditions imposed on the rotating member, such as load changes, the logic circuit will detect numbers corresponding to the end points of a permissible speed range; there being an acceptable error or deadband between the detected speeds. Thus, through interaction of the counter 16 and logic circuitry 18, the actual speed is immediately classified in one of three states; above, below, or within a predetermined deadband; and it becomes unnecessary to actually compute speed or speed error. The classifying of speed in one of three states may be contrasted to the prior art technique where speed error is actually computed.

Depending upon the classification of the speed, a down trim gate 20, and up trim gate 22 or neither gate will be enabled by a signal provided by the logic unit 18. When one of

gates

20 and 22 is enabled, an actuator drive signal will be passed from circuit 24 to a suitable electromechanical control mechanism. For example, the signals passed by

gates

20 and 22 may be applied to solenoids which move the fuel flow regulating mechanism respectively to the increased and decreased fuel flow conditions to thereby adjust the speed of the rotating member.

FIG. 2 is a circuit block diagram of a preferred embodiment of the invention shown in the form of a functional diagram in FIG. 1. The signal conditioning circuit 10, which has the speed sensor device output signal applied as an input thereto, comprises a series connected filter 40, squaring circuit 42, and averaging circuit 44. As indicated above, the purpose of the signal conditioning circuit is to convert the cyclic and variable frequency input speed signal to a waveform suitable for controlling gate 12. Filter 40 will typically be a low pass filter which removes noise from the input signal. The output of filter 40 is applied to squarer circuit 42. Circuit 42 will comprise a high gain amplifier which is permitted to go into saturation in response to the filtered input signal thereby generating a substantially square-wave signal. The train of square pulses appearing at the output of circuit 42 is applied to an averaging circuit 44. Averaging circuit 44 will typically comprise a bistable multivibrator which is responsive to the trailing edges of the applied square wave signal. Since the averaging circuit 42 is actuated by a nonsymmetricalbut continuous signal, it is considered desirable to employ an averaging circuit in order to provide a signal commensurate with the sensed quantity; the averaged signal having precisely a 50 percent duty cycle.

Restated, the signal applied to circuit 42 is not perfectly square thereby requiring averaging in the interest of system accuracy.

In addition to being applied as the control input to AND- gate 12, the output of signal conditioning circuit 10 is also applied to a one shot multivibrator 46. Astable multivibrator 46 is switched by the trailing edge of each pulse provided by conditioning circuit 10. The output pulses provided by multivibrator 46 are of short duration and, in the manner to be described below, control the transfer of speed error state information to the up" and down" trim gates. Multivibrator 46 may, therefore, be considered a transfer strobe pulse source. Through the action of inverter 48, multivibrator 46 also causes the generation of negative pulses which are applied to the reset input of counter 16 thereby causing the counter to be resequenced before the next sampling period as determined by the application of the next succeeding positive pulse to gate 12 from conditioning circuit 10.

In the interest of precision operation, the speed reference signal generation circuit 14 will comprise a crystal oscillator and suitable pulse shaping circuitry whereby the output of the oscillator is a series of pulses at a preselected frequency substantially above the highest expected input signal frequency. It is to be noted that FIG. 1 depicts a speed command input to the speed reference circuit 14. This input has been omitted from FIG. 2 in the interest of facilitating understanding of the invention. It is, however, to be noted that the apparatus being controlled may be operated at a plurality of speeds and these speeds may be remotely selected by changing the frequency of the speed reference input to gate 12 by several well known techniques. Thus, for example, it is possible to employ either a plurality of crystal oscillators or a variable frequency oscillator; the output frequency in either case being adjustable by means well known in the art. Alternatively, the count points of counter 16 may be varied to achieve the same result.

As noted above in the discussion of FIG. 1, signals from speed conditioning circuit 10 enable gate 12 thereby permitting the-speed reference or clock pulses from crystal oscillator 14 to be loaded into counter 16. In one operative embodiment of the present invention, counter 16 comprised an ll-bit binary counter. A typical I l-bit counter which may be employed in the present invention comprises three Signetics Corporation type SS828I binary counters suitably interconnected. A pair of NAND gates, typically Signetics type S84 l 7 50 and 52 are connected to preselected stages of counter 16. As a result of the selection of which counter stages are connected to the inputs of

gates

50 and 52, these gates respectively sense when the counter has been filled short of or beyond a preselected number. As shown in FIG. 2, counter 50 will sense a lower number than counter 52 and the difference between the numbers sensed by

counters

52 and 50 will comprise a deadband. In one embodiment of the invention, the high" I speed decision gate 50 sensed the binary number while the low" speed decision gate 52-was responsive to the binary number 78. If the number loaded into counter 16 during each sampling of the input speed signal falls within the deadband, the region between 75 and 78 in the example given, the speed of the apparatus being controlled will be sufficiently close'to the desired speed so that corrective action will be deemed to be unnecessary.

Gates

50 and 52 will, in the manner known in the art, provide output signals which are respectively applied to the count inputs of

binary gates

54 and 56.

Gates

54 and 56 may comprise Signetics type S8424A RST multivibrators. Upon receipt of a signal from gate 50, multivibrator 54 will be switched whereby the binary one" initially applied to the first input of transfer ANDgate 60 will be switched to the first input of transfer AND-gate 62. Similarly, upon receipt of a signal from gate 52, multivibrator 56 will be switched whereby the binary one initially applied at a first input of transfer AND-gate 64 will be switched to the first input of transfer AND-gate 66.

Gates

54 and 56 are reset, after each sampling of the input signal by a negative reset pulse generated by differentiator 68 and simultaneously applied to the reset inputs of both multivibrators. Differentiator 68 is responsive to the trailing edge of the pulse provided by astable multivibrator 46.

As noted above, the output pulses from multivibrator 46 are also employed as transfer or strobe pulses and thus are applied as second inputs to transfer

gates

60, 62, 64, and 66. Signals passed by either of

transfer gates

60 and 62, in response to a strobe pulse, are applied to the opposite inputs of down bistable multivibrator 70. Signals similarly passed by

transfer gates

64 and 66 are applied to the opposite inputs of up bistable multivibrator 72.

A first output of down" multivibrator 70 is applied as the control input to the down trim gate 20. The first output of up multivibrator 72 is employed as the control signal for the up" trim gate 22. The other inputs to gates and 22 are connected to actuator drive or modulator circuit 24 which may be a source of variable frequency, variable duty cycle modulation. Depending on which of

gates

20 or 22 is enabled, the energizing signal from circuit 24 will be applied to the speed adjustment actuator by one of

driver amplifiers

74 and 76. It is to be understood that modulator 24 and

gates

20 and 22 are not necessary for operation and the outputs of multivibrators 70 and 72 may be applied directly to

respective driver amplifiers

74 and 76. It is also to be understood that the circuitry of modulator 24 does not comprise part of the present invention and will not be described herein. Thus, for purposes of this disclosure, modulator 24 may be considered to be any device which will provide an electrical signal suitable, after amplification, for energizing the electromechanical actuator connected to the outputs of

amplifiers

74 and 76.

ln operation, considering first the condition where the speed of the mechanism being controlled is within acceptable limits, counter 16 will count a number of pulses sufficient to enable gate 50 but insufficient to enable gate 52 during each sampling of the input signal applied to signal conditioning circuit 10. Accordingly, multivibrator 54 will be switched while multivibrator 56 will remain in its initial or reset condition. Accordingly, the one signal normally applied from multivibrator 54 to the input of transfer gate 60 will be switched to the input of transfer gate 62. However, the one signal normally applied by multivibrator 56 to the input of transfer gate 64 will not be switched to the input of transfer gate 66. it is significant that the switching of one or both of

multivibrators

54 and 56, as results from the filling of counter 16, occurs simultaneously with the sampling of the input signal. Immediately upon termination of each period of sampling of the input, multivibrator 46 will generate a transfer pulse which will cause the signals applied at the inputs of

transfer gates

60, 62, 64, and 66 to be applied to the up and down multivibrators 72 and 70. in the condition being described where there is no significant speed error, no signal or a binary zero will be applied to the input to multivibrator 70 which is connected to gate 60 while a one will be applied to the multivibrator input which is connected to gate 62. Similarly, a binary zero will be transferred to the input of multivibrator 72 which is connected to gate 64 while a one will be coupled to the multivibrator input which is connected to gate 66. Multivibrator 70 will initially have a one appearing at the output connected to gate 20 whereas multivibrator 72 will normally have a zero appearing at its output which is connected to gate 22. Accordingly, upon delivery of a strobe pulse to the transfer gates, multivibrator 70 will be caused to switch whereas multivibrator 72 will remain in its initial state. The switching of multivibrator 70 will cause a zero to be applied to trim gate 20 and thus this gate will not be enabled. Since a zero" initially appeared at the output of multivibrator 72 which is connected to gate 22, gate 22 will similarly not be enabled. Accordingly, neither of

gates

20 or 22 will pass a drive signal and the speed of the mechanism being controlled will not be adjusted.

When neither of the

gates

50 and 52 is enabled, thus indicating that the speed of the mechanism being controlled is too high, the initial conditions as discussed above will be maintained and an enabling one will be applied to gate 20 from the output of multivibrator 70. Gate 20 will accordingly pass signals from modulator 24 to down driver amplifier 74.

When the speed of the mechanism being controlled is too low, both of

gates

50 and 52 will be enabled by the filling of counter 16 to a number greater than that to which gate 50 is responsive. Accordingly, both of

multivibrators

54 and 56 will be switched thereby resulting in application of a zero to the input to transfer gate 60, a one to the input of transfer gate 62, a zero to the input of transfer gate 64 and a one" to the input of transfer gate 66. In the manner described above in the discussion of the deadband condition, the generation of a strobe pulse by multivibrator 46 will transfer the signals applied at the inputs of

transfer gates

60 and 64 to the inputs of multivibrator 70 thereby causing multivibrator 72 to change state and provide a zero" at the output connected to down" trim gate 20. Similarly, the signals appearing at the inputs to transfer

gates

64 and 66 will be coupled to the inputs to multivibrator 72 causing multivibrator 72 to change state and one to appear at the output which is connected to up trim gate 22. Gate 22 will thus be enabled and will pass drive signals from modulator 24 to amplifier 76 and thereby causing the speed of the mechanism being controlled to be increased.

It is to be noted that upon termination of the strobe pulse provided by one shot multivibrator 46, through the action of differentiator 68,

multivibrators

54 and 56 will return to their initial states. However, since there will be no signal applied by multivibrator 46 to the transfer gates until termination of the next sampling period, multivibrators 70 and 72 will remain in their last commanded state and corrective action will continue if necessary. However, if the last sampling of the input signal produced an indication that the speed of the mechanism being controlled was within the established deadband, multivibrator 72 will remain in its initial state whereas multivibrator 70 will remain in the switched state; in this condition both multivibrators providing a binary zero" output at the terminal which is connected to their respective trim gates.

While a preferred embodiment has been shown and described, various modifications and substitutions may be made thereto without departing from the spirit and scope of the present invention. Accordingly, it is to be understood that the present invention has been described by way of illustration rather than limitation.

What is claimed is:

1. Control signal generating means comprising:

a source of clock pulses;

counter means;

gate means connected between said clock pulse source and said counter means, said gate means being responsive to an input signal commensurate with the instantaneous value of a monitored parameter for controlling the delivery of clock pulses to said counter means;

means connected to said counter means and responsive to the number of clock pulses counted thereby during the periods said gate means is enabled by an input signal for classifying said input signal with respect to a preselected value of the monitored parameter, said classifying means providing output signals commensurate with the classification of the input signal; and

control signal generating means connected to said classifying means and responsive to said classification signals for providing output signals which may be employed to adjust the monitored parameter.

2. The apparatus of claim 1 wherein said classifying means comprises:

first decision gate means interconnected with said counter means for detecting the filling of said counter to a first number; and

second decision gate means interconnected with said counter means for detecting the filling of said counter means to a second number which is greater than said first number, the range of the monitored parameter commensurate with the interval between said first and second numbers defining a normal range of values of the monitored parameter.

7 8 3. The apparatus of claim 2 wherein said classifying means means connected to said signal conditioning means and further comprises: responsive to the pulses provided thereby for generating first bistable circuit means responsive to the detection of transfer pulses at the termination of each pulse commensaid first and second numbers by said decision gate means surfite W the input g and for providing steady-state output signals commensurate means for applying said transfer pulses to said transfer gate with the classification of the input signal; and means whereby said steady-state signals commensurate transfer gate means for delivering said steady-state signals th th Classification of the input signal will be applied to to said control signal generating means. said control signal generating means immediately follow-v 4. The apparatus of claim 3 further comprising: s each classification of the input signalsignal conditioning means responsive to said input signals 'f apparatus of F 5 wherein Said comm] Signal commensurate with the monitored parameter for generatgenerating means compnsesi second bistable circuit means.

7. The apparatus of claim 6 further comprising:

means responsive to said transfer pulses for resetting said l5 counter means and said first bistable circuit means.

ing pulses having widths proportional to the instantaneous value of the monitored parameter, said pulses being applied to said gate means and controlling the delivery of clock pulses to said counter means. 5. The apparatus of claim 4 further comprising:

Claims

1. Control signal generating means comprising: a source of clock pulses; counter means; gate means connected between said clock pulse source and said counter means, said gate means being responsive to an input signal commensurate with the instantaneous value of a monitored parameter for controlling the delivery of clock pulses to said counter means; means connected to said counter means and responsive to the number of clock pulses counted thereby during the periods said gate means is enabled by an input signal for classifying said input signal with respect to a preselected value of the monitored parameter, said classifying means providing output signals commensurate with the classification of the input signal; and control signal generating means connected to said classifying means and responsive to said classification signals for providing output signals which may be employed to adjust the monitored parameter.

2. The apparatus of claim 1 wherein said classifying means comprises: first decision gate means interconnected with said counter means for detecting the filling of said counter to a first number; and second decision gate means interconnected with said counter means for detecting the filling of said counter means to a second number which is greater than said first number, the range of the monitored parameter commensurate with the interval between said first and second numbers defining a normal range of values of the monitored parameter.

3. The apparatus of claim 2 wherein said classifying means further comprises: first bistable circuit means responsive to the detection of said first and second numbers by said decision gate means for providing steady-state output signals commensurate with the classification of the input signal; and transfer gate means for delivering said steady-state signals to said control signal generating means.

4. The apparatus of claim 3 further comprising: signal conditioning means responsive to said input signals commensurate with the monitored parameter for generating pulses having widths proportional to the instantaneous value of the monitored parameter, said pulses being applied to said gate means and controlling the delivery of cloCk pulses to said counter means.

5. The apparatus of claim 4 further comprising: means connected to said signal conditioning means and responsive to the pulses provided thereby for generating transfer pulses at the termination of each pulse commensurate with the input signal; and means for applying said transfer pulses to said transfer gate means whereby said steady-state signals commensurate with the classification of the input signal will be applied to said control signal generating means immediately following each classification of the input signal.

6. The apparatus of claim 5 wherein said control signal generating means comprises: second bistable circuit means.

7. The apparatus of claim 6 further comprising: means responsive to said transfer pulses for resetting said counter means and said first bistable circuit means.