US3638214A - Vector generator - Google Patents

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US3638214A
US3638214A US5229A US3638214DA US3638214A US 3638214 A US3638214 A US 3638214A US 5229 A US5229 A US 5229A US 3638214D A US3638214D A US 3638214DA US 3638214 A US3638214 A US 3638214A
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signal
waves
binary
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Howard Mulder Scott
Carl Rutherford Corson
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RCA Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/08—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam directly tracing characters, the information to be displayed controlling the deflection and the intensity as a function of time in two spatial co-ordinates, e.g. according to a cartesian co-ordinate system

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  • Registers store the binary words, and gates "340/324 6323933 respond to the stored digits for controlling a plurality of l 5 8] Fie'ld 1 5/1 8 switches which select for each digit one of the complementary "I 179/15 ramp waves or the direct-current levels, depending on whether or not a digit has changed value during the preceding 56] References Cited time interval.
  • a sum wave is obtained for each component of l the vector by adding the selected waves with weights depen- UNITED STATES PATENTS dent on the power of two represented by a particular digit.
  • the sum waves serve as deflection waveforms for the respec- Larrowe A five deflection means of [he cathode-ray tube. 3,533,096 10/1970 Bouchard ..340/324 A 3,500,332 3/1970 Vosbury ..340/324 A 8 Claims, 5 Drawing Figures X HOQIZONTHL DEFLEt'T/UA/ REG/5W5 cnzcu/"rs O 2 tr M f U l l i P & a 10 ...a t Molt. 5Tfl/ZT Q REFERENCE VOLTAGE ExEcurE mm: E RAMP GENE apron.
  • Terminal displays are becoming increasingly important in computer and data processing systems. An important feature present in many of these displays is the capability to generate vectors.
  • vector generators are known in the art, each with its own good and bad features. Certain ones generate a vector in a constant time whereas others are generated at a constant velocity. In a constant time system, vectors of different length are generated in the same amount of time which results in vectors of different length having different brightness. In a constant velocity system, since a vector is generated in a time dependent on its length, all vectors are substantially drawn at equal brightness.
  • Means for concurrently producing four waves, namely first and second direct-current levels, a first ramp extending from the first to the second level, and a second ramp extending from the second level to the first level.
  • first and second direct-current levels namely first and second direct-current levels
  • first ramp extending from the first to the second level
  • second ramp extending from the second level to the first level.
  • Means responsive to the signals select for each such signal one of the four waves, depending upon the value of the binary digit represented by the signal and whether or not it has changed value during the preceding time interval.
  • a sum signal is obtained for each group of signals by adding, with different weights, the selected waves corresponding to each such group ofsignals.
  • FIG. 1 is a block diagram of a preferred form of the invention
  • FIG. 2 is a schematic and block diagram which includes a more detailed showing of the reference voltage and sawtooth generator and horizontal deflection circuits of FIG. 1;
  • FIG. 3 illustrates waveforms present in the circuit of FIG. 2
  • FIG. 4 is a block diagram which includes a more detailed showing of the vector velocity control circuit of FIG. 1;
  • FIG. 5 is a block diagram which includes a more detailed showing of the gates in the vector velocity control circuit of FIG. 4.
  • FIG. 1 A preferred embodiment of the invention is illustrated in FIG. 1.
  • the vector generator shown may operate as a constant time or a constant velocity system as will be explained later.
  • a computer 2 generates, during successive time intervals, successive groups of signals, each such group of signals representing a multiple digit binary number which defines one component of a vector to be drawn on a cathode-ray tube 4.
  • Each group of signals representing an X (horizontal) component of a vector is applied, in parallel, to theX-registers 6 via multiple conductor cable 31.
  • Each group of signals representing a Y (vertical component of a vector is applied, in parallel, via multiple conductor cable 33 to the Y-register 8.
  • Each of the Xregisters 6 and Y-registers 8 comprises two storage registers.
  • X-registers 6 only.
  • the first storage register in X-registers 6 receives from computer 2 a group of signals indicative of the end point value of the X-component of the first vector to be drawn.
  • the second register in registers 6 stores no data at this time, which is indicative of the zero starting point of the X-component of the first vector.
  • a short time before the second time interval in which the second vector is to be drawn the data in the first register is shifted into the second register.
  • the second register therefore, is now storing the starting point data of the X-component of the second vector which is to be drawn in the second time interval.
  • the first register receives data indicative of the end point value of the vector to be drawn during this time interval.
  • the shifting of data into the first and second registers of X-registers 6 continues in like manner during succeeding time intervals.
  • the first and second registers in Y-registers 8 operate in a similar fashion to those described for registers 6 and so will not be explained in detail. A more detailed explanation concerning the operation of registers 6 and 8 is to be given shortly.
  • a reference voltage and ramp generator 10 concurrently produces four waves, namely first and second direct-current reference levels and first and second complementary ramp waves which extend between these levels. These four waves are coupled to input terminals of horizontal and vertical deflection circuits l4 and 16, respectively.
  • the velocity at which the ramp waves are generated is controlled by a vector velocity control unit 12 which is coupled between the registers 6 and 8 on the one hand and the generator 10 on the other hand.
  • the horizontal and vertical deflection circuits l4 and 16 each include groups of switches and logic gates, each group of switches for passing one of the four waves produced by the generator 10.
  • the switches are controlled by the signals stored in the X- and Y-registers, which signals are applied to the logic gates of the deflection circuits via multiple conductor cables 7 and 9.
  • the waves passed by the switches in the deflection circuits are summed with different weights, to produce the horizontal and vertical deflection waves.
  • These deflection waves are coupled to horizontal and vertical deflection means such as plates 18a and 20a, respectively, of cathode-ray tube 4.
  • Horizontal deflection plate 181 is connected in common with vertical deflection plate 20b to ground.
  • FIG. 2 is a detailed schematic and block diagram of certain portions of FIG. 1.
  • Computer 2 X-registers 6, reference voltage and ramp generator 10, and horizontal deflection circuits 14-are illustrated.
  • Y-registers 8 and vertical deflection circuit 16 are not shown as they are identical in structure and operation to X-registers 6 and horizontal deflection circuits 14, respectively.
  • the X-registers 6 include two storage registers, as explained earlier.
  • the first register is comprised of a plurality of storage devices such as flip-flops A, B F
  • the second register is comprised of a plurality of storage devices such as flip-flops A, B F.
  • each register section has six stages (three of which are shown), however, a greater or lesser number may be used dependent on the deflection wave accuracy required.
  • Each of the flip-flops A, B F in the first register receive set signals from AND-gates 22a, 22b 22f and reset signals from AND-gates 24a, 24b 24f.
  • the flip-flops A, B F in the second register receive set signals from AND-gates 26a, 26b 26f and reset signals from AND-gates 28a, 28b 28]".
  • bits of information describing a terminal point of the horizontal component of a vector are transmitted, in parallel, from computer 2 to flip-flops A, B F via lines 30a, 30b 30f.
  • bits of information on lines 30a and 30] are the most significant (MSB) and least significant (LSB), respectively, and that the bits of information on lines 30a, 30b and 30f are relatively positive signals representing a binary l. (The convention adopted is that a relatively positive signal is indicative of a binary l and a relatively negative signal is indicative of a binary 0.)
  • the binary 1 signal is applied to the input terminal of an inverter 32a and a first input terminal 34a of AND-gate 22a.
  • the binary output signal from inverter 32a disables AND-gate 24a and the binary 1 signal applied to terminal 34a primes AND-gate 22a.
  • a signal from AND-gate 38 of generator is applied to the second input terminals of gates 22a and 24a via line 36. At time t this signal is at a relatively positive or binary l level, as will be explained later.
  • Flip-flop A is in the reset or 0 state at time t as gates 26a and 28a are disabled. The latter are disabled by the execute complete signal 0 which is at a binary 0 level.
  • This Q signal is produced by a monostable multivibrator 40 which is always triggered to the 1 state a short interval before a clock pulse t t etc., and which automatically returns to the 0 state a short interval prior to the leading edge of the clock pulse, all as will be explained shortly.
  • the output signal from the 1 terminal of flip-flop A is illustrated at A and the execute complete signal from the 1 terminal of monostable multivibrator 40 of generator 10 is illustrated at Q.
  • the output signals from flip-flops A and A serve as input signals to four AND-gates 42a, 42b, 42c and 42d.
  • Gate 42a receives A and A; 421: receives A and A; 42c receives A and A; and 42d receives A and A.
  • the gates control the operation of four electronic singlepole single-throw (SPST) switches 44a, 44b, 44c, and 44d, respectively, that is, when a gate is enabled it closes the switch and the switch conducts the input wave it receives (one of-l-E, ST, E and +ST) to the common switch output terminal 45.
  • the switches may be any one of a number of electronic SPST switches which are commercially available.
  • the inputs to the respective switches 44a44d, are the positive referencevoltage (+E); the negative ramp wave (ST); the negative reference voltage (E); and the positive ramp wave (+ST). The manner in which these four waves are generated is discussed in detail later.
  • a relatively short time prior to monostable multivibrator 40 is set to the 1 state, as will be explained shortly, and as illustrated at 0 (FIG. 3).
  • AND-gate 26a becomes enabled and flip-flop A is set to the I state (A' changes to l).
  • AND-gate 42a is then enabled as flip-flops A and A are each in the 1 state, whereby switch 440 selects the positive reference voltage (+13).
  • monostable multivibrator 40 is set to the 1 state whereby gate 280 is enabled which in turn resets flip-flop A to the 0 state. Since flip-flops A and A are each in the reset or 0 state, AND-gate 42c is enabled energizing switch 44c which selects negative reference voltage (E).
  • mul tivibrator 40 is again set to the 1 state and AND-gate 28a is enabled whereby flip-flop A remains in the reset or 0 state. Since flip-flops A and A are still in the reset or 0 state, E remains as the selected wave.
  • deflection circuits 14 which are controlled by fiipflops B, B F, F, operate similarly to those described for flip-flops A, A.
  • the output signals from the respective selection circuits (W for A, A) are coupled through resistors of different value to a common summing bus 46.
  • Each resistor has a value inversely proportional to the power of two represented by the corresponding digit or bit.
  • the resistor corresponding to the least significant digit has a value R, as indicated, the resistor (not shown) for the next most significant bit (the fifth bit in this example) has a value R12; the resistor (not shown) for the next (third) most significant bit (the fourth bit in this example) has a value R/4; the resistor (not shown) for the next (fourth) most significant bit has a value of R/8 and so on up to the resistor for the most significant bit (in this instance the first bit) which has a value of R/32, as shown.
  • each resistor is shown as a single element, in practice, any one of a number of known ladder networks may be utilized.
  • the currents passing through the resistors to the summing bus 46 are applied to a summing amplifier 48, which is represented in conventional fashion.
  • the resultant current flowing through the summing bus 46 is converted to a voltage by the amplifier 48 and is applied to the horizontal deflection plates of the cathode-ray tube 4 (FIG. 1) for deflecting the electron beam in the horizontal direction.
  • the vertical component of the vector is generated in like manner whereby the resultant vector is drawn on the face of cathode-ray tube 4.
  • the reference voltage and ramp generator 10 may generate a ramp wave in a constant time or at a constant velocity.
  • the following description is based on the generator 10 operating in a'constant time to simplify the timing diagram illustrated at FIG. 3.
  • the voltage (S) applied to switch 50 (upper part of FIG. 2), which is derived in the vector velocity control unit 12 (FIGS. 1 and 4), determines whether the ramp generator operates in a constant time or at a constant velocity.
  • C is the value of capacitor 62
  • V is the voltage to which it charges (+V in this instance)
  • I is the current applied to terminal 58 of integrator 52. I is proportional to S since 1% S )/R, where R is the resistance of resistor 74.
  • the ramp generator operates in a time which is inversely proportional to -S. It can be proved that if S is varied proportional to one over the vector length, the ramp generator generates vectors of different lengths at a constant velocity. This is to be explained in detail shortly.
  • the ramp generator (FIG. 2) comprises an AND-gate 38 which receives input signals from computer 2, and the 0 terminals of multivibrators 40 and 78.
  • the output terminal of gate 38 is connected via line 84 to a monostable multivibrator 82.
  • the multivibrator 82 is normally in the 0 state, that is, the 0 output terminal is at a binary 1 level and the 1 output terminal is at a binary 0 level. (The convention is adopted that a relatively positive pulse is indicative of a binary l and a relatively negative pulse is indicative of a binary O.)
  • monostable multivibrator 82 In response to a pulse at a binary 1 level monostable multivibrator 82 is switched to the 1 state (1 terminal at binary 1 level). A short time thereafter, monostable multivibrator returns to the 0 state. The time that monostable multivibrator 82 remains in the 1 state is determined by the design of 82.
  • the 1 output terminal of 82 is coupled to a first input terminal of an OR-gate 80.
  • the second input terminal of 80 is coupled to the 1 output terminal of a monostable multivibrator 40.
  • the output terminal of 80 is connected to the trigger terminal ofa fiip-flop 78.
  • the flip-flop 78 if in the 0 state, is set to the 1 state, or if in the 1 state, is set to the 0 state by a pulse at a binary 1 level from gate 80.
  • the 0 output terminal is connected to an input terminal of gate 38.
  • the 1 output terminal is connected to a control terminal 76 of an electronic single-pole double-throw (SPDT) switch 50.
  • SPDT electronic single-pole double-throw
  • Switch 50 has input terminals 68 and 72 and an output terminal 60.
  • Terminal 68 is connected to a reference potential +V through a resistor 70 and to one terminal of a resistor 66.
  • Terminal 72 is connected to voltage S through resistor 74.
  • Output terminal 60 is connected to one terminal of capacitor 62 and the negative input terminal 58 of an integrator 52.
  • flip-flop 78 If flip-flop 78 is in the 0 state, the binary 0 level at control terminal 76 of switch 50 connects input terminal 68 to output terminal 60. If 78 is in the 1 state the binary 1 level at control terminal 76 of switch 50 connects input terminal 72 to output terminal 60.
  • the positive input terminal 56 of integrator 52 is connected to ground.
  • the output terminal 64 is connected to terminals of capacitor 62 and resistor 66. Integrator 52 therefore produces at its output terminal 64 a linearly increasing voltage which is of opposite polarity to the input current present at terminal
  • Output terminal 64 of integrator 52 is also connected through resistors 94 and 96 to the negative input terminal 95 and the positive input terminal 97 of amplifiers 98 and 100, respectively.
  • Amplifier 98 produces at its output terminal a voltage which is equal to and of opposite polarity to the voltage present at input terminal 95.
  • the voltage produced is the negative ramp waveform (ST).
  • Amplifier 100 produces at its output terminal a voltage which is equal to and of the same polarity as the voltage present at input terminal 97.
  • the voltage produced is the positive ramp waveform (+ST).
  • Output terminal 64 of integrator 52 is further connected to a first input terminal 92 of a comparator 88.
  • the second input terminal 90 is connected to the reference potential +V.
  • a pulse at level binary l is produced at the output terminal of comparator 88 whenever the voltage at input terminal 92 reaches +V, which is the value of the voltage at terminal 90.
  • the output terminal of comparator 88 is connected to the input terminal of the monostable multivibrator 40.
  • Monostable multivibrator 40 is normally in the 0 state (output terminal 0 at a binary 1 level and output terminal 1 at a binary 0 level). In response to a pulse at a binary 1 level at its input terminal, 40 switches to the 1 state and then returns to the 0 state a short time later. The time monostable multivibrator 40 remains in the 1 state is determined by the design of 40.
  • the 0 output terminal of 40 is connected to an input terminal of gate 38.
  • the 1 output terminal of 40 is connected to an input terminal of gate and is also connected to computer 2 and, as explained earlier, input gates 26a, 28a, etc.
  • a reference supply 54 which may be one of many known in the art, generates direct-current levels :V and E, where liEl [iv]
  • the levels :E are applied to the switches 44 of deflection circuits 14 (lower part of FIG. 2) and the level +V is applied to l tenninal of resistor 70 and terminal of comparator 88.
  • flip-flop 78 Prior to the first clock pulse at time t flip-flop 78 is in the 0 state.
  • the 0 state at the 1 terminal of this flip-flop is applied to the control terminal 76 of switch 50 which connects input terminal 68 to output terminal 60.
  • Capacitor 62 is bypassed and the +V reference voltage is applied via resistor 70 to input terminal 58 of integrator 52 producing a signal V at output terminal 64.
  • the first clock pulse (C, FIG. 3) is applied via line 102 enabling AND-gate 38.
  • the signal produced by the AND-gate 38 is coupled via line 36 to certain input gates of registers 6, whereby the flip-flops A-F become set or reset depending upon the binary digits on lines 30a-30b.
  • This signal is also coupled via line 84 to the input terminal of monostable multivibrator 82 setting it to the I state.
  • the output signal produced by gate 38 and the signal produced at the 1 terminal of multivibrator 82 are illustrated at M and N, respectively, of FIG. 3.
  • the positive pulse N from the one output terminal of multivibrator 82 is applied to OR- gate 80.
  • the flip-flop 78 thereupon disables gate 38 and connects output terminal 60 of switch 50 to terminal 72.
  • Capacitor 62 is now back in circuit and integrator 52 begins integrating at a rate determined by S.
  • the comparator 88 When integrator 52 has integrated to the voltage +V,. the comparator 88 generates a pulse (T, FIG. 4) which sets monostable multivibrator 40 to the 1 state (Q, FIG. 4).
  • the pulse from the 1 terminal primes the gates 260-261" and 28a-28f, whereby the flip-flops A'F' assume the same states as the flip-flops AF, respectively.
  • This pulse (Execute Complete) is also coupled to the computer 2 informing it that the system is ready to generate another vector.
  • the clock pulse at time t is generated by computer 2 a fixed time delay after the Execute Complete pulse.
  • the signal from the 1 terminal of monostable multivibrator 40 also is coupled to OR-gate 80.
  • OR- gate 80 again is enabled and resets flip-flop 78 to the 0 state (P changes to 0).
  • Output terminal 60 of switch 50 is again connected to terminal 68 and the output signal level of integrator 52 again returns to V, causing the output of comparator 88 to return to a binary 0 level.
  • monostable multivibrator 40 returns to its quiescent condition, that is the signal 6 at the 0 output terminal returns to a binary 1 level. This is the second priming signal for gate 38.
  • a short time later at time t, the next clock or start pulse occurs and AND-gate 38 becomes enabled. This starts the next cycle, M changes to l, monostable stage 82 becomes set, N changes to l and so on, all as described above.
  • FIG. 4 is a block diagram of the vector velocity control unit 12 (FIG. 1). This unit, as explained earlier, generates the voltage S which controls the rate of integration of integrator 52 (FIG. 2).
  • the X-registers 6 and Y-registers 8 are connected to subtractors 104 and 106, respectively.
  • the output terminals from these subtractors are connected to a comparator 108 and gates 110 and 112.
  • the comparator 108 is also connected to the gates 110 and 112 via lines 114 and 116, respectively.
  • the output terminals of gates 110 and 112 are connected to the input terminals of registers 118 and 120, respectively.
  • Registers 118 and 120 are connected to digital-to-analog (D/A) converters 122 and 124, respectively, which are connected in the feedback path between input terminal 126 and output terminal 128 of an operational amplifier 130.
  • the input terminal 126 is connected to a source of reference potential 132 through a resistor 134.
  • the output terminal 128 is connected to the input terminal 136 of an inverter 138.
  • the X-registers 6, as explained earlier, are comprised of first (AF) and second (AF) registers (FIG. 2) 141 and 143, respectively.
  • the Y-registers 8 are comprised of first and second registers 145 and 147, respectively.
  • the output signals from the X- and Y-registers are shifted in parallel into subtractors 104 and 106, respectively, via the multiconductor cables shown as single leads in the drawing.
  • the subtractor 104 computes the absolute value of the difference in magnitude of the digits in registers 141 and 143 I AXl This computation is performed at a time shortly after the data in register 141 (A F) is shifted into register 143 (A F) and new data is shifted into register 141.
  • Subtractor 106 operates on the data in registers 145 and 147 in similar manner.
  • the subtractors may be any of a number which are known in the art.
  • lAX l and lAY signals produced are concurrently coupled, in parallel, via multiconductor cables, shown as single leads in the drawing, to comparator unit 108 and gates 110 and 112.
  • Comparators are well known in the art and one such binary comparator which may be used in the practice of this invention is described in Weinstein U.S. Pat. No. 3,251,035 assigned to the assignee of the instant invention.
  • Comparator 108 when comparing lAX I and lAYI produces one of three signals: (1) lAXl lAYl (2) lAYI lAXl; or (3) lAXl IAYl at a given time. These signals are coupled via multiconductor cables 114 and 116, shown as single leads in the drawing, to gates 110 and 112, respectively.
  • Gates 110 and 112 are detailed in FIG. 5.
  • Gate 110 comprises inverter 140, AND-gates 142 and 144, and OR-gate 146.
  • Gate 112 comprises inverter 148, AND-gates 150 and 152, and OR-gate 154.
  • the signal produced at terminal 158 is concurrently coupled to gates 110 and 112.
  • gate 110 the signal is coupled to terminal 160 of AND-gate 142 and the input terminal of the inverter 140.
  • Applied to the second input terminal of gate 142 is the AXl signal.
  • the output terminal of inverter 140 is connected to the first input terminal of gate 144, and applied to the second input terminal is lAYI
  • gate 112 the signal produced at the output terminal of gate 158 is coupled to terminal 162 of AND-gate 150 and the input terminal of inverter 148.
  • Applied to the second input terminal of gate 150 is the lAYl signal.
  • the output terminal of inverter 148 is connected to the first input terminal of gate 152, and applied to the second input terminal is lAX I.
  • Gate 142 transmits the lAX l signal to OR-gate 146 which transmits the lAXl signal to register 118 (FIG. 4).
  • Gate 150 transmits the IAYI signal to register 120 (FIG. 4).
  • lAXl IAYI This condition produces a binary 0 signal level at the terminal 158 of gate 156. This signal disables AND-gates 142 and 150.
  • Inverters 140 and 148 produce binary 1 signals at their respective output terminals in response to the binary 0 input signal.
  • AND-gates 144 and 152 therefore, are primed.
  • Gate 144 transmits the lAYl signal to vOR-gate 146 which transmits the lAY l signalto register 118 (FIG. 4).
  • Gate 152 transmits the lAX l signal to gate 154 which transmits thel AX l signal to register 120 (FIG. 4).
  • register 120 stores lAYl if lAYllAXI or stores .IAXl if lAXl IAYI
  • register 120 stores lAYl if lAYllAXI or stores .IAXl if lAXl IAYI
  • gates 110 and 112 are designed to receive lAXl and lAYl binary data serially. If, however, lAXl and IAYI binary data are to be shifted into gates 110 and 112 in parallel, there would be a gate 110 and 112 for each bit. For example, if the lAXl and lAYI signals each comprise three bits, there would be three gates 110 and three gates 112.
  • lAX l signal is shifted in parallel, over a multiconductor cable shown as a single lead, from register 118 to digital-to-analog (D/A) converter 122.
  • the lAYl signal is shifted in parallel, over a multiconductor cable shown as a single lead, to D/A converter 124.
  • the vector velocity control unit 12 (FIG. 4) approximates l/AP by one of the following equations.
  • the D/A converter 122 which converts AX from digital to analog is designed to have an impedance
  • the D/A converters 122 and 124 are in the feedback path of operational amplifier 130.
  • the standard transfer function of an operational amplifier is:
  • Equation (6) E EL-7L2.5RTKR 1 R.
  • the following explanation should make it clear that if the voltage described in equation (7) is applied via inverter 138 to integrator 52 (FIG. 2), all vectors are drawn at a substantially constant velocity.
  • the voltage S applied to the integrator 52 is: s) -Em2.5RTKR Rt'n AP
  • the output signal from the vertical amplifier which is the vertical component of the vector is: (13) K RZAPMlQ
  • the resultant vector AP is:
  • first and second direct-current levels namely first and second direct-current levels, a first ramp extending from said first to said second level, and a second ramp extending from said second to said first level;
  • means for producing a sum signal comprising means for adding with different weights the selected waves.
  • the means for adding includes means for adding the selected waves with weights, in each case, proportional to the power of two represented by the signal calling for said wave.
  • means for concurrently producing four waves namely first and second direct-current levels, a first ramp extending from said first to said second level, and a second ramp extending from said second to said first level;
  • said means responsive to each group of signals comprising for each signal in each group a first and second means, each capable of assuming one of two states, the first means assuming at the beginning of each interval one state if the signal represents one binary value and assuming the second state if the signal represents the other binary value, the second means assuming the state of the first means at a time slightly before the end of a time interval, said first and second means controlling the selection made by said four switch means.
  • a line generator comprising: means for generating first and second groups of signals representing multiple digit binary numbers which define the terminal point of a line, each binary number being capable of changing its value during successive time intervals, said groups of signals changing correspondingly;
  • first and second means for each signal in each of said groups, each capable of assuming one of two states, said first means assuming at the beginning of each interval one state if the signal represents one binary value and assuming the second state if the signal represents the other binary value, the second means assuming the state of the first means at a time slightly before the end of the time interval;
  • means for generating first and second deflection waveforms comprising means for adding, with weights proportional to the power of two represented by the signal calling for the selected wave in each group of signals.
  • Patent No. 3,633 21 ma January 25 192 2 Invent0 Howard Mulder Scott 82 Carl Rutherford Carson It is certified that error appears in the above-identified patent and that said Letters Patent are hereby cetcre'cted as shown beln'w':

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CA (1) CA935240A (enrdf_load_stackoverflow)
DE (1) DE2102990A1 (enrdf_load_stackoverflow)
FR (1) FR2076925A5 (enrdf_load_stackoverflow)
GB (1) GB1335874A (enrdf_load_stackoverflow)
NL (1) NL7100887A (enrdf_load_stackoverflow)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3870871A (en) * 1973-11-29 1975-03-11 Thomas Edward Nead Vector magnitude summing circuit
US4074359A (en) * 1976-10-01 1978-02-14 Vector General, Inc. Vector generator
US4481605A (en) * 1982-03-05 1984-11-06 Sperry Corporation Display vector generator utilizing sine/cosine accumulation
EP0108473A3 (en) * 1982-09-09 1987-07-01 Sperry Corporation Slew length timer
US4736330A (en) * 1984-09-04 1988-04-05 Capowski Joseph J Computer graphics display processor for generating dynamic refreshed vector images

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2218646B1 (enrdf_load_stackoverflow) * 1973-02-20 1976-09-10 Thomson Csf

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3320409A (en) * 1963-01-30 1967-05-16 Burroughs Corp Electronic plotting device
US3500332A (en) * 1967-02-10 1970-03-10 Sanders Associates Inc Curve generator for oscillographic display
US3533096A (en) * 1967-09-01 1970-10-06 Sanders Associates Inc Character display system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3320409A (en) * 1963-01-30 1967-05-16 Burroughs Corp Electronic plotting device
US3500332A (en) * 1967-02-10 1970-03-10 Sanders Associates Inc Curve generator for oscillographic display
US3533096A (en) * 1967-09-01 1970-10-06 Sanders Associates Inc Character display system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3870871A (en) * 1973-11-29 1975-03-11 Thomas Edward Nead Vector magnitude summing circuit
US4074359A (en) * 1976-10-01 1978-02-14 Vector General, Inc. Vector generator
US4481605A (en) * 1982-03-05 1984-11-06 Sperry Corporation Display vector generator utilizing sine/cosine accumulation
EP0108473A3 (en) * 1982-09-09 1987-07-01 Sperry Corporation Slew length timer
US4736330A (en) * 1984-09-04 1988-04-05 Capowski Joseph J Computer graphics display processor for generating dynamic refreshed vector images

Also Published As

Publication number Publication date
CA935240A (en) 1973-10-09
GB1335874A (en) 1973-10-31
NL7100887A (enrdf_load_stackoverflow) 1971-07-27
DE2102990A1 (de) 1971-07-29
FR2076925A5 (enrdf_load_stackoverflow) 1971-10-15

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