US3638214A

US3638214A - Vector generator

Info

Publication number: US3638214A
Application number: US5229A
Authority: US
Inventors: Howard Mulder Scott; Carl Rutherford Corson
Original assignee: RCA Corp
Current assignee: RCA Corp
Priority date: 1970-01-23
Filing date: 1970-01-23
Publication date: 1972-01-25
Anticipated expiration: 1989-01-25
Also published as: NL7100887A; CA935240A; FR2076925A5; DE2102990A1; GB1335874A

Abstract

Complementary ramp waves are generated which extend between first and second direct-current levels. During successive time intervals, multiple digit binary words are generated defining the horizontal and vertical components of the vector being generated. Registers store the binary words, and gates respond to the stored digits for controlling a plurality of switches which select for each digit one of the complementary ramp waves or the directcurrent levels, depending on whether or not a digit has changed value during the preceding time interval. A sum wave is obtained for each component of the vector by adding the selected waves with weights dependent on the power of two represented by a particular digit. The sum waves serve as deflection waveforms for the respective deflection means of the cathode-ray tube.

Description

United States Patent Scott et a1. Jan. 25, 1972 54 VECTOR GENERATOR Primary Examiner-Thomas B. Habecker Assistant Examiner-Marshall M. Curtis [72] Inventors: Howard Mulder Scott, Morrestown; Carl Au fl ch i t ff Rutherford Corson, Trenton, both of NJ. [73] Assignee: RCA Corporation [57] [ABSTRACT [22] Filed. Jam 23 1970 Complementary ramp waves are generated which extend between first and second direct-current levels. During succes- [21] App]. No.: 5,229 sive time intervals, multiple digit binary words are generated defining the horizontal and vertical components of the vector being generated. Registers store the binary words, and gates "340/324 6323933 respond to the stored digits for controlling a plurality of l 5 8] Fie'ld 1 5/1 8 switches which select for each digit one of the complementary "I 179/15 ramp waves or the direct-current levels, depending on whether or not a digit has changed value during the preceding 56] References Cited time interval. A sum wave is obtained for each component of l the vector by adding the selected waves with weights depen- UNITED STATES PATENTS dent on the power of two represented by a particular digit.

The sum waves serve as deflection waveforms for the respec- Larrowe A five deflection means of [he cathode-ray tube. 3,533,096 10/1970 Bouchard ..340/324 A 3,500,332 3/1970 Vosbury ..340/324 A 8 Claims, 5 Drawing Figures X HOQIZONTHL DEFLEt'T/UA/ REG/5W5 cnzcu/"rs O 2 tr M f U l l i P & a 10 ...a t Molt. 5Tfl/ZT Q REFERENCE VOLTAGE ExEcurE mm: E RAMP GENE apron.

VElT/CAL osrtscr/au CIIZCUITS vecron. VELOCITY CONTROL.

VECTOR GENERATOR BACKGROUND OF THE INVENTION Terminal displays are becoming increasingly important in computer and data processing systems. An important feature present in many of these displays is the capability to generate vectors.

Many different forms of vector generators are known in the art, each with its own good and bad features. Certain ones generate a vector in a constant time whereas others are generated at a constant velocity. In a constant time system, vectors of different length are generated in the same amount of time which results in vectors of different length having different brightness. In a constant velocity system, since a vector is generated in a time dependent on its length, all vectors are substantially drawn at equal brightness.

In either type of vector generator, the usual practice is to utilize a plurality of ramp generators and matrices to generate a vector.

It is the object of this invention to provide a vector generator which operates as a constant time or constant velocity type depending on the users need and which utilizes only one ramp generator and a relatively simple and inexpensive gating system for generating vectors.

SUMMARY OF THE INVENTION Means are provided for concurrently producing four waves, namely first and second direct-current levels, a first ramp extending from the first to the second level, and a second ramp extending from the second level to the first level. During successive intervals of time, successive groups of signals are generated, each such group of signals representing a multiple digit binary number. Means responsive to the signals select for each such signal one of the four waves, depending upon the value of the binary digit represented by the signal and whether or not it has changed value during the preceding time interval. A sum signal is obtained for each group of signals by adding, with different weights, the selected waves corresponding to each such group ofsignals.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a block diagram of a preferred form of the invention;

FIG. 2 is a schematic and block diagram which includes a more detailed showing of the reference voltage and sawtooth generator and horizontal deflection circuits of FIG. 1;

FIG. 3 illustrates waveforms present in the circuit of FIG. 2;

FIG. 4 is a block diagram which includes a more detailed showing of the vector velocity control circuit of FIG. 1; and

FIG. 5 is a block diagram which includes a more detailed showing of the gates in the vector velocity control circuit of FIG. 4.

DETAILED DESCRIPTION A preferred embodiment of the invention is illustrated in FIG. 1. The vector generator shown may operate as a constant time or a constant velocity system as will be explained later.

A computer 2 generates, during successive time intervals, successive groups of signals, each such group of signals representing a multiple digit binary number which defines one component of a vector to be drawn on a cathode-ray tube 4.

Each group of signals representing an X (horizontal) component of a vector is applied, in parallel, to theX-registers 6 via multiple conductor cable 31. Each group of signals representing a Y (vertical component of a vector is applied, in parallel, via multiple conductor cable 33 to the Y-register 8.

Each of the Xregisters 6 and Y-registers 8 comprises two storage registers. Consider X-registers 6 only. During the first time interval X-registers 6 receive data, the first storage register in X-registers 6 receives from computer 2 a group of signals indicative of the end point value of the X-component of the first vector to be drawn. The second register in registers 6 stores no data at this time, which is indicative of the zero starting point of the X-component of the first vector.

A short time before the second time interval in which the second vector is to be drawn the data in the first register is shifted into the second register. The second register, therefore, is now storing the starting point data of the X-component of the second vector which is to be drawn in the second time interval.

At the start of the second time interval the first register receives data indicative of the end point value of the vector to be drawn during this time interval. The shifting of data into the first and second registers of X-registers 6 continues in like manner during succeeding time intervals. The first and second registers in Y-registers 8 operate in a similar fashion to those described for registers 6 and so will not be explained in detail. A more detailed explanation concerning the operation of

registers

6 and 8 is to be given shortly.

A reference voltage and ramp generator 10 concurrently produces four waves, namely first and second direct-current reference levels and first and second complementary ramp waves which extend between these levels. These four waves are coupled to input terminals of horizontal and vertical deflection circuits l4 and 16, respectively. The velocity at which the ramp waves are generated is controlled by a vector velocity control unit 12 which is coupled between the

registers

6 and 8 on the one hand and the generator 10 on the other hand.

The horizontal and vertical deflection circuits l4 and 16, each include groups of switches and logic gates, each group of switches for passing one of the four waves produced by the generator 10. The switches are controlled by the signals stored in the X- and Y-registers, which signals are applied to the logic gates of the deflection circuits via multiple conductor cables 7 and 9. The waves passed by the switches in the deflection circuits are summed with different weights, to produce the horizontal and vertical deflection waves. These deflection waves are coupled to horizontal and vertical deflection means such as plates 18a and 20a, respectively, of cathode-ray tube 4. Horizontal deflection plate 181; is connected in common with vertical deflection plate 20b to ground.

FIG. 2 is a detailed schematic and block diagram of certain portions of FIG. 1. Computer 2, X-registers 6, reference voltage and ramp generator 10, and horizontal deflection circuits 14-are illustrated. Y-registers 8 and vertical deflection circuit 16 are not shown as they are identical in structure and operation to X-registers 6 and horizontal deflection circuits 14, respectively.

The X-registers 6 include two storage registers, as explained earlier. The first register is comprised of a plurality of storage devices such as flip-flops A, B F, and the second register is comprised of a plurality of storage devices such as flip-flops A, B F. In the embodiment of the invention illustrated, each register section has six stages (three of which are shown), however, a greater or lesser number may be used dependent on the deflection wave accuracy required.

Each of the flip-flops A, B F in the first register receive set signals from AND-gates 22a, 22b 22f and reset signals from AND-gates 24a, 24b 24f.

The flip-flops A, B F in the second register receive set signals from AND-gates 26a, 26b 26f and reset signals from AND-gates 28a, 28b 28]".

The setting and resetting of flip-flops A and A of the first and second register sections, respectively, is explained in detail below. The remaining stages operate in Similar fashion.

Assume that at a time t which corresponds in time with a clock pulse being generated, bits of information describing a terminal point of the horizontal component of a vector are transmitted, in parallel, from computer 2 to flip-flops A, B F via

lines

30a, 30b 30f. Further assume that the bits of information on lines 30a and 30] are the most significant (MSB) and least significant (LSB), respectively, and that the bits of information on

lines

30a, 30b and 30f are relatively positive signals representing a binary l. (The convention adopted is that a relatively positive signal is indicative of a binary l and a relatively negative signal is indicative of a binary 0.)

Considering flip-flop A only, the binary 1 signal is applied to the input terminal of an inverter 32a and a first input terminal 34a of AND-gate 22a. The binary output signal from inverter 32a disables AND-gate 24a and the binary 1 signal applied to terminal 34a primes AND-gate 22a. A signal from AND-gate 38 of generator is applied to the second input terminals of

gates

22a and 24a via line 36. At time t this signal is at a relatively positive or binary l level, as will be explained later. AND-gate 22a, therefore, is enabled and the binary 1 signal (A=1) it produces sets flip-flop A to the 1 state. Referring briefly to FIG. 3, the output signals from gate 38 and the 1 terminal of flip-flop A are illustrated at M and A, respectively.

Flip-flop A is in the reset or 0 state at time t as

gates

26a and 28a are disabled. The latter are disabled by the execute complete signal 0 which is at a binary 0 level. This Q signal is produced by a monostable multivibrator 40 which is always triggered to the 1 state a short interval before a clock pulse t t etc., and which automatically returns to the 0 state a short interval prior to the leading edge of the clock pulse, all as will be explained shortly. The output signal from the 1 terminal of flip-flop A is illustrated at A and the execute complete signal from the 1 terminal of monostable multivibrator 40 of generator 10 is illustrated at Q.

The output signals from flip-flops A and A serve as input signals to four AND-gates 42a, 42b, 42c and 42d. Gate 42a receives A and A; 421: receives A and A; 42c receives A and A; and 42d receives A and A. These inputs cover all of the combinations of states which are possible for flip-flops A and A so that it is clear that only one of the four AND-gates 42 can be enabled at a time.

The gates control the operation of four electronic singlepole single-throw (SPST) switches 44a, 44b, 44c, and 44d, respectively, that is, when a gate is enabled it closes the switch and the switch conducts the input wave it receives (one of-l-E, ST, E and +ST) to the common switch output terminal 45. The switches may be any one of a number of electronic SPST switches which are commercially available. The inputs to the respective switches 44a44d, are the positive referencevoltage (+E); the negative ramp wave (ST); the negative reference voltage (E); and the positive ramp wave (+ST). The manner in which these four waves are generated is discussed in detail later.

Returning to FIG. 3, it may be seen how the selection process of the four waves is accomplished during four successive time intervals r t Prior to time t all flip-flops in the first and second registers are in the reset condition as no data or binary bits of information have been inserted in the X-registers 6 (FIG. 2). Flip-flops A and A are each in the reset or zero state so that A=1 and A'=l and AND-gate 42c is enabled. All ofthe remaining AND-gates 42a, 42b, and 42d each receive at least one input representing binary 0 so that they are all disabled. Thus, of the four switches 44, only 440 is closed and it passes the reference voltage (E) to common output terminal 45. The output signals present at the 1 output terminals of A and A are illustrated at A and A in FIG. 3 and the output signal produced by the enabled 1 of the switches 44 is illustrated at W in FIG. 3.

Assume that at clock pulse time t a signal indicative of a binary l is applied to line 30a. As M=l, AND-gate 22a becomes enabledand sets flip-flop A to the 1 state. Flip-flop A remains in the reset or 0 state as monostable multivibrator 40 is in the 0 state (0 0). AND-gate 42d thereupon becomes enabled as A=l, A=l, and closed switch 44d passes selects") the positive ramp (+ST) to the common output terminal 45.

A relatively short time prior to monostable multivibrator 40 is set to the 1 state, as will be explained shortly, and as illustrated at 0 (FIG. 3). In response to the Q=1 signal, AND-gate 26a becomes enabled and flip-flop A is set to the I state (A' changes to l). AND-gate 42a is then enabled as flip-flops A and A are each in the 1 state, whereby switch 440 selects the positive reference voltage (+13).

Assume that at clock pulse time t a bit of data indicative of binary 0 is applied via line 30a. The l produced by inverter 32a thereupon enables AND-gate 240 as M=l at this time. The enabled AND-gate 24a resets flip-flop A changing to l. Flip-flop A remains in the l state as monostable multivibrator 40 has returned to the 0 state (see FIG. 3, wave Q), whereby gates 26a and 280 are disabled. Therefore, AND-gate 42b becomes enabled, energizing switch 441: whereby the negative ramp voltage (ST) is selected.

A relatively short time prior to clock pulse time t,, monostable multivibrator 40 is set to the 1 state whereby gate 280 is enabled which in turn resets flip-flop A to the 0 state. Since flip-flops A and A are each in the reset or 0 state, AND-gate 42c is enabled energizing switch 44c which selects negative reference voltage (E).

Assume that at clock pulse time a bit of data indicative of binary O is applied to line 30a (this is the same value bit as applied during the previous interval t -t Now the flip-flop A remains in the same state, that is, the reset or 0 state. Flip-flop A remains in the 0 state as

gates

26a and 28a are disabled since monostable multivibrator 40 has returned to the reset or 0 condition. Switch 440, therefore, remains energized and E remains as the selected wave.

A relatively short time prior to clock pulse time t, mul tivibrator 40 is again set to the 1 state and AND-gate 28a is enabled whereby flip-flop A remains in the reset or 0 state. Since flip-flops A and A are still in the reset or 0 state, E remains as the selected wave.

Assume that at clock pulse time a bit of data indicative of a binary l is applied to line 30a. It may be seen from the discussion above that this results in the selection of the positive ramp voltage (+ST), as was done at clock pulse time t Wave Z (FIG. 3) is the unblanking voltage applied to the cathode-ray tube 4 (FIG. 1). The selected wave W is unblanked in the time interval when the ramp wave is traversing from E to +E or vice versa. This is done so that transients present at the beginning of a time interval and those caused by the integrator generating the ramp have no effect on the vector generated.

The selection process, as described above, continues in like manner for succeeding time intervals. The portions of deflection circuits 14, which are controlled by fiipflops B, B F, F, operate similarly to those described for flip-flops A, A.

The output signals from the respective selection circuits (W for A, A) are coupled through resistors of different value to a common summing bus 46. Each resistor has a value inversely proportional to the power of two represented by the corresponding digit or bit. Thus, if the resistor corresponding to the least significant digit has a value R, as indicated, the resistor (not shown) for the next most significant bit (the fifth bit in this example) has a value R12; the resistor (not shown) for the next (third) most significant bit (the fourth bit in this example) has a value R/4; the resistor (not shown) for the next (fourth) most significant bit has a value of R/8 and so on up to the resistor for the most significant bit (in this instance the first bit) which has a value of R/32, as shown.

While in FIG. 2 each resistor is shown as a single element, in practice, any one of a number of known ladder networks may be utilized.

The currents passing through the resistors to the summing bus 46 are applied to a summing amplifier 48, which is represented in conventional fashion. The resultant current flowing through the summing bus 46 is converted to a voltage by the amplifier 48 and is applied to the horizontal deflection plates of the cathode-ray tube 4 (FIG. 1) for deflecting the electron beam in the horizontal direction.

As was explained earlier, the vertical component of the vector is generated in like manner whereby the resultant vector is drawn on the face of cathode-ray tube 4.

The reference voltage and ramp generator 10 (FIG. 2), as was explained earlier, may generate a ramp wave in a constant time or at a constant velocity. The following description is based on the generator 10 operating in a'constant time to simplify the timing diagram illustrated at FIG. 3.

The voltage (S) applied to switch 50 (upper part of FIG. 2), which is derived in the vector velocity control unit 12 (FIGS. 1 and 4), determines whether the ramp generator operates in a constant time or at a constant velocity.

The time required to charge the capacitor 62 of integrator 52 is determined by the equation:

(1) t=CV/1,

where C is the value of capacitor 62, V is the voltage to which it charges (+V in this instance), and I is the current applied to terminal 58 of integrator 52. I is proportional to S since 1% S )/R, where R is the resistance of resistor 74.

Since C and V are constants, if I is held constant t also remains constant. This means that all vectors are generated in the same amount of time if S is held at a constant level. That is, a relatively short vector is generated in the same amount of time as a relatively long vector.

If S is varied from vector to vector, the ramp generator operates in a time which is inversely proportional to -S. It can be proved that if S is varied proportional to one over the vector length, the ramp generator generates vectors of different lengths at a constant velocity. This is to be explained in detail shortly.

The ramp generator (FIG. 2) comprises an AND-gate 38 which receives input signals from computer 2, and the 0 terminals of

multivibrators

40 and 78. The output terminal of gate 38 is connected via line 84 to a monostable multivibrator 82. The multivibrator 82 is normally in the 0 state, that is, the 0 output terminal is at a binary 1 level and the 1 output terminal is at a binary 0 level. (The convention is adopted that a relatively positive pulse is indicative of a binary l and a relatively negative pulse is indicative of a binary O.) In response to a pulse at a binary 1 level monostable multivibrator 82 is switched to the 1 state (1 terminal at binary 1 level). A short time thereafter, monostable multivibrator returns to the 0 state. The time that monostable multivibrator 82 remains in the 1 state is determined by the design of 82.

The 1 output terminal of 82 is coupled to a first input terminal of an OR-gate 80. The second input terminal of 80 is coupled to the 1 output terminal of a monostable multivibrator 40. The output terminal of 80 is connected to the trigger terminal ofa fiip-flop 78.

The flip-flop 78, if in the 0 state, is set to the 1 state, or if in the 1 state, is set to the 0 state by a pulse at a binary 1 level from gate 80. The 0 output terminal is connected to an input terminal of gate 38. The 1 output terminal is connected to a control terminal 76 of an electronic single-pole double-throw (SPDT) switch 50.

Switch 50 has input terminals 68 and 72 and an output terminal 60. Terminal 68 is connected to a reference potential +V through a resistor 70 and to one terminal of a resistor 66. Terminal 72 is connected to voltage S through resistor 74. Output terminal 60 is connected to one terminal of capacitor 62 and the negative input terminal 58 of an integrator 52.

If flip-flop 78 is in the 0 state, the binary 0 level at control terminal 76 of switch 50 connects input terminal 68 to output terminal 60. If 78 is in the 1 state the binary 1 level at control terminal 76 of switch 50 connects input terminal 72 to output terminal 60.

The positive input terminal 56 of integrator 52 is connected to ground. The output terminal 64 is connected to terminals of capacitor 62 and resistor 66. Integrator 52 therefore produces at its output terminal 64 a linearly increasing voltage which is of opposite polarity to the input current present at terminal Output terminal 64 of integrator 52 is also connected through

resistors

94 and 96 to the negative input terminal 95 and the positive input terminal 97 of

amplifiers

98 and 100, respectively. Amplifier 98 produces at its output terminal a voltage which is equal to and of opposite polarity to the voltage present at input terminal 95. The voltage produced is the negative ramp waveform (ST). Amplifier 100 produces at its output terminal a voltage which is equal to and of the same polarity as the voltage present at input terminal 97. The voltage produced is the positive ramp waveform (+ST).

Output terminal 64 of integrator 52 is further connected to a first input terminal 92 of a comparator 88. The second input terminal 90 is connected to the reference potential +V. A pulse at level binary l is produced at the output terminal of comparator 88 whenever the voltage at input terminal 92 reaches +V, which is the value of the voltage at terminal 90. The output terminal of comparator 88 is connected to the input terminal of the monostable multivibrator 40.

Monostable multivibrator 40 is normally in the 0 state (output terminal 0 at a binary 1 level and output terminal 1 at a binary 0 level). In response to a pulse at a binary 1 level at its input terminal, 40 switches to the 1 state and then returns to the 0 state a short time later. The time monostable multivibrator 40 remains in the 1 state is determined by the design of 40. The 0 output terminal of 40 is connected to an input terminal of gate 38. The 1 output terminal of 40 is connected to an input terminal of gate and is also connected to computer 2 and, as explained earlier,

input gates

26a, 28a, etc.

A reference supply 54, which may be one of many known in the art, generates direct-current levels :V and E, where liEl [iv] The levels :E are applied to the switches 44 of deflection circuits 14 (lower part of FIG. 2) and the level +V is applied to l tenninal of resistor 70 and terminal of comparator 88.

Prior to the first clock pulse at time t flip-flop 78 is in the 0 state. The 0 state at the 1 terminal of this flip-flop, as explained before, is applied to the control terminal 76 of switch 50 which connects input terminal 68 to output terminal 60. Capacitor 62 is bypassed and the +V reference voltage is applied via resistor 70 to input terminal 58 of integrator 52 producing a signal V at output terminal 64.

At time t the first clock pulse (C, FIG. 3) is applied via line 102 enabling AND-gate 38. As was explained earlier, the signal produced by the AND-gate 38 is coupled via line 36 to certain input gates of registers 6, whereby the flip-flops A-F become set or reset depending upon the binary digits on lines 30a-30b. This signal is also coupled via line 84 to the input terminal of monostable multivibrator 82 setting it to the I state. The output signal produced by gate 38 and the signal produced at the 1 terminal of multivibrator 82 are illustrated at M and N, respectively, of FIG. 3. The positive pulse N from the one output terminal of multivibrator 82 is applied to OR- gate 80. At this same time, the monostable multivibrator 40 is at the 0 state (Q=0). The N=l input enables the OR gate and it produces an output representing a l which triggers the flipflop 78 to the I state. The flip-flop 78 thereupon disables gate 38 and connects output terminal 60 of switch 50 to terminal 72. Capacitor 62 is now back in circuit and integrator 52 begins integrating at a rate determined by S.

When integrator 52 has integrated to the voltage +V,. the comparator 88 generates a pulse (T, FIG. 4) which sets monostable multivibrator 40 to the 1 state (Q, FIG. 4). The pulse from the 1 terminal, as explained earlier, primes the gates 260-261" and 28a-28f, whereby the flip-flops A'F' assume the same states as the flip-flops AF, respectively. This pulse (Execute Complete) is also coupled to the computer 2 informing it that the system is ready to generate another vector. The clock pulse at time t, is generated by computer 2 a fixed time delay after the Execute Complete pulse.

The signal from the 1 terminal of monostable multivibrator 40 also is coupled to OR-gate 80. When 0 changes to 1, OR- gate 80 again is enabled and resets flip-flop 78 to the 0 state (P changes to 0). Output terminal 60 of switch 50 is again connected to terminal 68 and the output signal level of integrator 52 again returns to V, causing the output of comparator 88 to return to a binary 0 level. The P=l output of fiip-flop 78 again primes AND-gate 38.

A short time later, monostable multivibrator 40 returns to its quiescent condition, that is the signal 6 at the 0 output terminal returns to a binary 1 level. This is the second priming signal for gate 38. A short time later at time t,, the next clock or start pulse occurs and AND-gate 38 becomes enabled. This starts the next cycle, M changes to l, monostable stage 82 becomes set, N changes to l and so on, all as described above.

FIG. 4 is a block diagram of the vector velocity control unit 12 (FIG. 1). This unit, as explained earlier, generates the voltage S which controls the rate of integration of integrator 52 (FIG. 2).

The X-registers 6 and Y-registers 8 are connected to subtractors 104 and 106, respectively. The output terminals from these subtractors are connected to a comparator 108 and

gates

110 and 112. The comparator 108 is also connected to the

gates

110 and 112 via lines 114 and 116, respectively.

The output terminals of

gates

110 and 112 are connected to the input terminals of

registers

118 and 120, respectively.

Registers

118 and 120 are connected to digital-to-analog (D/A)

converters

122 and 124, respectively, which are connected in the feedback path between input terminal 126 and output terminal 128 of an operational amplifier 130. The input terminal 126 is connected to a source of reference potential 132 through a resistor 134. The output terminal 128 is connected to the input terminal 136 of an inverter 138.

The X-registers 6, as explained earlier, are comprised of first (AF) and second (AF) registers (FIG. 2) 141 and 143, respectively. The Y-registers 8 are comprised of first and

second registers

145 and 147, respectively. The output signals from the X- and Y-registers are shifted in parallel into

subtractors

104 and 106, respectively, via the multiconductor cables shown as single leads in the drawing.

The subtractor 104 computes the absolute value of the difference in magnitude of the digits in registers 141 and 143 I AXl This computation is performed at a time shortly after the data in register 141 (A F) is shifted into register 143 (A F) and new data is shifted into register 141. Subtractor 106 operates on the data in

registers

145 and 147 in similar manner. The subtractors may be any of a number which are known in the art.

The lAX l and lAY signals produced are concurrently coupled, in parallel, via multiconductor cables, shown as single leads in the drawing, to comparator unit 108 and

gates

110 and 112. Comparators are well known in the art and one such binary comparator which may be used in the practice of this invention is described in Weinstein U.S. Pat. No. 3,251,035 assigned to the assignee of the instant invention.

Comparator 108 when comparing lAX I and lAYI produces one of three signals: (1) lAXl lAYl (2) lAYI lAXl; or (3) lAXl IAYl at a given time. These signals are coupled via multiconductor cables 114 and 116, shown as single leads in the drawing, to

gates

110 and 112, respectively.

Gates

110 and 112 are detailed in FIG. 5. Gate 110 comprises inverter 140, AND-

gates

142 and 144, and OR-gate 146. Gate 112 comprises inverter 148, AND-

gates

150 and 152, and OR-gate 154.

The signals lAXl AYl and lAXl=lAYl produced by comparator 108 are coupled serially to first and second input terminals of an OR-gate 156. If either or both of these signals are at a binary 1 level a binary 1 signal is produced at the output terminal 158. If both signals are concurrently at a binary level a binary 0 signal is produced at terminal 158.

The signal produced at terminal 158 is concurrently coupled to

gates

110 and 112. In gate 110 the signal is coupled to terminal 160 of AND-gate 142 and the input terminal of the inverter 140. Applied to the second input terminal of gate 142 is the AXl signal. The output terminal of inverter 140 is connected to the first input terminal of gate 144, and applied to the second input terminal is lAYI In gate 112 the signal produced at the output terminal of gate 158 is coupled to terminal 162 of AND-gate 150 and the input terminal of inverter 148. Applied to the second input terminal of gate 150 is the lAYl signal. The output terminal of inverter 148 is connected to the first input terminal of gate 152, and applied to the second input terminal is lAX I.

Assume that lAX zlAYl therefore, a binary 1 is produced at terminal 158 of gate 156. This signal primes ANDgate 142 in 110 and AND-gate 150 in 112. Inverters 140 and 148 produce binary 0 signals at their respective output terminals in response to the binary 1 input signal. AND-

gates

144 and 152,

therefore, are disabled. Gate 142, therefore, transmits the lAX l signal to OR-gate 146 which transmits the lAXl signal to register 118 (FIG. 4). Gate 150 transmits the IAYI signal to register 120 (FIG. 4). Assume now that lAXl IAYI This condition produces a binary 0 signal level at the terminal 158 of gate 156. This signal disables AND-

gates

142 and 150. Inverters 140 and 148 produce binary 1 signals at their respective output terminals in response to the binary 0 input signal. AND-

gates

144 and 152, therefore, are primed. Gate 144 transmits the lAYl signal to vOR-gate 146 which transmits the lAY l signalto register 118 (FIG. 4). Gate 152 transmits the lAX l signal to gate 154 which transmits thel AX l signal to register 120 (FIG. 4).

4) stores'lAXl iflAXl lAYl or stores lAYl if |AYllAXl,

and that register 120 (FIG. 4) stores lAYl if lAYllAXI or stores .IAXl if lAXl IAYI For the remainder of the discussion assume that lAXl lAYl therefore, lAXl is stored in register 118 and lAYl is stored in register 120.

It is clear that

gates

110 and 112 are designed to receive lAXl and lAYl binary data serially. If, however, lAXl and IAYI binary data are to be shifted into

gates

110 and 112 in parallel, there would be a

gate

110 and 112 for each bit. For example, if the lAXl and lAYI signals each comprise three bits, there would be three gates 110 and three gates 112.

Returning to FIG. 4, lAX l signal is shifted in parallel, over a multiconductor cable shown as a single lead, from register 118 to digital-to-analog (D/A) converter 122. The lAYl signal is shifted in parallel, over a multiconductor cable shown as a single lead, to D/A converter 124.

If AP is the vector length, it is known that AP= KX+A 1'. It can be shown that if the integrator 52 (FIG. 2) integrates at a rate proportional to HA! all vectors are drawn at a constant velocity.

The vector velocity control unit 12 (FIG. 4) approximates l/AP by one of the following equations.

Since it has been assumed that lAXl lA YI equation (1) is to be used in the remainder of the discussion. It can be shown that this equation approximates l/AP to within less than fl percent.

The D/A converter 122 which converts AX from digital to analog is designed to have an impedance The D/

A converters

122 and 124 are in the feedback path of operational amplifier 130. The standard transfer function of an operational amplifier is:

(5) E0=Ein R /R. Ein is the reference voltage at 132, R, is resistor 134, and as was stated above, R is the parallel combination of D/

A converters

122 and 124. Therefore. R is expressed by the equationz It is clear from the discussion above that register 118 (FIG.

9 RTKR 2.5RTK R IAX IA Y RF -T R K 2.5R A

l l an 5 R 2.5R K F !A |+2- iA Substituting Equation (6) in (5) l (7) E EL-7L2.5RTKR 1 R. |9 L It may be seen that the term in the parenthesis is the approximation of l/ P as set forth in equation l l The following explanation should make it clear that if the voltage described in equation (7) is applied via inverter 138 to integrator 52 (FIG. 2), all vectors are drawn at a substantially constant velocity. The voltage S applied to the integrator 52 is: s) -Em2.5RTKR Rt'n AP For ease of explanation let:

(9) Ein2.5R -K (Rin) l Therefore, substituting (9) in (8) 10) -S K /AP The output signal from integrator 52 (FIG. 2) is, therefore:

. 9 MAP Tilf- The output signal from horizontal amplifier 48, which is the horizontal component of the vector is:

(12) KPT/A.P(..AX2.

The output signal from the vertical amplifier which is the vertical component of the vector is: (13) K RZAPMlQ The resultant vector AP is:

14 a 2 AP: eggs if Ail f? 7 since AP VAX AY The velocity of the vector is the derivative of the magnitude of the vector with ewesttsafimsithersf (15) ..--EL!'FY HEM.

This shows that the velocity of the vector AP-isjalconstant 'for all vectors drawn, when the voltage AS is'proportional to A vector generator has been described which dperates in a constant time or at a constant velocity.

Since S=K /AP, the greater in' magnitude ,AP is,the smaller in value S is. It follows; therefore,-that-a long vector is generated in a. longer time. than a short vector as S controls the rate of integ ration of.integrator 52 (FIG. 2).

Referring to FIG. 3, it may be seen that if the system operates at a constant velocity, the output ramp signal R from 0 integrator 52 (FIG. 2) does not occur at a fixed time interval as shown. This in turn produces an Execute Complete signal (Q) (FIG. 3) at varying time intervals. Hence, the system operates on an aperiodic basis.

What is claimed is:

1. In combination:.

means for concurrently producing four waves, namely first and second direct-current levels, a first ramp extending from said first to said second level, and a second ramp extending from said second to said first level;

means for generating during successive time intervals successive groups of signals, each such group of signals representing a multiple digit binary number;

means responsive to said groups of signals generated in two succeeding time intervals for comparing the value of cor- 5 responding signals in each group;

means responsive to said comparing means for selectingior each said signal pair one of said four waves, the selection depending on the presence or absence of change and the direction of change; and

means for producing a sum signal comprising means for adding with different weights the selected waves.

2. The combination as set forth in claim 1, wherein the means for adding includes means for adding the selected waves with weights, in each case, proportional to the power of two represented by the signal calling for said wave.

3. The combination set forth in claim 1, including means for generating said sum signal at a constant rate.

4. The combination set forth in claim 1, including means for generating said sum signal in a constant time.

5. In a stroke generator the combination comprising:

means for concurrently producing four waves, namely first and second direct-current levels, a first ramp extending from said first to said second level, and a second ramp extending from said second to said first level; means for generating first and second groups of signals representing multiple digit binary numbers which define the terminal point of a stroke, each binary number being capable of changing its value during successive time intervals, said groups of signals changing correspondingly;

means responsive to each group of signals, for selecting for each signal in said group, one of said four waves, depending upon the value of the binary digit represented by the signal and whether or not it has changed value during the preceding time interval; and means for generating for each pair of binary numbers defining a terminal point of a stroke, first and second deflection waveforms, comprising means for adding together the waves selected for one binary number with weights, in each case, proportional to the power of two represented by the respective waves, and means for adding together the waves selected for the other binary number of the pair, in similar fashion. 6. The combination claimed in claim 5, further including four switch means for each signal in each group for selecting one of said four waves.

7. The combination claimed in claim 6, said means responsive to each group of signals comprising for each signal in each group a first and second means, each capable of assuming one of two states, the first means assuming at the beginning of each interval one state if the signal represents one binary value and assuming the second state if the signal represents the other binary value, the second means assuming the state of the first means at a time slightly before the end of a time interval, said first and second means controlling the selection made by said four switch means.

8. In a line generator the combination comprising: means for generating first and second groups of signals representing multiple digit binary numbers which define the terminal point of a line, each binary number being capable of changing its value during successive time intervals, said groups of signals changing correspondingly;

means for concurrently generating four waves, namely first and second direct-current levels, a first ramp wave extending from said first to said second level, and a second ramp wave extending from said second to said first level;

first and second means, for each signal in each of said groups, each capable of assuming one of two states, said first means assuming at the beginning of each interval one state if the signal represents one binary value and assuming the second state if the signal represents the other binary value, the second means assuming the state of the first means at a time slightly before the end of the time interval;

four switch means for each signal in each group for selecting one of said four waves, the states of said first and second means controlling the selection made by said switches; and

means for generating first and second deflection waveforms comprising means for adding, with weights proportional to the power of two represented by the signal calling for the selected wave in each group of signals.

Patent No. 3,633 21 mama January 25 192 2 Invent0 Howard Mulder Scott 82 Carl Rutherford Carson It is certified that error appears in the above-identified patent and that said Letters Patent are hereby cetcre'cted as shown beln'w':

Column line 15 "1/ P" should be l/AP Coiumn 9, line 19 should be -S Column 9, line 36 "KV'R" should be KVT Columm line 51 "3" should be -5 Signed and sealed this 29th day of May 1973 (SEAL) Attes't 2 EDWARD M.FLETCHER,JR. ROBERT GOTTSCHALK Attestlng Officer Commissioner of Pateniis a FORM Po-1o50(1 0- 59) USCOMWDC eosnhpfl E 3535 lyz a us. GOVERNMENT PRINTING erelcez 1959 oaes-3a' 1

Claims

1. In combination: means for concUrrently producing four waves, namely first and second direct-current levels, a first ramp extending from said first to said second level, and a second ramp extending from said second to said first level; means for generating during successive time intervals successive groups of signals, each such group of signals representing a multiple digit binary number; means responsive to said groups of signals generated in two succeeding time intervals for comparing the value of corresponding signals in each group; means responsive to said comparing means for selecting for each said signal pair one of said four waves, the selection depending on the presence or absence of change and the direction of change; and means for producing a sum signal comprising means for adding with different weights the selected waves.

5. In a stroke generator the combination comprising: means for concurrently producing four waves, namely first and second direct-current levels, a first ramp extending from said first to said second level, and a second ramp extending from said second to said first level; means for generating first and second groups of signals representing multiple digit binary numbers which define the terminal point of a stroke, each binary number being capable of changing its value during successive time intervals, said groups of signals changing correspondingly; means responsive to each group of signals, for selecting for each signal in said group, one of said four waves, depending upon the value of the binary digit represented by the signal and whether or not it has changed value during the preceding time interval; and means for generating for each pair of binary numbers defining a terminal point of a stroke, first and second deflection waveforms, comprising means for adding together the waves selected for one binary number with weights, in each case, proportional to the power of two represented by the respective waves, and means for adding together the waves selected for the other binary number of the pair, in similar fashion.

6. The combination claimed in claim 5, further including four switch means for each signal in each group for selecting one of said four waves.

8. In a line generator the combination comprising: means for generating first and second groups of signals representing multiple digit binary numbers which define the terminal point of a line, each binary number being capable of changing its value during successive time intervals, said groups of signals changing correspondingly; means for concurrently generating four waves, namely first and second direct-current levels, a first ramp wave extending from said first to said second level, and a second ramp wave extending from said second to said first level; first and second means, for each signal in each of said groups, each capable of assuming one of two states, said first means assuming at the beginning of each interval one state if the sigNal represents one binary value and assuming the second state if the signal represents the other binary value, the second means assuming the state of the first means at a time slightly before the end of the time interval; four switch means for each signal in each group for selecting one of said four waves, the states of said first and second means controlling the selection made by said switches; and means for generating first and second deflection waveforms comprising means for adding, with weights proportional to the power of two represented by the signal calling for the selected wave in each group of signals.