US3725897A

US3725897A - Visual display system

Info

Publication number: US3725897A
Application number: US00107930A
Authority: US
Inventors: M Bleiweiss
Original assignee: Raytheon Co
Current assignee: Raytheon Co
Priority date: 1971-01-20
Filing date: 1971-01-20
Publication date: 1973-04-03
Anticipated expiration: 1990-04-03

Abstract

A constant writing rate vector generator capable of accepting digital inputs representative of the endpoints of a line and converting them into analog voltages proportional to the transition time of the generated line such that random positioning of the electron beam on a cathode ray tube and the writing of vectors while maintaining an equal and constant brightness without additional intensity compensation is achieved. The digital endpoint data controls a constant voltage ramp with a time duration directly proportional to the vector length, which ramp is used to control the transition rate of a pair of digital to analog converters.

Description

United States Patent Apr. 3, 1973 Bleiweiss [54] VISUAL DISPLAY SYSTEM [75] Inventor: Mark H. Bleiweiss, Marlboro, Mass.

[73] Assignee: Raytheon Company, Lexington,

Mass.

[22] Filed: Jan. 20, 1971 [21] Appl. N0.: 107,930

[52] US. Cl. ..340/324 A, 235/151, 315/18,

[51] Int. Cl. ..G06t 3/14 [58] Field of Search ..340/324 A; 328/183, 185; 315/18, 26; 235/151 [5 6] References Cited UNITED STATES PATENTS Primary Examiner-David L. Trafton AttrneyMilton D. Bartlett, Joseph D. Pannone, Herbert W. Arnold and David M. Warren [57] ABSTRACT A constant writing rate vector generator capable of accepting digital inputs representative of the endpoints of a line and converting them into analog voltages proportional to the transition time of the generated line such that random positioning of the electron beam on a cathode ray tube and the writing of vectors while maintaining an equal and constant brightness without additional intensity compensation is achieved. The digital endpoint data controls a constant voltage ramp with a time duration directly proportional to the vector length, which ramp is used to control the transition rate of a pair of digital to analog 3,320,409 /1967 Larrowe ..340/324 A X onverter 3,482,309 12/1969 Bouchard ...340/324 A X I 3,325,802 6/1967 Bacon ..340/324 A 4 Claims 7 Drawin Fi ures 2a [2 r N n I N n 3 t X0 X E Z Xon X0 (XODVOVUREOZ X V l-,,. -Xo il a) 'REcIsTER D/A a f t X susgAcrIoN Axojzmorrxm) SUMQING \OUT( '):)(AU-tqV) N WORK me illx CHANNEL ,XOUXIDWD AMPLIFIER N 22 X I DVI M 12 5 /4 X v 'c I I In ref 11 R IsT R /A 2 g 56 x 2" D 1A Q C(Y lS"TlWT RKTE UIW-I" I GENERATOR I q LENGTH V t) CALCULATOR RAMP I l INVERTER V (t) DISPLAY z I Ax +AY GENERATOR I rer" 0 3 I LUD 42 I E I 48 I 52 0 N 0 l6 n i E L, "I x 'n o Yln Y1 Y V ttl-Y REGISTER D/A suBTRAcrIoN N Y NETWORK SUMMING Y CHANNEL lip- D|=AYD AY i2 (Y -AMRI IFIER our oA E 24 34 lAT 1a t l Y YO OD d QA TI REGISTER l N W 4 Z'W PATEi-HWAPM m5 SHEET 5 0F 5 304 m o wom qzo C F l|.| :9: m3 M936 VISUAL DISPLAY SYSTEM BACKGROUND OF THE INVENTION This invention relates to graphic visual display systems and more particularly to a vector generator suitable for use in a computer controlled stroke or vector generation system. Computer controlled stroke generating systems utilizing cathode ray tubes of the prior art have inherent inaccuracies resulting from variable writing speeds, and require brightness compensat-' ing circuits to compensate for the reduced illumination produced by long vectors which must be written in the same time as short vectors. It is therefore desirable to write at a constant rate, independent of vector length to eliminate compensating circuitry and to improve overall system accuracy when many strokes must be generated.

A constant writing rate vector generator is disclosed by patent Ser. No. 3,482,086 to CF. Caswell and assigned to the same assignee as the present application. Constant writing rate is achieved by means of an errorrate processor which developes an error voltage function in orthogonal axes. These orthogonal X and Y error voltages are summed in quadrature, normalized and separated into X and Y components to develop a continuous calculation for the composite error voltage. In the present application, digital endpoint data is coupled directly from a computer to derive an approximate length calculation which controls a ramp generator to generate control voltages proportional to the vector length. The charging and discharging of a bank of hinary weighted capacitors generates the required ramp function, and the balanced modulators and demodulators, the normalization circuitry and the error processor of Caswell is eliminated.

SUMMARY OF THE INVENTION The above and other features and advantages of the present invention are achieved by the provision of a constant writing rate vector generator in which digital endpoint data in two orthogonal axes is coupled directly from a computer or interface circuitry to a vector length calculator and to a pair of data decoders which determine the vector direction and endpoints. A constant rate ramp generator comprising a plurality of binary weighted and digitally controlled capacitors generates a constant voltage ramp with a time duration directly proportional to the vector length. The ramp is used as a reference for a pair of digital-to-analog converters in each axis to directly control the transition rate of the digital-to-analog converter, thereby providing analog outputs controlling the constant transition rate proportional to the vector length between the vector coordinates.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an operational block diagram of a stroke generator in accordance with the present invention;

FIG. 2 is a diagram of several of the outputs of the circuitry described by FIG. I for one axis;

FIG. 3 is a block diagram of the vector length calculator of the present invention;

FIG. 4 is a block diagram of an embodiment of the stroke generator of the present invention;

FIG. 5 is a simplified circuit diagram of the ramp generator employed in the embodiment illustrated by FIG. 4;

FIG. 6 is a simplified circuit diagram of the switching circuitry employed with the ramp generator of FIG. 5; and

FIG. 7 is a waveform diagram of the timing waveforms required to interface the stroke generator of the present invention with a central computer.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, a vector generator is illustrated generally at 10 which has the capability of accepting digital inputs representing the end points of a line and converting them into analog voltages representing the transition or writing time of the line. Equal and constant brightness without intensity compensation with random positioning of the electron beam is achieved.

Positional data from a central computer or data on input lines such as telephone lines is inputted to the vector generator 10 via data lines l2, l4, l6 and 18 to two X axis positional storage registers x and

X

20 and 22, respectively, and to two Y axis positional storage registers Y and Y,, 24 and 26, respectively. The positional data inputted to registers 20 through 26 comprises the X and Y line end point data in digital form. The outputs of

X registers

20 and 22 are fed to digitalto-

analog converters

28 and 30 respectively, the analog outputs of which are summed in an X position summing amplifier 32. Similarly, the outputs of

Y registers

24 and 26 are fed to digital-to-

analog converters

34 and 36, respectively, the analog outputs of which are summed in a Y position summing amplifier 38. The X and Y summing amplifier outputs supply constant rate transition signals to the electron beam deflection circuitry of a CRT at a constant writing rate as will be described with reference to FIG. 4 (calculator) 40 for positioning the electron beam in the X and Y axes.

The line length is calculated from the digital end points in a length calculator network 42 which is supplied with the changes in the X and Y end point coordinate data from subtraction networks 44 and 46, respectively, which provide the absolute values of the X and Y line variations. The hypotenuse calculation performed in calculating network 42 is used to directly control the transition time or the time required to generate a ramp voltage between two predetermined limits, one of which is zero and the other of which is a reference voltage Vr in a ramp generator 48. The length calculator 42 and ramp generator 48, taken together, comprise the constant rate line generator 50, which will be described in detail, particularly with reference to FIG. 3.

The output of ramp generator 48, which represents the signal periodicity, or the stroke time duration, is coupled through an inverter 52 to the X and Y initial condition digital-to-

analog converters

28 and 34 and directly to the digital-to-

analog converters

30 and 36 which receive the X and Y positional end point data for the conclusion of a stroke.

The digital end point data inputted to registers 20 through 26 generates an analog output positional signal representative of stroke length which is independent of the positioning of the previous stroke, thereby providing for random access operation. This is accomplished by multiplying the previous digital number X by zero (0) and the current number X, by a reference voltage Vr to obtain an output which equals X (0) X, (Vr), and (Y 0 Y, (Vr), or X, (Vr) and Y, (Vr). The current word then shifts to the X and Y registers and X and Y are inputted to the X, and Y, registers. Thus, X, and Y, are multiplied by zero, hence X, and Y, are also independent of the previous position.

Considering only the X channel, as the Y channel is identical, the ramp generator 48 is at zero (0) and the inverter 52 output is at Vr, therefore the output of register is a digital X and the output of'digitaI-toanalog converter 28 is X (0) 0; while the output of register 22 is a digital X, and the output of digital-to analog converter 30 is X, Vr f (X and the output of summing amplifier 32 is X, Vr, an analog signal represented as X At time t the first data pulse is loaded into register 20, and at time t,, the second data pulse is loaded into the X, channel. At time the third data pulse is transferred both to the X channel, and so forth. Mathematically, at time t=0, a digital word representing the initial stroke position in the X axis, X is loaded into the X register. This word, digitally is A new digital word representing the X, position,

is then loaded into the X, registers, with the ramp generator output equal to 0 (V, 0) and the inverter output V Vref. Therefore, the summing amplifier output X consists of the analog value X of the digital wordX (X,,,,, X The output of the line length calculator 42 sets the slope of the controlled ramp generator 48 such that the stroke transition time Yis directly Proportional to the line length L Referring nowto FIG. 2, a transition time diagram for stroke positioning in the X axis is illustrated. At time i=0, the ramp generator output V,(t), shown as curve A, increases from zero to the reference voltage, Vref while the inverter output, V,,(t), shown as curve B, decreases from Vrefto zero (0). Simultaneously, the X digital-to-analog converter output X V 0), shown as curve C, decreased from X, to 0 and the X, digital-toanalog output, curve D, increases from zero (0) to X, Thus, the final summing amplifier output X transfers from a first analog voltage X to a second analog voltage X,,, in a time (Y,,) which is proportional to the calculated vector line length Ly where:

Referring now to FIG. 3, the circuitry for implementing the vector line length calculation is illustrated. The length calculator receives, the vector end points in digital form, X X,, Y and Y,, and performs a mathematical computation to derive an approximation of the vector length, which approximation is used to directly control the ramp generator transition time for the ramp generator discussed with respect to FIG. 5. I

The vector end points X and X, are fed to a subtractor which derives the absolute digital value of the difference between X and X while simultaneously, the vector end points Y and Y, are fed to a subtractor 62 which derives the absolute digital value of the difference between Y and Y,. These values A X and A l are coupled to gating circuitry 64 and to a comparator 66 where the relative magnitudes of A X and A Y are compared. [f A X is greater than or equal to A Y, A Y is gated into the shift register 68 where it is multiplied by one-half and A X is gated directly to an adder 70. Thus, when A X is greater than or equal to A Y, the quantities A Y and A X are inputted to adder 70. If A l is greater than A X, A X is gated into the shift register 68 where it is multiplied by one half and A Y is gated directly to the adder 70. Thus, when A Y is greater than AX, the quantities A A X and A Y are inputted to adder 70.

The above-derived quantities comprise an approximation of the Pythagorean quantity VX 7 and the relationship may be expressed generally as:

The error due to this approximation is a function of the vector angle, which results in a worst case brightness deviation of approximately plus or minus 6 percent which is imperceptable to the viewing eye.

The calculated approximate vector length, either A X k A Yor A Y+ it A X is coupled to a storage register 72 from where it is coupled in a binary sequence to the ramp generator 48 described with reference to FIG. 5.

Referring now to FIG. 4, a stroke generator embodying the present invention is shown generally at 100. Digital inputs representative of vector end points are coupled from a central computer (not shown) to data storage registers for the X and Y axes via lines 102 and 104, respectively. The data storage registers which receive the X axis endpoint data are ten bit storage registers 106 and 108, with register 106 receiving the vector starting point data and register 108 receiving the vector end point data in the X axis. Similarly, for the Y axis, 10 bit storage registers 110 and 112 receive the Y axis starting and end point data respectively. A total of 40 bits of X and Y starting and endpoint data is received, with additional bits for blanking, unblanking and intensity, bringing the total required digital input to 43 bits per stroke. The X and Y endpoint data is transferred to the length calculator and to the X and Y axis data decoders 114 and 116, respectively. One bit unblanking signals are coupled from the computer to a one bit storage register, the Z register 1 18 to unblanking logic 120, which is a series of AND/OR gates of conventional design, the output of which is coupled to the video circuitry of a CRT display in a conventional manner. The length calculator determines the vector length while the data decoders determine the vector endpoints and direction.

The output of the length calculator 42 is coupled to a constant rate ramp generator 122 which generates a constant voltage ramp with a time duration directly proportional to the vector length. This ramp voltage is used as a reference for a pair of differential digital-

toanalog converters

124 and 126 for the X axis and Y axis respectively; hence, the transition rate of these D/A converters is controlled by the constant rate ramp generator and by the output of an inverter 128 which supplies the inverted output of ramp generator 122, a negative going ramp, to the digital-to-

analog converters

124 and 126, The outputs of the digital-to-

analog converters

124 and 126, which represent the coordinates of the generated vector, are generated for a time proportional to the vector length, i.e., the vector transition rate is constant; hence, the CRT brightness of a display 128 is constant. The X and Y D/A outputs are coupled to X and Y deflection amplifiers (not shown) in the display, while the Z output, or unblanking signal, is coupled via line 130 to the video amplifier of the display.

The vector generator control logic circuitry 132 interfaces a central computer and couples the required timing and control signals to and from the computer to the X and Y registers and to the ramp generator.

Referring now to FIG. 7, the waveform timing diagram illustrates the various timing pulses required. The basic system timing is provided by a 100 nanosecond clock illustrated by waveform (a) of FIG. 7. A data available signal is sent from the computer to the logic 132 whenever the interface circuitry is ready to accept data and when the vector generator is not busy generating previous vectors. This signal, illustrated by waveform (d) is present when an control counter of conventional design has counted to L9 microseconds.

When the data available signal goes high, an internal state counter with a 100 nanosecond clock initiates data storage and timing signals for the arithmetic length calculation. Waveform (e) illustrates 19 states for the control counter; however, other states may be added or omitted as desired.

When the vector generator is processing or writing, a busy signal illustrated by waveform (c) goes high on the first clock pulse after a data available" signal goes low on the trailing edge of a 100 nanosecond end of stroke signal illustrated by waveform (b) indicating the end of a vector. New vector generation data cannot be entered while the busy" signal is high. The end of stroke pulse of waveform (b) signals the end of a vector when the vector is completed. This pulse may be generated by a comparator operating in conjunction with a digital one shot multivibrator to generate the 100 nonosecond pulse.

' A toggle signal illustrated by waveform (j) toggles on every end of stroke signal to distinguish between successive vectors. This distinction is required since the digital-to-analog converters require that the timing of one vector is determined by a positive going ramp and the timing of the next vector is determined by a negative going ramp, both of which ramps require different control signals. When the next data available" signal is received from the computer, the toggle signal switches from high to low, and during successive states of a conventional state counter, data is strobed into A registers and B registers, the X and Y start registers and the X and Y end registers, the timing of which is illustrated by waveforms (k) and (1), respectively. Also, the high and low pulses for charging the binary weighted capacitors of the ramp generator via the initializing transistors, as described with reference to FIG. FIG. 5, are generated on the control count after data is strobed into the X and Y registers as illustrated by waveforms (m) and (n Thus, if on control count 1, data is strobed into the X and Y start registers, on the rising edge of control count 2, the charge capacitors high signal of waveform (m) goes high, thereby insuring that all the capacitor are charged to a fixed positive reference voltage and ready to be linearly discharged causing a negative going ramp. The current switch is enabled and goes high to provide negative current to the positively charged binary weighted capacitors in the proper sequence. This pulse is shown by waveform (g), and it is coupled to an FET switch as shown with reference to FIG. 5.

At the end of the counting sequence, the length calculation is completed and the analog circuitry is enabled to paint the derived vector. A ready signal, illustrated by waveform (h), is derived from the decoders 1 l4 and 116 which is coupled from the logic 132 to the computer, which, upon receipt of the ready" signal, couples back to the logic a start signal illustrated by waveform (i) to paint the vector. The start" signal lowers the ready signal and resets the charge capacitors high signal thereby allowing the capacitors to discharge linearly to ground through the current switch. A length enable signal, waveform (f) is generated when the data available" signal is high to implement the vector length calculation.

Blanking of the cathode ray tube beam for vector segments not to be painted is accomplished by the coupling of a one bit blanking signal, either a logical one or a zero from the computer to the one bit storage register 118 for input to the unblanking circuits 132, where the unblanking pulse is conventionally processed in the unblanking logic 120 before coupling to the video circuits via line 130. Unblanking timing is provided by the outputs of two voltage comparators, one of which, comparator 134, detects when the generated ram exceeds zero (0) volts, and the other of which, comparator 136, detects when the generated ramp reaches the reference voltage Vr. The outputs of

comparators

134 and 136 are logically ANDed with the unblanking Z bit to produce the vector unblanking signal when the generated ramp is between zero (0) volts and the reference voltage Vr when the Z bit is a logical one.

The four-position switches 140 and 142 for the X and Y axes respectively, described with reference to FIG. 6 couple the decoded outputs of decoders 114 and 116 to the reference voltages and ramps whereby the appropriate voltage selection is made for coupling to the analog circuitry for generation of the required stroke deflection voltages.

The vector length approximation provided by the length calculator 42 is coupled to the ramp generator 122 to provide ramps with a time duration directly proportional to the calculated vector length, thus achieving constant writing speed. The vector endpoints determinative of the X position are coupled to subtractor 144 from the X start register 106 and the X end register 108, which subtractor derives the change in the vector position:

The Y position end points are coupled to subtractor 146 from the Y end point register 1 l2 and the Y start register 1 10 to obtain the change in vector length in the Y direction The outputs of

subtractors

144 and 146 are coupled to a comparator 148 where A X is compared with A Y and to two storage registers 150 and 152 in the X and Y axis respectively. If A Y is greater than or equal to AX, then A Y is coupled to register 150 and the quantity A X A A X) is derived. If A X is greater than A Y, then the output of comparator 148 is coupled to storage register 152 to derive quantity 1% A Y (A Y) and the outputs of both registers 150 and 152, which are conventional ten bit storage registers, is coupled to an adder 154 of conventional design in which the quantities:

AX+%AYforAX AY AY+%AXforAY z AX are derived and coupled to an ll-bit storage register 156 for storage prior to coupling to the ramp generator 122 to develop the generated ramp transition time.

The error due to this approximation is.a function of vector angle, and the worst case error is sufficiently small such that a worst case brightness deviation of plus or minus 6 percent results, which deviation is imperceptible to the human eye. I

Referring now to FIG. 5, the ramp generator is illustrated generally at 48. The ramp generator produces a linear voltage oiitput V (t) which is clamped at zero volts and at a reference voltage Vref. Of; course, the output could, if desired, be clamped to two different reference voltages. The ramp generator receives digital length data from the line length calculating network 42 via 10 lines, L, through L which length data enables or disables a bank of binary weighted capacitors, C, through C four of which are shown at 200, 202, 204 and 206. Of course, any number of digital length inputs, Ly to L may be used, with either more or less than 10 binary weighted capacitors. The binary weighting is 2C, 2C, 2 C Z C, with the enabled capacitance values being a function of vector length for effecting the determination of the transition time of the generated ramp in accordance with the following equatrons:

V0 (y) (I/Ct) y constant V and n) y Cl KiLv and y KLv where r= ramp transition time C, enabled capacitance K constant of proportionality Lv vector length Vr= reference voltage I constant current source Thus, the ramp output signal which equals V,(t],y) and its inversion V, [l (!/y)] are used as reference signals for the digital-to-analog converters. With the output V (t) clamped between two reference voltages, the transition time is proportional to the calculated line length in accordance with i =yk la The two alternative methods of making the transition time y proportional to the vector line length Lv are controlling I as a function of i 1/ W0 D) and controlling C as a function of VA X K Y The former is difficult to achieve since the computation .practical useful range of control may be extended beyond 100,000zl (50 pf to 5 mf). Therefore, this method of control is particularly suitable to a binary weighting system and increases the range of constant transition line lengths that can be generated.

Transistors

208 and 210 charge the binary weighted capacitors with either +V or -V while diode networks 212 through 218 provide binary selection. For a given vector length (Lv) digitally inputted in binary form at Lvl through Lvn, where n is 10, for example, the appropriate FET switches 220, 222, 224 and 226 will close, which represents the charge across the 10 capacitors, developing a total capacitance of C, where C =2 Lvo C+2 Lv1+ 2 Lv which may be generally expressed as where

Transistors

208 and 210 are initializing transistors which initialize the charge on the binary weighted capacitors before each stroke. Control signals from the logic network are supplied via lines 228 and 230 to the bases of

transistors

208 and 210 respectively, which signals turn the initializing transistors ON and OFF in accordance with the digital input, with a logical one being ON and a logical zero being OFF.

The outputs of the FET switches 220 through 226 are summed at node 232, which voltage is the analog representation of the total summed capacitance. the value of which is representative of the length of the stroke to be generated. This summed capacitance is coupled to a pair of alternately switched positive and negative current sources +l and l respectively, the switching being provided by a transistor switch 234 which is driven from the logic circuitry via line 236 to provide the output ramp function. The ramp is coupled through a buffer, such as an emitter follower 240,

which couples the high impedance input to two

low impedance comparators

242 and 244 of conventional design.

Comparators

242 and 244 compare the output of emitter follower 240 to a reference voltage Vr and to zero respectively, and

transistors

246 and 248 clamp the comparators to these values, thus comparing the clamping voltage with the ramp voltage. When the ramp voltage exceeds the compared voltage,

transistors

246 and 248 switch ON to hold the output within the clamping limits. The output of

comparators

242 and 244 are coupled to the blanking and unblanking circuitry respectively, and the ramp generator output appears at none 250.

Referring now to H6. 6, the decoder and four position switch is illustrated for the X axis generally at 260. As the Y-axis decoder and four position switch is identical, only the X-axis circuit is illustrated. The X axis decoder 260 compares each bit of the initial X position (Xs) with each bit of the final X position (Xe) in four

NAND gates

262, 2 64, 266 and 268 which receive their inputs from the X and X registers 106 and 108 via lines 270 through 276. The decoder output consists of four output lines for each bit of the input length, which lines are coupled through

emitter followers

278, 280, 282 and 284 to four

FET switches

286, 288, 290 and 292.

The four possible combinations which may be switched to the digital-to-analog ladder network 294 of which only a portion is shown, are:

X =X =0 X0 X l X0=0,X!=1 X0: l,X 0

This data is switched via

lines

296, 298, 300 and 302 respectively, and the activated line couples in one of the four reference signals into the leg of the digital-toanalog network 294 representing the value and weight of the decoded bit. The reference signals coupled via lines 298 and 300 are derived from the ramp generator 48 and invertor 52, and comprise the positive and negative going ramps Vr (t)/(1') and Vr [l (t/r)] respectively, while lines 296 and 302 couple zero volts and Vr respectively to the four position switch.

As is apparent on line 296, X O and X 0, therefore the starting and ending vector position are a logical 0, and the reference 0V is switched into the digital-to-analog leg.

When X 0 and X, I, that bit increases from 0" to 1 during the stroke transition time y, hence the rampgenerator reference output V0(t) Vr (t)/('r) is switched into the digital-to-analog leg via line 298.

When X 1 and X 0," that bit will decrease during the transition time y from l to O," hence the inverter reference output V0(t) Vr [l (t/1')] will be switched into the digital-to-analog leg via line 300.

Similarly, when X 1 and X l the starting and ending position for that bit are a logical l therefore, the reference voltage Vr is switched into the digital-to-analog leg via line 302.

It is apparent that the positive and negative going ramps and the two reference voltage levels are determinative of the stroke positioning in the X axis. While the D/A ladder is illustrated only for the X l and X 1 l condition, the other ladders are identical, and the composite output is summed in an X summing amplifier 304, from which the analog voltage Vx (r) X I /r)] X; (t/r) is applied to the X axis CRT deflection circuitry. Of course, the circuitry for the Y axis is identical, and the signal applied to the Y axis Y deflection circuitry is Vy (t) Y0 [(1 (t/r)] 1 (#1).

The digital-to-analog output is the binary weighted sum of each of the reference inputs as determined by the decoder NAND switches which establishes the amplitude change of the digital-to-analog converter. When a ramp is generated, digital-to-analog outputs produce the X and Y coordinates of the vector to be generated.

While particular embodiments of the invention have been shown and described, various modifications thereof will be apparent to those skilled in the art. For

example, alphanumeric characters may be generatedby expansion of the logic rather than vectors, and therefore it is not intended that the invention be limited to the disclosed embodiments or details thereof and departures may be made therefrom within the spirit and scope of the invention as defined in the appended claims.

What is claimed is: l. A visual display system comprising: means for generating digital vector end point data; means for converting said digital data to analog signals having a time duration that is directly proportional to the length of said vector; means coupled to said converting means for generating a visual display at a constant writing rate; means coupled to said means for generating digital vector end point data for generating stroke length data; means for generating a voltage ramp with a time duration directly proportional to said derived stroke length; means for switching said voltage ramp into said digital-to-analog converting means in accordance with said digital end point data such that a constant transition rate vector is generated on said visual display; and wherein said means for generating stroke length data comprises a hypotenuse approximation circuit which comprises: a first subtractor for subtracting the X component of a starting point of said vector from the X component of an end point of said vector; a second subtractor for subtracting the Y component of a starting point of said vector from the Y component of an end point of said vector; a comparator for comparing the outputs of said first and said second subtractors; first combining means responsive to an output of said comparator for providing an output equal to the sum of an output of said first subtractor with one-half the output of said second subtractor when the output of said second subtractor is greater than the output of said first subtractor; second combining means responsive to an output of said comparator for providing an output equal to the sum of an output of said second subtractor with one-half the output of said first subtractor when the output of said first subtractor is greater than the output of said second subtractor; and

means for coupling the output of said first combining means and the output of said second combining means to said ramp generating means, the output of said first combining means being the hypotenuse approximation when the output of said second subtractor is greater than the output of said first subtractor, the output of said second combining means being the hypotenuse approximation when the output of said first subtractor is greater than the output of said second subtractor. 2. A vector generator comprising: means for receiving digital vector end point data; meansfor converting said digital end point data into a digital quantity representative of the vector length; means for generating control voltages responsive to said digital quantity, the time duration of said control voltages being proportional to the vector length; digital-to-analog means for converting said control voltages to-analog signals in accordance with said digital end point data; means for displaying said analog signals as vectors at a constant writing rate; said means for receiving digital vector end point data comprising first and second storage registers for receiving vector starting point data and vector end point data for a first axis, said vector end point receiving means further comprising third and fourth storage registers for receiving vector starting point data and vector end point data for a second axis, said second axis being orthogonal to said first axis; said means for converting said digital end point data into a digital quantity representative of said vector length comprising: means for digitally approximating the function substituting therefor the quantity AX+VzA Y when AX AY and AY+%AX when AY z AX where A X is the absolute value of the difference between the vector end point and starting point in the X axis and A Y is the difference between the vector end point and starting point in the Y axis; and wherein said digital approximation means includes: first and second subtractors for deriving the quantities A X and A Y, from said first and second and said third and fourth storage registers, respectivey; a comparator for comparing the outputs of said first and second subtractors; first means for storing the output of said comparator when A Y .2 A X;

second means for storing the output of said comparator when A X A Y;

means for adding the outputs of said first and second storage registers to derive said digital approximation; and

means for storing said digital approximation.

3. In combination:

means for receiving components of data of a vector to be displayed, said data having an X component and a Y component of a start point of said vector, and said data having an X component and a Y component of an end point of said vector;

means for generating a ramp signal, said ramp generating means including means for inverting said ramp signal;

means coupled to said data receiving means and said ramp generation means for multiplying said start point data and said end point data by respectively said inverted ramp signal and said ramp signal;

means coupled to said multiplying means for combining output signals of said multiplying means for displaying said vector;

a hypotenuse approximation circuit coupled to said ramp generation means for varying the rate of change of said ramp signal, said hypotenuse ap proximation circuit comprising: first and second subtractors for deriving the quantities A X and A Y from said X and said Y component of said start point and said X and Y component of said end point;

a comparator for comparing the outputs of said first and said second subtractors;

first means coupled to said comparator for obtaining one-half the output of said first subtractor when A Y a A X;

second means coupled to said comparator for obtaining one-half the output of said second subtractor when A X A Y;

means for adding the outputs of said first and said second subtractors to the outputs of said first and said second obtaining means to derive a signal having a value approximating a hypotenuse from said start point to said end point.

4. In a system employing a ramp generator for generating a display of vectors each of which are drawn from a start point to an end point, the start point and the end point each being described by an X component and a Y component, a hypotenuse approximation circuit coupled to the ramp generator for varying the rate of change of ramp signals provided by said ramp generator, said hypotenuse approximation circuit comprising:

first and second subtractors for deriving the quantities A X and A Y from said X components and said Y components of said start and said end points;

a comparator for comparing the outputs of said first and said second subtractors; first means coupled to said comparator for obtaining one-half the output of said first subtractor when A Y AX;

means for adding the outputs of said first and said ing a value approximating a hypotenuse from said second subtractors to the outputs of said first and start point to said end point. said second obtaining means to derive a signal hava

Claims

1. A visual display system comprising: means for generating digital vector end point data; means for converting said digital data to analog signals having a time duration that is directly proportional to the length of said vector; means coupled to said converting means for generating a visual display at a constant writing rate; means coupled to said means for generating digital vector end point data for generating stroke length data; means for generating a voltage ramp with a time duration directly proportional to said derived stroke length; means for switching said voltage ramp into said digital-toanalog converting means in accordance with said digital end point data such that a constant transition rate vector is generated on said visual display; and wherein said means for generating stroke length data comprises a hypotenuse approximation circuit which comprises: a first subtractor for subtracting the X component of a starting point of said vector from the X component of an end point of said vector; a second subtractor for subtracting the Y component of a starting point of said vector from the Y component of an end point of said vector; a comparator for comparing the outputs of said first and said second subtractors; first combining means responsive to an output of said comparator for providing an output equal to the sum of an output of said first subtractor with one-half the output of said second subtractor when the output of said second subtractor is greater than the output of said first subtractor; second combining means responsive to an output of said comparator for providing an output equal to the sum of an output of said second subtractor with one-half the output of said first subtractor when the output of said first subtractor is greater than the output of said second subtractor; and means for coupling the output of said first combining means and the output of said second combining means to said ramp generating means, the output of said first combining means being the hypotenuse approximation when the output of said second subtractor is greater than the output of said first subtractor, the output of said second combining means being the hypotenuse approximation when the output of said first subtractor is greater than the output oF said second subtractor.

2. A vector generator comprising: means for receiving digital vector end point data; means for converting said digital end point data into a digital quantity representative of the vector length; means for generating control voltages responsive to said digital quantity, the time duration of said control voltages being proportional to the vector length; digital-to-analog means for converting said control voltages to analog signals in accordance with said digital end point data; means for displaying said analog signals as vectors at a constant writing rate; said means for receiving digital vector end point data comprising first and second storage registers for receiving vector starting point data and vector end point data for a first axis, said vector end point receiving means further comprising third and fourth storage registers for receiving vector starting point data and vector end point data for a second axis, said second axis being orthogonal to said first axis; said means for converting said digital end point data into a digital quantity representative of said vector length comprising: means for digitally approximating the function Square Root ( Delta X)2 + ( Delta Y)2 substituting therefor the quantity Delta X + 1/2 Delta Y when Delta X > Delta Y and Delta Y + 1/2 Delta X when Delta Y > or = Delta X where Delta X is the absolute value of the difference between the vector end point and starting point in the X axis and Delta Y is the difference between the vector end point and starting point in the Y axis; and wherein said digital approximation means includes: first and second subtractors for deriving the quantities Delta X and Delta Y, from said first and second and said third and fourth storage registers, respectively; a comparator for comparing the outputs of said first and second subtractors; first means for storing the output of said comparator when Delta Y > or = Delta X; second means for storing the output of said comparator when Delta X > or = Delta Y; means for adding the outputs of said first and second storage registers to derive said digital approximation; and means for storing said digital approximation.

3. In combination: means for receiving components of data of a vector to be displayed, said data having an X component and a Y component of a start point of said vector, and said data having an X component and a Y component of an end point of said vector; means for generating a ramp signal, said ramp generating means including means for inverting said ramp signal; means coupled to said data receiving means and said ramp generation means for multiplying said start point data and said end point data by respectively said inverted ramp signal and said ramp signal; means coupled to said multiplying means for combining output signals of said multiplying means for displaying said vector; a hypotenuse approximation circuit coupled to said ramp generation means for varying the rate of change of said ramp signal, said hypotenuse approximation circuit comprising: first and second subtractors for deriving the quantities Delta X and Delta Y from said X and said Y component of said start point and said X and Y component of said end point; a comparator for comparing the outputs of said first and said second subtractors; first means coupled to said comparator for obtaining one-half the output of said first subtractor when Delta Y > or = Delta X; second means coupled to said comparator for obtaining one-half the output of said second subtractor when Delta X > Delta Y; means for adding the outputs of said first and said second subtractors to the outputs of said first and said second obtaining means to derive a signal having a value approximating a hypotenuse from said start point to said end point.

4. In a system employing a ramp generator for generating a display of vectors each of which are drawn from a start point to an end point, the start point and the end point each being described by an X component and a Y component, a hypotenuse approximation circuit coupled to the ramp generator for varying the rate of change of ramp signals provided by said ramp generator, said hypotenuse approximation circuit comprising: first and second subtractors for deriving the quantities Delta X and Delta Y from said X components and said Y components of said start and said end points; a comparator for comparing the outputs of said first and said second subtractors; first means coupled to said comparator for obtaining one-half the output of said first subtractor when Delta Y > or = Delta X; second means coupled to said comparator for obtaining one-half the output of said second subtractor when Delta X > Delta Y; means for adding the outputs of said first and said second subtractors to the outputs of said first and said second obtaining means to derive a signal having a value approximating a hypotenuse from said start point to said end point.