US3576434A - Addressing circuit - Google Patents

Addressing circuit Download PDF

Info

Publication number
US3576434A
US3576434A US707532A US3576434DA US3576434A US 3576434 A US3576434 A US 3576434A US 707532 A US707532 A US 707532A US 3576434D A US3576434D A US 3576434DA US 3576434 A US3576434 A US 3576434A
Authority
US
United States
Prior art keywords
transformers
group
windings
winding
transformer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US707532A
Other languages
English (en)
Inventor
Alfons Reszka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Teletype Corp
Original Assignee
Teletype Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teletype Corp filed Critical Teletype Corp
Application granted granted Critical
Publication of US3576434A publication Critical patent/US3576434A/en
Assigned to AT&T TELETYPE CORPORATION A CORP OF DE reassignment AT&T TELETYPE CORPORATION A CORP OF DE CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). EFFECTIVE AUG., 17, 1984 Assignors: TELETYPE CORPORATION
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/02—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using magnetic or inductive elements

Definitions

  • a transformer-coupled memory addressing cir- 9 Claims, 1 Drawing Fig cuit uses first and second groups of addressing transformers with each addressing input being applied to the primary wind- [52] U.S. Cl 235/154, ing f one f h transformers of the first group and all but one 340/347 of the primary windings of the second group.
  • Each primary [51 I [1!- Cl H03k13/247 i ding of each transformer of [he first group links a plurality [50] Field of Search 340/166, f secondary windings equal in number to the number f 347; 235/154 transformers in the second group.
  • Each of the primary winding sheets is encoded to represent a different word of character, and whenever a particular primary winding sheet is supplied with an input signal, a signal corresponding to this word or character is induced in the secondary windings of the transformers and may be utilized by any suitable device connected to the output of the memory.
  • the windings are printed on a sheet of insulating material of a suitable plastic, such as Mylar," and it has been necessary to connect the end terminals of the primary winding conductor sheets to the input signal source by means of direct electrical connections.
  • a sheet is replaced in order to change the information stored in the memory, it is necessary to sever these connections and to make new connections with a newly inserted sheet bearing the new information placed in the memory.
  • an input amplifier generally is required for each of the primary winding sheets in a direct-wired memory of this type; so that if the memory is utilized to decode a large number of words, a correspondingly large number of input amplifiers are required.
  • the addressing circuit for the printed primary windings of a plurality of memory transformers consists of first and second groups of addressing transformers with each addressing input being applied to the primary winding of one of the transformers of the first group and being applied to all but one of the primary winding of the second group.
  • Each primary winding of each transformer of the first group links a plurality of secondary windings equal in number to the number of transformers in the second group.
  • Each of the secondary windings of the first group then is connected in series with a secondary winding from a different transformer in the second group, and the windings are arranged such that current induced in the secondary windings of the first group opposes current induced in secondary windings of the second group.
  • Each set of seriesconnected windings then is connected to the end terminals of the printed primary windings of a different primary winding sheet in the memory transformers. This can be accomplished by printing the series-connected secondaries on the same sheets as the primary windings of the memory transformers. Only when a secondary winding of the first group has current induced in it, in the absence of current induced in its seriesconnected winding of the second group, does current flow through the printed primary winding of the corresponding sheet in the memory transformer.
  • FIGURE of the drawing is a schematic diagram of an addressing circuit made in accordance with a preferred embodiment of the invention.
  • a -decoder circuit 10 which may be of anysuitable type; such as a circuit for converting permutation-coded input signals to digital output signals.
  • the decoder circuit 10 is capable of providing 25 difierent digital outputs in response to input signals supplied to it. These 25 digital outputs are supplied on 25 output leads 11 with only a single output signal being obtained from the decoder 10 at any one time. Each output lead 11 then is connected to one input of a first group of five input OR gates 12a to l2e.
  • Both of the outputs 11a and 11b are connected to the inputs of the OR gate 12a. While the OR gates 14 are shown for simplicity with only four inputs each, it will be evident that each amplifier 16 must be energizable by no less than 20 different ones of the 25 output leads 11. To accomplish this, five OR gates can be used with each amplifier l6-rather than the one OR gate 14 that is shown for simplicity in the drawing. Alternatively, each OR gate 14 could be provided with 20 inputs. As still another alternative, the 25 diodes 13 could be considered as being arranged as five OR gates, each such five-input OR gates having five diodes l3 driving four of the OR gates 14.
  • the OR gates l6ana 14 edntrol the input bias supplied to two groups of amplifiers I5 and I 6, respectively, indicated in the drawing as NPN transistors, with amplifiers ISa-through I5e being controlled by the outputs of the OR gates 12a through I2e, respectively, and with amplifiers 16a through l6e being controlled by the outputs of the OR gates 14a through He, respectively.
  • amplifiers ISa-through I5e being controlled by the outputs of the OR gates 12a through I2e, respectively
  • amplifiers 16a through l6e being controlled by the outputs of the OR gates 14a through He, respectively.
  • the transistors 15 and 16 are nonconductive, so that no current flows through them.
  • each of the transistors 1511 through l5e is connected through a current limiting resistor 17a through 17e to the primary (first) winding of a corresponding one of a first group of addressing transformers 18a through 18e. Only the transformer 18a has been shown in detail, but all of the transformers 18 are identical, having a single primary winding and five secondary (second) windings.
  • the collectors of the transistors 16a through l6e are connected through current limiting resistors 20a through 20e to the primary windings of a second group of addressing transformers 22a through 22e.
  • the transformers 22 are identical to the transformers 18, each having a single primary winding and five secondary windings.
  • transformer 22e Only the transformer 22e has been shown in detail, but all of the transformers 22 are identical.
  • Current for energizing the primary windings of the transformers l8 and 22 is supplied by a battery 19 which is connected in series with each primary winding, the associated current limiting resistor 17 or 20 and the transistor amplifier 15 or 16 for each of the addressing transformers 18 or 22.
  • Each of the secondary windings of the transformer 18a is connected in series with the secondary windings of a different one of the transformers 22 and, as shown in the drawing, the upper secondary winding of the transformer 18a is connected in series with a secondary winding of the transformer 22e while the next lower secondary winding of the transformer 18a is connected in series with a secondary winding of the transformer 22d.
  • Each set of series-connected secondary windings from the transformers l8 and 22 is connected to the input terminals 50 and 52 of a different one of a plurality of primary winding sheets 36 fitted over a plurality of memory transformers (not shown). This connection is made through a diode 23 so that current pulses flowing in one direction only pass through the printed primary windings on the sheets 36.
  • one of the output leads 11 from the decoder is energized.
  • this output lead is the output lead 11a.
  • a signal is passed by the OR gate 120 to render the transistor a conductive, which results in a pulse of current flowing through the primary winding of the transformer 18a.
  • This induces a current pulse in all five of the secondary windings on the addressing transformer 18a flowing in the direction of the diodes 23 which are connected in series with the secondary windings of the transformer 18a.
  • the cur rent pulses induced in the four secondary windings corresponding to the printed primary winding sheets 36 which are not to be selected must be suppressed. This is accomplished by the series-connections between the secondary windings on the transformers 18 with corresponding secondary windings on the transformers 22.
  • each of the secondary windings from the transformer 18a is connected in series with a secondary winding on a different one of the transformers 22a through 2242 with the upper secondary windings on the transformer 18a being connected in series with the upper secondary winding of the transformer 22e. All of the other secondary windings of the transformer 18a are connected to a secondary winding on the transformers 22a through 22d respectively.
  • a signal is passed by the OR gate 12a to render the transistor amplifier 15a conductive
  • a signal also is passed through a diode 13 to each of the OR gates 14a, 14b, 14c and 14d to render the transistor amplifiers 16a through 16d conductive.
  • the amplifiers l5 and 16 and the transformers l8 and 22 are chosen so that the currents induced in the secondary windings of the transformers l8 and 22 are of equal magnitude, which causes the current induced in the secondary windings of the transformers 220 through 22d to cancel the current induced in the secondary windings of the transformer 18a connected in series therewith, since theses currents are equal and opposite.
  • the diodes 23 also prevent any current from flowing through the printed primary winding on any of the sheets 36 due to a voltage pulse being induced in a secondary winding on any of the transformers 22 in the absence of a voltage pulse being induced in a corresponding secondary winding of one of the transformers 18a through l8e. This causes only the top memory sheet 36 to be provided with an input current in response to the selected one of the 25 outputs of the decoder 10 supplied over the lead 11a.
  • a similar selection of the next sheet 36 from the top sheet 36 is effected by the provision of an output pulse on the lead 22b, 22c and 22a to be energized; so that only the transformer 22d does not provide a blocking signal to the secondary winding of the transfonner connected in series with a secondary winding thereof.
  • only the second from the top sheet 36 is selected by an input signal on the lead 111:.
  • a similar showing could be made for each of the 25 outputs of the decoder 10. It should be noted that the first five of these outputs cause current to flow in the primary winding of the transformer 18a coupled with the absence of current in the primary winding of a different one of each of the five transformers in the group of transformers 22a through 22e.
  • next five outputs of the decoder 10 cause current to flow in the primary winding of the transformer 18b, with corresponding lack of current in the primary winding of a dif ferent one of the transformers 220 through 22a for each of the five different inputs to the OR gate 12b.
  • the diodes 13 are necessary to prevent the feed back of signals to the OR gates 12a to He from the application of signals to the inputs of the OR gates 14a through Me.
  • the printed primary winding sheets 36 used as the output utilization devices for the memory addressing circuit may include printed thereon the secondary windings of the corresponding transformers 18 and 22 which are used to select a particular sheet 36. Then the different sheets 36 using these secondary winding inputs printed thereon, may be slipped over the appropriate transformer cores 18 and 22 so that no direct wiring directions to the terminals 50 and 52 are required.
  • each transformer 18a would have five sheets 36 with a corresponding secondary winding threaded through the core of the transformer 18a and a seriesconnected secondary winding on each of the different sheets selectively threaded through a different core of the group of transformers 22a through 22e.
  • the transformer-coupled memory addressing circuit disclosed in the preferred embodiment of this invention also may be used to address any type of read-only memory and is not limited to addressing of a read-only memory using printed primary winding sheets of the type disclosed in the preferred embodiment.
  • the addressing transformers By dividing the addressing transformers into two groups with series-connected secondary windings, it is possible to substantially reduce the number of input amplifiers needed to select the memory address positions, with 10 amplifiers and IO-addressing transformers being capable of selecting any one of 25-memory address locations; and with 16 amplifiers and l6-addressing transformers being capable of selecting any one of 64 possible address positions in a read-only memory. It also should be noted that it is not necessary to have an equal number of addressing transformers and amplifiers in each group. The best utilization of the addressing transformers, however, results when this number is equal since the maximum possible number of address outputs for a given number of addressing transformers is realized when the two groups of addressing transformers 18 and 22 are equal in number.
  • An addressing circuit including:
  • a first transformer having a primary winding and a plurality of secondary windings for producing an output signal on all of said secondary windings in response to receipt of a signal on the primary winding;
  • a circuit according to claim 1 wherein the combining means comprises a series-connection of each secondary winding of the first transformer with a secondary winding of a different second transfonner.
  • An addressing circuit including:
  • first group of transformers each having a first winding and a plurality of second windings
  • a second group of transfonners each having a first winding and a plurality of second windings
  • a circuit according to claim 5 having an output conductor for each of said series-connected second windings wherein a desired output indication is obtained from only when current is induced in the second winding from the first group of transformers in the absence of any current being induced in the series-connected winding from the second group of transformers.

Landscapes

  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
US707532A 1968-02-23 1968-02-23 Addressing circuit Expired - Lifetime US3576434A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US70753268A 1968-02-23 1968-02-23

Publications (1)

Publication Number Publication Date
US3576434A true US3576434A (en) 1971-04-27

Family

ID=24842087

Family Applications (1)

Application Number Title Priority Date Filing Date
US707532A Expired - Lifetime US3576434A (en) 1968-02-23 1968-02-23 Addressing circuit

Country Status (5)

Country Link
US (1) US3576434A (xx)
BE (1) BE728745A (xx)
DE (1) DE1908820A1 (xx)
FR (1) FR2002476A1 (xx)
NL (1) NL6902667A (xx)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2734183A (en) * 1952-12-22 1956-02-07 Magnetic switching devices
US2920317A (en) * 1958-09-17 1960-01-05 Bell Telephone Labor Inc Code translators
US2964737A (en) * 1955-06-27 1960-12-13 Ibm Addressing circuit
US3159828A (en) * 1959-11-24 1964-12-01 Sperry Rand Corp Binary to decimal matrix converter
US3287700A (en) * 1962-05-23 1966-11-22 Flowers Thomas Harold Core matrix having input and output lines connected in a priority arrangement
US3418460A (en) * 1965-02-03 1968-12-24 Burroughs Corp Decoder circuit using magnetic core elements and operating a display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2734183A (en) * 1952-12-22 1956-02-07 Magnetic switching devices
US2964737A (en) * 1955-06-27 1960-12-13 Ibm Addressing circuit
US2920317A (en) * 1958-09-17 1960-01-05 Bell Telephone Labor Inc Code translators
US3159828A (en) * 1959-11-24 1964-12-01 Sperry Rand Corp Binary to decimal matrix converter
US3287700A (en) * 1962-05-23 1966-11-22 Flowers Thomas Harold Core matrix having input and output lines connected in a priority arrangement
US3418460A (en) * 1965-02-03 1968-12-24 Burroughs Corp Decoder circuit using magnetic core elements and operating a display device

Also Published As

Publication number Publication date
FR2002476A1 (xx) 1969-10-17
NL6902667A (xx) 1969-08-26
DE1908820A1 (de) 1969-10-02
BE728745A (xx) 1969-08-01

Similar Documents

Publication Publication Date Title
US2739300A (en) Magnetic element memory matrix
US2931015A (en) Drive system for magnetic core memories
US3576434A (en) Addressing circuit
US3164810A (en) Matrix access arrangement
GB1042043A (xx)
US3234529A (en) Semi-permanent memory
US3154763A (en) Core storage matrix
US2914748A (en) Storage matrix access circuits
US3021511A (en) Magnetic memory system
US3558914A (en) Signal voltage control for logic circuit
US3320518A (en) Switched regulator with magnetic field responsive phase control device
US3210690A (en) Controlled frequency static inverter
US3927365A (en) Switch operating device
US3466633A (en) System for driving a magnetic core memory
US3188499A (en) Protective circuit for a transistor gate
US3153228A (en) Converting systems
GB1565146A (en) Random access momory cells
US3148357A (en) Current switching apparatus
US3170147A (en) Magnetic core memory
US3174137A (en) Electrical gating apparatus
US3193804A (en) Electronic information storage circuit utilizing negative resistance elements
US3293622A (en) Termination for combined bit and sense windings
KR860007666A (ko) 복수 메모리셀 어레이용 공통 구동회로를 갖는 반도체 메모리 장치
US3025508A (en) Variation of high speed redundancy check generator
US3299412A (en) Semi-permanent memory

Legal Events

Date Code Title Description
AS Assignment

Owner name: AT&T TELETYPE CORPORATION A CORP OF DE

Free format text: CHANGE OF NAME;ASSIGNOR:TELETYPE CORPORATION;REEL/FRAME:004372/0404

Effective date: 19840817