US3571805A

US3571805A - Random or sequential access multichannel multiplexer

Info

Publication number: US3571805A
Application number: US750840A
Authority: US
Inventors: Duane C Fox
Original assignee: North American Rockwell Corp
Current assignee: Boeing North American Inc
Priority date: 1968-08-07
Filing date: 1968-08-07
Publication date: 1971-03-23
Anticipated expiration: 1988-03-23
Also published as: GB1243886A; CA928437A; DE1940297A1; DE1940297C3; NL6912039A; FR2015238A1; JPS5217369B1; DE1940297B2

Abstract

A multipurpose multiplexer comprised of a four-bit binary counter, the outputs of which are coupled to a means for logically decoding all of the counter states. A plurality of switch circuits are connected to respond to the decoded states, to open or close, and thereby complete circuit paths for a corresponding plurality of input terminals to one or more output terminals. Means are provided for controlling the switches in a single-ended or differential mode; one switch is activated for each state while in the single-ended mode, while two switches are simultaneously activated for each state in the differential mode.

Description

United States Patent [72] inventor Duane C. Fox 3,312,941 4/1967 Booth et al 340/166 Fullerton, Calif. 3,337,720 8/1967 Gottfried et al. 235/92 [21] Appl. No. 750,840 3,349,228 10/1967 Gordon et al 235/92 A [22] Filed 1968 Primary Examiner-Gareth D, Shaw [45] Patented Mar. 23,1971 A t E M l B Ch k 73] Assignee North American Rockwell Corporation ms an xammer e apmc Attorneys-L. Lee Humphrles and Edward Dugas 54 RANDOM 0R SE UENTIAL ACCESS l 1 MULTICHANNESMULTIPLEXER ABSTRACT: A multipurpose multiplexer comprised of a fourbit binary counter, the outputs of WhlCh are coupled to a 3 Claims, 7 Drawing Figs.

means for logically decoding all of the counter states. A plu- [52] US. Cl 340/ 172.5 rality f Switch circuits are connected to respond to the [51] G06. 3/00 decoded states, to open or close, and thereby complete circuit [50] Field of Search 235/157; paths for a corresponding plurality f input terminals to one or 340/1 72.5; 235/92; 340/166; 328/42 more output terminals. Means are provided for controlling the 56 R f C d switches in a single-ended or differential mode; one switch is I 1 e erences l e activated for each state while in the single-ended mode, while UNITED STATES PATENTS two switches are simultaneously activated for each state in the 3,264,567 8/1966 Prieto 328/42X differential mode.

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SHEET 2 BF 5 FIG. 2

INVENTOR.

DUANE C. FOX

PATENTEU MR23I97| 9,571,805

saw 3 BF 5 CLEAR FIG. 3

SET COMMAND s READ INVENTOR. DUANE Co FOX PATENT Enmm l9?! 3571 805 saw m nr 5 IJWFERENTIAL SINGLE ENDED W COMMAND lo 35 A ADDRESS CLEAR INVENTOR. DUANE C. FOX

MAQ

ATTORN Pmmwmmamn 3,671; 805

SHEET 5 OF 5 F w m n 1 1 l 3s ADDRESS I l l I 36 Q u FFERENT|AL I SNGLE ENDED I COMMAND l l I J INVENTOR.

DUANE C. FOX

ATTO

RANDOM R SEQUENTIAL ACCESS MULTICHANNIEL MULTIPLIEXER BACKGROUND OF THE INVENTION The present invention pertains to the field of switching circuits and more particularly to a multipurpose circuit for selectively connecting a plurality of input terminals to at least one output terminal.

The art of multiplexing signals has recently been developed to a fine degree of perfection. For example, multiplexing techniques are used in the coding of information, the transmission of many signals time-sequentially over a single communi cation link, and for the conversion of analogue signals for quick and easy processing by digital computers.

A multiplexing device for converting analogue input signals at a plurality of input terminals into usable digital code is dis closed in US. Pat. No. 3,293,608 entitled HIGH SPEED DATA CONVERSION AND HANDLING by M. L. Klein et al., that patent being assigned to North American Aviation, Inc., the assignee of the present invention. In the device of that patent, a tape recorder receives as many as a hundred channels of analogue-type information and operates as a multiplexer to supply these analogue signals to a clamp and an analogue to digital converter employing a logical matrix keyed by a master timer which compares the analogue signals with a standard voltage of successively diminishing value until any difference or error voltage falls to a predetermined minimum level. The number and type of comparisons required form a digital code representative of the analogue value. A tape code transcriber is provided for preparing the digital code for a multichannel recorder monitor, which in turn supplies the digital code to a tape handler such which an intermediate tape is caused to travel. The playback unit is arranged to read off the digital code in a plurality of channels as it is recorded on the intermediate tape, to separate the coded information into blocks, and to supply it to a plurality of separate tape recorders. Such a system, as previously described, will perform the required functions of a multiplexer. The equipment necessary to practice the invention is characteristically not only expensive but quite large in size. It would, therefore, be highly desirable to havea small relatively inexpensive and entirely electronic circuit, or system, which would perform the same functions as the larger more expensive unit. In these types of systems, it is frequently necessary to time-share a particular information carrier with minimum error signals being introduced by the switching type circuit. For example, consider a telemetering system wherein separate voltages represent such factors as temperature, humidity, radiation, intensity, velocity or other such factors. It is common to generate voltages which are each proportional through a. separate factor which has been measured and must now be transmitted over a common time-shared radio frequency carrier system such as a pulse, pulse width or amplitude modulated system. In a telemetering system, a timing circuit is used to switch the input of the system modulator from one information source to anotherto achieve the aforementioned time-sharing.

SUMMARY OF THE INVENTION The multipurpose multiplexer of this invention is comprised of a binary counter, the outputs of which are coupled to a means for logically decoding all states of the counter. A plurality of switch circuits are connected to respond to the decoded states to open or close, thereby completing circuit paths for a corresponding plurality of input terminals to one or more output terminals. Means are provided for controlling the switches in a differential or single-ended mode such that when in the single-ended mode, one switch is activated for each counter state; while in the differential mode, two switches are simultaneously activated for each counter state. A conventional clock signal, such as may be provided by a crystal oscillator or multivibrator, is fed to the input of the binary counter the plurality of switch circuits. Means are provided to reset the counter at any point in the sequence. Additional means are provided to inject into the counter at any desired time a predetennined signal which allows a ransom setting of the states of the counter and, in turn, of the plurality of switches. With this unique circuit arrangement, it is possible to sequentially scan a plurality of input channels, or to randomly scan in any predetermined manner the same number of channels, or to do both of the above mentioned functions in a differential mode such that two inputs are simultaneously sampled either sequentially or at random.

It is, therefore, an object of the present invention to provide a new and novel multiplexer.

It is another object of the present invention to provide a multiplexer utilizing digital commutating means for achieving sequential or random access.

It is a further object of the present invention to provide a novel multiplexer particularly adapted to solid-state components and compatible with existing digital systems.

It is another object of the present invention to provide a multiplexer having the capability for single-ended or differential operation without the necessity for rewiring.

The aforementioned and other objects of the present invention will become more apparent when taken in conjunction with the following description and drawings, throughout which like characters indicate like parts, and which drawings form a part of this application.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic circuit diagram, partially in block diagram form, of the preferred embodiment of the invention;

FIG. 2 is a schematic circuit diagram partially in block form of the decoding logic block of FIG. 1;

FIG. 3 is a schematic circuit diagram of the logic block 120 of FIG. I;

FIG. 4 is a schematic circuit diagram of the read logic block 1l0ofFIG.l;

FIG. 5 is a schematic circuit diagram of the end of scan logic block of FIG. 1;

FIG. 6 is a schematic circuit diagram of the clear logic block 100 ofFlG. l; and

FIG. 7 is a schematic circuit diagram of the address logic block of FIG. ll.

BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a plurality of input signal terminals 0 to 15 are connected to a corresponding number of semiconductor switches 20a to 20p. The gating terminal 22 of each switch is connected to a corresponding terminal Map-Mp of a decoding logic block 50 (see FIGS. 1 and 2). When'the gate 22 of any switch, 20a to 2011, is true, its input terminal is connected to a common output terminal 28. In an identical manner, input terminals through 15 are connected to a common output terminal 29 when the gates 22 of switches 201' to 20p, corresponding to the respective switches for terminals 3 through 15, are true. Thus the decoding logic block 50 selectively gates signals present on input signal terminals 0--7 to the common output 2% and selectively gates signals present on input signal terminals 8-15 to the common output 29. For the embodiment shown, the common output terminals 28 and 29 are time shared by the input signals on input signal terminals 0-7 and 8-15 respectively.

The four-bit binary counter provides the inputs for the decoding logic block 50. The four-bit binary counter is comprised of four binary-type counters: 30, 40, 60, and 70. The counters are sequentially connected as shown by the arrows in FIG. I to provide a four bit, 16 state serially operated binary counter. The output of the

counters

30, 40 and 60 are fed directly to the decoding logic block 50. The output of the binary counter 70 is fed first to a logic block 90 and from there to the decoding logic block 50.

Counters

30, 40, 60 and 70 are actuated to count sequentially as a four bit counter by counting clock pulses of a conventional clock signal and may be selectively set to any of the 16 states by inputs Set 01, Set Q2, Set 03 and Set Q4. A conventional clock train signal in such as may be provided by a crystal oscillator or multivibrator is applied to terminal 17 which is connected to an input of the logic block 120. The output of logic block 120 is fed to the first bit counter 30. A read signal, generated by any means sufficient to provide a logic true pulse, is'applied as required to terminal 18 which is connected to the input of logic block 110. The read signal resets the binary counter to any desired state by causing the appropriate bit to copy either Set Q1," Set 02, Set Q3," or Set Q4," as indicated in FIG. 1. The output of logic block 110 is connected to terminals of the binary counters 30, 40, 60 and 70. Each of the binary counters is provided with a set terminal labeled Q1, Q2, Q3, and Q4, respectively. A terminal 19 is connected to an input of the logic block 100 and is adapted to receive a logic true pulse used to clear (set to binary the counter. The pulse is designated as a clear or reset signal. The logic true pulse may be provided by a source of a voltage level having the required voltage to trigger the AND gate 51 for providing a logic true pulse to OR gate 52. A typical true pulse is +7 volts. The output of logic block 100 is a clear signal which is sent to the binary counters 30, 40, 60 and 70 and to the inputs of logic blocks 120 and 110. One of the outputs of binary counter 60 (O3) is fed to the logic block 80. In a similar manner, the output 04 of binary block 70 is also fed to logic block 80. Logic block 80 samples the states of

binary counters

60 and 70 to provide an end of scan signal when each of the switches have been sampled in the preselected manner. The outputs of

binary counters

30, 40, 60 and 70 are sampled by binary indicator switches 31, 32, 33 and 34, respectively. These indicator switches can be utilized to read out or indicate the state of each of the aforementioned counters. The readout may be accomplished visually by having each of the switches connect an indicator light 38 in circuit to a source of power 39. In the embodiment shown, these indicators 31 to 34 are semiconductor switches which are turned on or off depending on the state of the counter. The address terminal 35 is connected directly to the logic blocks 100 and 90 and is adapted to receive an address signal which when applied will override all other signals to allow a random address to be applied to the decoding logic block 50. The address terminal 35, in normal operation, provides a logic true signal to AND

gates

51 and 59 and to inverter 53. Application of the address signal provides a conventional logic false signal to

elements

51, 59 and 53. A typical logic false signal is l4 volts. Terminal 36 is connected to an input of the logic block 90 and is adapted to receive the differential or single mode input signal such that in the differential mode, two switches are simultaneously sampled for each binary counter state, and in the single mode, only one switch is sampled for each binary counter state. When a logic false signal is applied to terminal 36 the multiplexer will operate in the single ended mode whereas the presence of a logic true signal will effect differential mode operation.

Referring to FIG. 2, in which a further circuit breakdown of the decoding block 50 is shown, there are sixteen AND gates 42 having four inputs each. The gates 42 are segregated into two banks of eight each. The left-hand bank is comprised of gates 41a to 42h and receives as an input to each gate the Y labeled output from the logic circuit 90. The right-hand bank is comprised of gates 42i to 42p and receives as an input to each gate the V labeled output from the logic circuit 90. The three remaining inputs for each AND gate in a bank are connected to three of the six outputs O1 to Q3 and O1 to O3 in the manner shown such that only one switch in a bank is activated for each unique state of

counters

30, 40 and 60. The AND gates in the left-hand bank are connected in a symmetrical manner to the AND gates of the right-hand bank, with the exception of the Y and Ytgminals, as previously discussed. If a signal is present on the X and Y terminals simultaneously, then the banks of gates operate in a differential mode rather than single ended. That is, instead of only one switch closing for each counter state, two switches, one in each bank, are simultaneously closedJThe output of each AND gate is fed to the control gate of a corresponding lettered switch 20.

Referring to FIG. 3, the logic block 120 is shown comprised of an OR gate 42 which receives as inputs a clear signal from logic block 100 and the external clock signal 1],. The output of the OR gate 41 is fed to an inverter 43. The output of inverter 43 is the internal clock signal C,,,,.which is fed to one gate input of binary counter 30. The output C,,,, is also fed to the inyerter 44 to provide a complementary output C The output C is fed to the other gate input of binary counter 30.

Referring to FIG. 4, the logic block 110 is shown comprised of an OR gate 25 which receives as inputs the clear signal from logic block I00 and a read signal from terminal 18. The output of OR gate 25 is fed to each of the binary counters to allow the set lines (Set 0,, 0 Q and Q to be copied by the binary counters when the read command on terminal 18 is set true. In addition, the output signal of OR gate 25 during thg cl e ar o eration goes true and the counter is reset to the 0,, 0,, Q

4 (0000) state.

Referring to FIG. 5, the logic block is shown comprised of an inverter 46, AND

gates

45 and 47 and an OR gate 48. The AND gate 45 receives a differential or single-ended command signal on one tenninal and the signal Q on the other terminal. The inverter 46 inverts the command signal which is then fed to one of the inputs of AND gate 47. The other input to gate 47 is 0,. The outputs of

gates

45 and 47 are fed to the inputs of the OR gate 48. The output of the gate 48 controls the state of switch 49. The purpose of logic block 80 is to change the timing of the End of Scan signal to correspond to completions of multiplexing eight channels of data in the differential mode or sixteen channels of data in the single-ended mode. In operation, when the command signal is true, the differential mode is selected and the AND gate 45 causes the switch 49 to close when 0 goes true. Likewise, when the command signal is false and O4 is true, the switch 49 is closed.

Referring to FIG. 6, the logic block 100 is shown comprised of AND gate 51, OR gate 52, and invertet3 'l'h e fgnction of block 100 is to clear the counters to the O, Q, 0;, O, (0000) state, when no signal is received on the address terminal, or when there is an address signal simultaneously with a clear/reset signal on terminal 19. The AND gate 51 has one of its inputs connected to terminal 19 and the other to the address terminal. The inverter 53 has its input connected to the address terminal. The output of the AND gate 51 and of the inverter 53 are sent to the inputs of the OR gate 52. The output of the gate 52 is the CLEAR signal.

Referring to FIG. 7, the logic block is shown comprised of an inverter 54, OR

gates

57 and 58, and the AND

gates

55, 56 and 59. The AND gate 56 receives as an input the 0, signal, and the output from the inverter 54. The AND gate 55 receives as an input the 0 signal and the output from the inverter 54. The output from AND gate 55 is fed to the input of OR gate 58 with the output of AND gate 56 fed to the input of OR gate 57. The AND gate 59 receives as inputs the differential/single-ended command signal and the address signal. The output signal from AND gate 59 is fed to the inputs of OR gates 57 an d 58. The output of OR

gates

57 and 58 are designated Y and X, respectively. This logic block ensures that two switches, one in each bank, close for every state of the binary counter in the differential mode of operation. In operation when the differential/single-ended command is true (differential mode) and the signal on the address terminal is true (normal unactuated condition), then both X and V are identical and have no affect on the selection of the switches. Therefore, two switches will close for every state. In the single-ended mode X will follow Q4 and Y will follow 04, thereby closing only one switch for every state of the binaries.

The random access multimode multiplexer may be operated in either a single-ended or differential mode. It is operated in a single ended mode when one switch is activated for each counter state, and in a differential mode when a plurality of switches are simultaneously activated for each counter state.

In a single-ended mode, the four bit binary counter of FIG. I (counters 39, Ail, 60 and 70) is actuated by a pulse generator providing a conventional clock signal at terminal 17 to enable the binary counter to sequentially assume the 16 binary counter states. When the clock pulse f (FIG. 3 provides a logic true pulse, the OR gate 41 provides b inary element 30 with a C,,,, signal through inverter a3 and a C,,,, signal through inverters A3 and M. The resulting signal, Cm, is a timing pulse corresponding to the logic true state of terminal 17 and G, is the complement or prime of C,,,,. In other words, when the timing pulse provides a logic true signal at terminal 17, logic block 120 provides binary counter element 30; with both a corresponding timing pulse C,,,, and the pulse C,,,,, which is the signal C inverted.

As the four bit binary counter assumes the 16 possible counter states in response to the timing pulse, each of the counters 30, d0, 60 and 70 provides an output (shown in FIG. I.) to the decoding logic block 50. For instance, a logic true pulse is provided at Q1, Q2, Q3, and Q4 when the binary counters 30, 40, 60 and 70 are in a binary ll state. Likewise, a true pulse is provided at 61, O2, O3 and 64 when the binary counters 30, 4t), 60 and 70 are in a binary zero state.

For example, assume that the

counters

30, 40, 60 and 70 read 0, ll, 0, and l, respectively, representing binary number eight. A binary true pulse is then provided at terminals Q1, Q2, Q3 and Q4, the true pulse at terminal Q4 applied as shown in FIG. 7 to one inputof AND gate 56.

When operating in the single ended mode, the terminal 36 (FIG. 7) is in a logic false state. Thus, a signal representing a logic false state is presented to inverter element 54, the output of which is a signal representing a true state applied to the other input of AND gate 56. Therefore, both inputs of AND gate 56 become true which provides a true signal to OR gate 57 causing a true pulse to be present on Y of. logic block 50 1 FIG. 2). A true pulse present on Y will provide a true pulse to one input of AND gates 42i-42'p. With the counter assuming the binary number 8, and true pulses present on terminals 01, Q2, and 03, it is seen from FIG. 2 that only AND gate 421' would then have logic true signals on all four inputs. In response to this decoding of the binary number 8 by logic block 50, the switch 201' is activated so as to connect the input signal present on line 8 to the common output terminal 29.

When a subsequent counting pulse is received by counter 30, the counter changes from a logic state to a logic 1 state for increasing the count in the binary counter to binary 9. A logic true pulse then appears at output 01.

Referring to FIG. 2, it is thus seen that AND gate 4l2j and only AND gate 42j would then have logic true signals present on all four input terminals thus connecting the input signal present on line 9 through the switch 20] to common output terminal 29. Thus, it is seen that as the binary counter continues to receive counting pulses from logic block 120 the counter will sequentially assume the 16 possible states of the 4 bit binary counter which in turn will cause logic block 50 to sequentially actuate switches 20a through 20p and thus sequentially connect lines 0 through lines 15 to the output terminals 2d and 29 shown in FIG. 1. Input signals present on lines ll through 7 will be connected to common output 28 and input signals present on lines 8 through 115 will be connected to common output 29.

After the counter has progressed to the binary number 16, (binary 1 states present in

counter elements

30, 40, 60 and 76) the counter will reassume the binary number zero, (binary 6 states in the counter elements) with subsequent connection of line 0 through switch 20a to common output terminal 28.

It is seen from logic block 80 (FIG. that with the presence of a binary 1 state in binary counter 70, output terminal Q43 will present a logic true state on one input of AND gate d7. As previously mentioned, when operating in the single ended mode terminal 36 of FIG. 7 will be in a logic false state. This false state will be present on one input of AND gate 435 (FIG. 5) and at inverter 46 which in turn will provide a true state at'the other input of AND gate 47. Both inputs being true, AND gate 67 will provide a true signal at OR gate dill which in turn will actuate switch 69 to provide an end of scan signal. 1

Elements

31, 32, 33 and 34 of FIG. 1 provide switch means for readout of the binary state of counter elements 30, All), 60 and 70, as shown. To clear the counter to a binary zero position, a logic true signal is provided to both terminals of AND gate 51 of FIG. 6. Since the address terminal 35 (FIG. 7) is normally in a true state, it is only necessary to provide a true state at terminal 19- The clear reset terminal (terminal 19) normally in a false state, providing a true signal at terminal 19 will make both inputs of AND gate 51 true. This will provide a true signal at OR gate 52 with a subsequent true signal to one input of OR gate d1 (FIG. 3), the other input of OR gate 431 being connected to the pulse generator providing the clock timing pulse. A true pulse on ORgate 41 negates the effect of the clock timing pulse present on terminal 17, thus removing the sequential counting provision previously applied by logic block 1120 to binary counter 30. The true pulse from OR gate 52 also is provided at one input of OR gate 25 of FIG. 4, the other input normally false and designated as the read terminal 18. The presence of a true pulse-on one terminal of OR gate 25 results in a true pulse applied to

binary counters

30, 40, 60 and as shown in FIG. I. This true pulse will effect a binary zero state in all of the binary counter elements. As long as the true pulse is applied at terminal 19, the binary counter elements will remain in a binary zero state. With removal of the binary true pulse from clear reset terminal 19, the binary counter will resume the sequential counting from zero to fifteen, thus sequentially connecting lines 0 through 15 to output terminals 28 or 29, as previously described.

To operate in the differential mode, the terminal 36 (FIG, 7) is provided with a conventional logic true signal which is applied to one input of AND gate 39. The true state is also applied to inverter M providing a false state at one input of both AND

gates

55 and 56,thus preventing AND gates 55 and $6 from further operation in this mode. Since address terminal 35 is normally in a true state, both terminals of AND gate 59 become true providing a true signa l to OR

gates

58 and 57 resulting in a true signg at terminals X and V of FIG. 2. A true pulse present on both X and V will provide a true signal to one input of the AND gates 42a-4l2p. Then binary zero states in

counter elements

30, 40, and 60 provide a logic true pulse at 61, O2, and 63 resulting in a true pulse at the other three inputs of both AND gates 42a and 421'. The binary state of counter element 70 would now have no effect upon the operation of switches 20 a-20p since it has been shown from the previous discussion of FIG. 7, that with a true pulse present at terminal 36, the AND

gates

55 and 56, towhich counter outputs Q4 and 64 are connected, have been effectively removed from the circuit. Therefore, it is seen that with either the bi-' nary number 0 or the binary number 8 assumed by the counter, both AND gates 42a and 42i will have true pulses present on all four inputs which will provide that both switches 20a and 201' are actuated. Similarly, it can be shown that binary states present in the counter corresponding to either binary number 1 or 9 will actuate switches 20b and Zllj, that binary numbers 2 or 10 will actuate

switches

20c and 20k, and binary numbers 15 or 7 will actuate switches 20h and 20p. Thus, as the binary counter progresses from the binary 0 to the binary 7 number, all of the switches will be actuated in the following manner. A binary 0 number present in the counter will actuate switches 20a and 20L A binary 1 number will actuate switches 20b and 20 A binary 2 number will actuate

switches

20c and 20k. A binary 3 number will actuate

switches

20d and 201. A binary 4 number will actuate

switches

20c and 20m. A binary 5 number'will actuate switches 20f and 20m A binary 6 number will actuate switches 20g and 260. A binary 7 number will actuate switches 20h and 20p. Then, a binary 6 number will also actuate switches 20a and 201' as did binary number 0 and thus the combination of switch connections presented for binary numbers 0-7 will be repeated for binary numbers 3- -l5. The effect, therefore, is to provide input signals to the common output terminals 28 and 29 at twice the output rate as was provided in the single ended mode.

It can also be seen upon inspection of FIG. that counter outputs Q3 and Q4 are provided to AND

gates

45 and 47, respectively. Output terminal Q3 will provide a true pulse at one input of AND gate 45 when the counter contains the binary number 4-7 or 12-15. Likewise, the 04 output provides a true pulse to one input of AND gate 47 when the counter contains the number 813 15. Thus, with the terminal 36 (FIG. 7) in a logic true state (differential mode), the end of scan signal of FIG. 5 will be generated whenever the counter goes from a binary 7 number to a binary 8 number or from a binary number to a binary 0 number.

If it is desired to interrupt normal operation of the multiplexer to provide random access, the address terminal 35 (FIG. 7) is provided with a logic false state. When this is done, a false signal will be present at AND gate 51 (FIG. 6) which effectively removes the clear reset terminal 19 from the circuit. The logic false signal will also be applied to inverter element 53 (FIG. 6) which provides a true signal at OR gate 52 which has the same effect as previously discussed, when the clear reset terminal was actuated, to clear the counter to a binary 0 number. In addition, the presence of a false signal at address terminal 35 provides a false signal to AND gate 59 which provides a false signal to one input of OR

gates

57 and 58. As seen from the previous discussion of the differential mode of operation, a logic true state would be present at terminal 36 (FIG. 7) with inverter 54 providing a logic false signal to both AND

gates

55 and 56, thus providing false signals at the other inputs of OR

gates

57 and 58. The net result is that X and Y and therefore one input of AND gates 42a42p are provided with a false signal. In summation, the counter now contains a binary 0 number and all switches 20a 20p are open.

The binary number desired to be fed into the counter is predetermined with appropriate binary states present on set Q1, set 02, set Q3 and set Q4 (FIG. 1). To feed this number into the counter to effect the random access capability, a logic true signal is provided at read terminal 18 (FIG. 4) and thus to one terminal of OR gate 25. This true pulse provided to OR gate provides a true pulse (FIG. 1) to counter

elements

30, 40, 60 and 70 actuating the counters to copy the binary states provided in set Q1, Q2, Q3 and Q4. The logic false state is then removed from address terminal with the effect that the counter starts to sequentially count from the binary number fed into it by means of the random access capability.

Therefore, the multimode multiplexer can operate in either the single-ended or differential mode which effectively varies the input rates and accessibility of the various input signals. In addition, at any point in the operation of the multiplexer the counter may be reset to 0 and restarted in the single ended or differential mode of operation. Further, at any point in the operation of the multimode multiplexer (differential or single ended mode), the multiplexer may be interrupted to provide random access to the input signals and after such access the multiplexer may be allowed to sequentially proceed in its normal operation or random access may be repeated to sample any of the input signals in any sequence desired.

While there has been shown what is considered to be the preferred embodiment of the present invention, it will be manifest that many changes and modifications may be made therein without departing from the essential spirit of the invention. For example, the circuit used in each of the logic blocks may be comprised of different components which will perform the same arithmetic functions. It is intended, therefore, in the annexed claims, to cover all such changes and modifications as fall within the true scope of the invention.

I claim:

l. A multimode multiplexer comprising in combination:

a. a binary counter having a plurality of counter states, a pulse generator providing pulses to said binary counter for enabling said binary counter to sequentially assume said counter states;

b. logic means responsive to said binary counter for decoding said counter states; c. a plurality of switch circuits connected to said logic means, at least one of said switch circuits operatively responding to each decoded counter state;

d. a plurality of input signals, one signal being connected to each of said switch circuits;

e. a plurality of independent output terminals with certain of said output terminals being common to selected ones of said plurality of switch circuits, at least one of said input signals being selectively connected through a switch circuit to an output terminal in response to a decoded state of said binary counter, whereby said output terminal is time shared by a plurality of switch circuits; and

f. multiplexer mode control means connected to said logic means for rendering a plurality of said switch circuits operative for each decoded counter state whereby a plurality of said input signals are connected to a plurality of said independent common output terminals for each decoded binary state.

2. A random access multimode multiplexer comprising in combination:

b. decoding logic means responsive to said counter for decoding said counter states;

0. a plurality of switch circuits connected to said logic means at least one of said switch circuits operatively responsive to each decoded counter state;

e. a plurality of independent output terminals with certain of said output terminals being common to selected ones of said plurality of switch circuits, at least one of said input signals is selectively connected through a switch circuit to an output terminal in response to a decoded state of said binary counter, whereby said output terminal is time shared by a plurality of switch circuits; and

f. random access control means connected to said logic means and said counter for interrupting said counter and arbitrarily resetting the counter states to a predetermined count and then enabling said counter to again sequentially assume said counter states whereby selected ones of said pluralityof switch circuits are randomly actuated for connecting an input signal associated with a selected switch circuit to an output terminal.

3. The multiplexer according to Claim 2 and further comprising:

g. multiplexer mode control means connected to said decoding logic means for rendering a plurality of said switch circuits operative for each decoded counter state whereby a plurality of said input signals are connected to a plurality of said independent common output terminals for each decoded binary state.

Claims

1. A multimode multiplexer comprising in combination: a. a binary counter having a plurality of counter states, a pulse generator providing pulses to said binary counter for enabling said binary counter to sequentially assume said counter states; b. logic means reSponsive to said binary counter for decoding said counter states; c. a plurality of switch circuits connected to said logic means, at least one of said switch circuits operatively responding to each decoded counter state; d. a plurality of input signals, one signal being connected to each of said switch circuits; e. a plurality of independent output terminals with certain of said output terminals being common to selected ones of said plurality of switch circuits, at least one of said input signals being selectively connected through a switch circuit to an output terminal in response to a decoded state of said binary counter, whereby said output terminal is time shared by a plurality of switch circuits; and f. multiplexer mode control means connected to said logic means for rendering a plurality of said switch circuits operative for each decoded counter state whereby a plurality of said input signals are connected to a plurality of said independent common output terminals for each decoded binary state.

2. A random access multimode multiplexer comprising in combination: a. a binary counter having a plurality of counter states, a pulse generator providing pulses to said binary counter for enabling said binary counter to sequentially assume said counter states; b. decoding logic means responsive to said counter for decoding said counter states; c. a plurality of switch circuits connected to said logic means at least one of said switch circuits operatively responsive to each decoded counter state; d. a plurality of input signals, one signal being connected to each of said switch circuits; e. a plurality of independent output terminals with certain of said output terminals being common to selected ones of said plurality of switch circuits, at least one of said input signals is selectively connected through a switch circuit to an output terminal in response to a decoded state of said binary counter, whereby said output terminal is time shared by a plurality of switch circuits; and f. random access control means connected to said logic means and said counter for interrupting said counter and arbitrarily resetting the counter states to a predetermined count and then enabling said counter to again sequentially assume said counter states whereby selected ones of said plurality of switch circuits are randomly actuated for connecting an input signal associated with a selected switch circuit to an output terminal.

3. The multiplexer according to Claim 2 and further comprising: g. multiplexer mode control means connected to said decoding logic means for rendering a plurality of said switch circuits operative for each decoded counter state whereby a plurality of said input signals are connected to a plurality of said independent common output terminals for each decoded binary state.