US3458719A - Threshold logic switch with a feed-back current path - Google Patents

Threshold logic switch with a feed-back current path Download PDF

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US3458719A
US3458719A US495943A US3458719DA US3458719A US 3458719 A US3458719 A US 3458719A US 495943 A US495943 A US 495943A US 3458719D A US3458719D A US 3458719DA US 3458719 A US3458719 A US 3458719A
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potential
input
transistor
node
circuit
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Leonard Weiss
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International Business Machines Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/013—Modifications for accelerating switching in bipolar transistor circuits

Definitions

  • FIG.5 FIG-6 INPUT REFERENCE L. WEISS July 29, 1969 THRESHOLD LOGIC SWITCH WITH A FEED-BACK CURRENT PATH Filed 001;. 14. 1965 10 Sheets-Sheet 5 IIII! nil-I! ill-II: ill-I:
  • FIG.27 THRESHOLD LOGIC SWITCH WITH A FEED-BACK CURRENT PATH Filed Oct. 14; 1965 10 Sheets-Sheet 1 0 FIG.26 FIG.27
  • This invention relates to switching circuits for performing logic functions in digital computers and for other applications where binary switches are required.
  • the present invention has achieved a substantial increase in speed by an approach directly contrary to both the pievailing positive feedback and ultimate circuit philosop res:
  • a further object is to maintain the reference potential within said predetermined range by varying the reference potential in time-delayed phase with respect to the input potential.
  • Another object is to provide a preferred embodiment of the invention wherein said time-delayed in-phase variation of the reference potential is obtained by a novel negative feedback network extending from the in-phase output of the circuit to the reference node of the latter.
  • Still another object is closely related to the negative feedback aspect of the present invention. That is, circuits embodying the negative feedback are more economical in that they do not require tight component specifications and hence may utilize relatively less expensive transistors or other active devices, passive elements and power supplies. For a given set of component tolerances the negative feedback reduces the range of variation of the signal swing amplitudes at the outputs of the circuit.
  • a further object achieved by the negative feedback is to provide greater stability of the circuit at high frequencies. That is, any tendency to oscillation or transient ringing is substantially reduced.
  • Another object is to provide a novel current switch which requires only one power supply, as opposed to prior current switch circuits, which generally require at least two power supplies.
  • a further object is to provide a switching circuit having greater stability with respect to quiescent direct current levels. Any tendency of a direct current level to vary due to an input level variation or to a component parameter deviation is counteracted by the negative feedback.
  • Another object is to provide a novel switching circuit wherein the switching speed is less adversely affected by heavy loads on the outputs.
  • this advantage is particularly evident when loading the in-phase output. This loading increases the time delay of the reference potential with respect to the input potential swing and thereby increases the overdrive. The increased overdrive improves the switching speed so as to counteract the retarding effect of the heavy load.
  • Still another'object is to eliminate the reference base lead inductance that is inherent in the conventional current switch when embodied in the form of a monolithic integrated circuit. This elimination of base lead inductance further improves the high frequency stability.
  • Another object is to provide a current switch having a higher input impedance and lower input capacitance so as to result in less loading of the preceding circuit. This is achieved in the preferred embodiment of the present invention because the reference base is no longer grounded but is in effect connected to the relatively high impedance of the feedback network which impedance is reflected through both transistors to the input base so as to increase the impedance looking into the latter.
  • a further object is to provide a novel switching circuit wherein the rise time of the output is less dependent on the rise time of the input signal. If the rise time of the input signal is sufiiciently slow it is even possible to provide a negative propagation delay. That is, the output signal will reach its midpoint before the input signal reaches its midpoint.
  • the present invention varies the reference potential in approximate phase with the input potential but slightly time-delayed with respect thereto.
  • this variation of the reference potential is achieved by a negative feedback network extending from the in-phase output
  • similar results can be achieved by deriving the reference potential in other ways.
  • the reference potential may be derived from the input with a delay line or other means to provide the required delay with respect to the input signal.
  • FIG. 1 is a circuit diagram showing a preferred embodiment of the invention
  • FIG. 2 is a schematic diagram of a switching circuit illustrating the basic principle of those embodiments of the invention which are of the feedback type;
  • FIG. 3 shows a conventional emitter follower current switch in accordance with the prior art
  • FIG. 4 shows a modification of the prior art wherein in the emitter follower stage is replaced by a differential amplifier
  • FIG. 5 is an idealized plot of the input and reference potentials during the switching'operation of the current switch circuits of FIGS. 3 and 4;
  • FIG. 6 is an idealized plot of the input and reference potentials during the switching operation of the present invention as embodied in FIG. 1;
  • FIGS. 7 and 8 are oscilloscope photographs of the input and out-of-phase output potentials during respectively the turn-on and turn-off switching operations of the emitter follower current switch circuit of FIG. 3;
  • FIGS. 9 and 10 are oscilloscope photographs of the input and output potentials during respectively the turn-on and turn-off switching operations of the differential amplifier current switch circuit of FIG. 4;
  • FIGS. 11 and 12 are oscilloscope photographs showing the input and output potentials during respectively the turn-on and turn-off switching operations of the current switch in accordance with the present invention as shown in FIG. 1;
  • FIG. 13 shows the input and reference potentials of the current switch embodiment of FIG. 1 for both the turn-on and turn-off switching operations;
  • FIG. 14 is a circuit diagram showing the current switch embodiment of FIG. 1 arranged in a closed-loop test whereby the circuit drives itself;
  • FIG. 15 shows a modification of the current switch embodiment of FIG. 1 wherein a capacitor is added to the reference base to increase the delay ofthe reference potential;
  • FIG. 16 is a circuit diagram showing a comparison test of a single current switch stage both with and without a feedback network in accordance with the present invention
  • FIG. 17 shows a modified form of the invention wherein the reference potential is derived from the input instead of the output
  • FIG. 18 is an oscilloscope photograph showing the input and out-of-phase output potentials of the closed-loop test circuit shown in FIG. 14;
  • FIG. 19 is an oscilloscope photograph of the input and reference potentials of the comparison test circuit of FIG. 16 with the feedback network connected therein;
  • FIG. 20 is an oscilloscope photograph showing the input and output potentials of the comparison test circuit of FIG. 16 with the feedback network omitted;
  • FIG. 21 is an oscilloscope photograph similar to FIG. 20 but showing the input and output potentials of the comparison test circuit of FIG. 16 with the feedback network connected therein in accordance with the present invention
  • FIG. 22 shows a modified form of the invention similar to FIG. 1 but having the lower end of thefeedback network connected to ground instead of to the out-ofphase output;
  • FIG. 23 shows another modified formof the invention similar to FIG. 1 but having an active feedback-network comprising an additional transistor to reset the magnitude of the reference potential and to provide additional delay in the feedback loop;
  • FIG. 24 shows still another modified form of the invention comprising a single current switch stage and an active feedback network similar to the network of FIG. 23;
  • FIG. 25 shows another modified form of the invention comprising an emitter follower second stage and a passive feedback network extending therefrom to provide the reference potential;
  • FIGS. 26 to 28 show the circuitry and idealized input and output potential traces of two further modifications each having a positive feedback network in addition to the negative feedback network of the previous embodiments.
  • transistors Q5, Q6 constitute the current switch stage and transistors Q7, Q8 constitute the emitter follower stage.
  • the latter provides a relatively high load impedance for the current switch stage Q5, Q6 so as to prevent the latter from being excessivley loaded by succeeding circuits (not shown).
  • Input terminal 12 is connected to the base 5b of transistor Q5 having its collector 50 connected through collector load resistor R to a positive power supply E3.
  • the emitter 52 of transistor Q5 and the emitter 6e of transistor Q6 are connected at a common node to a constant current source comprising a resistor R9 and a negative power supply E2.
  • Resistor R9 is of sufiiciently high impedance so as to pass a relatively constant current which is switched through either transistor Q5 or Q6 in a manner to be described.
  • the base 6b of transistor Q6 is connected to a fixed reference potential which for purposes of illustration is shown in FIG. 3 as at ground level.
  • the collector 6c of transistor Q6 is connected through collector load resistor R11 to the power supply E3.
  • the collector 5c of transistor Q5 is direct-coupled by lead 5x to the base 7b of transistor Q7, and the collector 6c of transistor Q6 is similarly direct-coupled by lead 6x to the base 8 of transistor Q8.
  • the respective collectors 7c, 80 of transistors Q7, Q8 are directly connected to power supply E3.
  • the emitters 7e, 82 of transistors Q7, Q8 are connected through respective resistors R12, R13 to a negative power supply E4.
  • the two outputs O3, 04 of the circuit are taken from the emitters 7e, 8e.
  • the potential of the signal at the input 12 is designated by the label INPUT in FIG. 5, and the potential at the reference base 6b is shown at a constant ground level designated REFERENCE.
  • the potential at the input 12 is initially at the up level, it will be seen that the base-to-emitter potential of transistor Q5 is greater than that of transistor Q6. Hence the current flows through transistor Q5 while transistor Q6 is either cut off or has substantially less current flow therethrough.
  • the potential at the collector 5c of transistor Q5 is therefore at a down level where as the potential at the collector 6c of transistor Q6 is at a relatively up level.
  • transistor Q5 is now off, its collector 50 as well as the emitter 7e of transistor Q7 and output lead 03 are at the up level, whereas transistor Q6 is on so that its collector 6c as well as the emitter 8e of transistor Q8 and output lead 04 are at a down level.
  • This state will be maintained until the input potential at input terminal 12 moves upwardly to again traverse the reference potential as indicated at the point Y in FIG. 5 at which time the fixed current switches from transistor Q6 back to transistor Q5. It will thus beseen that the turn-on switching operation of transistor Q5 does not occur until after the time delay T2 from the instant when the input potential starts to rise to the instant when the input potential again traverses the reference potential at point Y.
  • FIG. 6 The basic approach by which the subject invention achieves a faster switching speed is shown schematically in FIG. 6.
  • the plot of the input signal potential in the latter figure is substantially identical to that in FIG. 5.
  • the reference potential is now no longer fixed at ground level but instead varies in time-delayed phase with the input potential so as to remain within a predetermined incremental range about the latter.
  • the reference potential when the input potential is at its up level the reference potential is also at its up level which is below but closely adjacent to that of the input potential. When the latter swings downwardly, the reference potential is maintained at its up level for a time-delay period until after the input potential has traversed the reference potential at the point V. At this instant the circuit of the subject invention commences its switching action. Because of the relatively close proximity of the reference potential to the input potential at their respective up levels, it will be seen that the time period T3 for this traversal to occur is relatively small as compared with the time period T1 for the traversal to occur in the prior art circuit of FIG. 3 as shown in FIG. 5.
  • the reference potential After the input potential attains its down level the reference potential will reach its down level which is higher than but closely adjacent to that of the input potential. Hence when the latter swings upwardly it quickly traverses the reference potential at the point W after a relatively small time period T4 which is substantially less than the time period T2 for the corresponding traversal to occur in the prior art circuit of FIG. 3 as shown in FIG. 5.
  • the circuit of the present invention assumes its initial quiescent state with the input potential at its up level and the reference potential also at its up level which is below but closely adjacent to the up level of the input potential. It will thus be seen that by maintaining the input and reference potentials at relatively close levels the time for the potential traversal to occur is substantially reduced thereby accelerating the commencement of the switch action, and substantially improving the switching speed of the circuit.
  • FIG. 1 discloses one of the many embodiments which the invention may take in practice.
  • the first stage comprising transistors Q1 to Qln inclusive and Q2 constitutes a current switch.
  • the OR and NOR logic functions a plurality of transistors are connected in parallel with transistor Q1 as shown by only the single transistor Qln for simplicity in illustration.
  • Collectors 1c, lcn, 2c of transistors Q1, Qln, Q2 are connected through respective collector load resistors R2 and R3 to ground.
  • the emitters 1e, len, 2e of transistors Q1, Qln, Q2 are connected at a common node to a constant current source comprising a resistor R1 and a negative power supply E1.
  • the input terminals I1, Iln are connected to the respective bases 1b, Ibn of transistors Q1, Qln whereas the base 212 of transistor Q2 has applied thereto the time-delayed in-phase reference potential described above with respect to FIG. 6 and derived from the output in a manner to be described below.
  • the second stage comprising transistors Q3, Q4 functions as a differential amplifier.
  • Power supply E1 and resistor R8 constitute a source of constant current which is switched to either transistor Q3 or transistor Q4 in response to the polarity of the difference between the signal at base 311 and that at base 4b.
  • the collectors 3c, 40 of transistors Q3, Q4 are con nected to ground through respective collector load resistors R6, R7.
  • the respective emitters 3e, 4e of transistors Q3, Q4 are connected at a common node to resistor R8.
  • the base 3b of transistor Q3 is direct-coupled by lead 1x to the collector 1c of transistor Q1, and the base 4b of transistor Q4 is similarly direct-coupled by lead 2x to the collector 2c of transistor Q2.
  • This differential amplifier stage Q3, Q4 serves a similar function to that of the emitter follower stage Q7, Q8 of FIG. 3 in that it provides a high impedance load on the first stage to permit higher fan-out power of the circuit while maintaining unity gain.
  • the Stage Q3, Q4 has the further advantage of providing greater noise tolerance in that noise of a magnitude less than that required to reach the switching threshold will not be transmitted to the outputs O1, 02.
  • a direct-current negative feedback network comprising a pair of resistors R4, R5 is provided. One end of resistor R4 is connected to collector 3c of transistor Q3 at the in-phase output 01 and one end of the other resistor R5 is connected to collector 4c of transistor Q4 at the out-of-phase output 02.
  • the opposite ends of resistors R4, R5 are mutually connected at a common node 21 which is in turn direct-coupled by lead 2y to the reference base 2! of transistor Q2 so as to apply thereto the reference potential.
  • the magnitude of resistor R4 is substantially less than that of resistor R5 so that the reference potential swing is approximately in phase with the swing of output 01 which is, except for a time delay, in phase with the input signal at input terminal I1.
  • the relative magnitudes of resistors R4, R5 are further selected so as to act as a voltage dividing attenuator to attenuate the amplitude of the reference potential swing at base 2b to a predetermined fraction of the amplitude of the output potential swing at ouput 01. Since the component parameters of the circuit are selected so that the circuit as a whole has unity gain, the amplitude swing at output 01 is substantially equal to that at input terminal I1 and hence the amplitude of the reference potential swing will be a predetermined fraction of the amplitude of the input potential swing.
  • the reference potential when the input potential is at its up level the reference potential will also be at its up level but below theinput level.
  • the reference potential when the input potential is at its down level, the reference potential will also be at its down level but at a somewhat higher level than that of the input potential.
  • This time delay of the reference potential may be provided either in the forward transmission path as in th embodiment of FIG. 1, or in the feedback network as embodied in other modified forms of the invention to be described below.
  • the time delay may be obtained as the inherent delay in the transistors or other active devices, or may be provided by a delay line or other component expressly designed for that purpose.
  • the delay may also be provided by various combinations of these factors; that is, partially in the forward transmission path and partially in the feedback network, and/ or partially in the inherent transistor structure and partially in a separate delay line.
  • the delay arises primarily in the forward transmission path from the input I1 to the outputs O1, O2 and is due to the delays caused by the junction capacitances and diffusion phenomena inherent in the structure of the several transistors.
  • the reference potential variation shown in FIG. 6 may be obtained by means other than direct-current negative feedback, as will be explained in connection with a modified form of the invention where the reference potential is derived from the input, the feedback approach is highly advantageous in that it automatically corrects any undesired variations due to component tolerances, input level deviations, temperature-induced variations, and power supply tolerances. For example, if the quiescent input potential level should change due to some variation in a preceding circuit, the negative feedback network will cause the quiescent reference potential level to change in the same direction and by almost the same amount so as to maintain substantially the same potential difference between the two levels.
  • the circuit will neither switch inadvertently due to an unintentional traverse of the two potentials, nor will its switching action be slowed down due to an excessive difference in the two levels.
  • the circuit may be embodied in economical form with inexpensive components and power supplies while maintaining reliability of operation and high switching speed.
  • FIG. 2 there is shown schematically a switching circuit illustrating the basic inventive concept utilizing negative feedback to derive the reference potential.
  • a switching element 11 is actuated to switch from one of its binary states to the other in response to traversal of the respective potentials at the signal input 12 and the reference input 13.
  • Extending from output 14 is a feedback network comprising a delay 15 and an attenuator 16 in series between output 14 and reference input 13.
  • Delay 15 may instead be embodied in the structure of switching element 11 or may be placed in the forward transmission path between switching element 11 and output 14.
  • the improvement in switching speed provided by the present invention over the'prior art may be demonstrated by an experimental setup wherein four transistors are mounted on a module which is then plugged into either of two positions on a printed-circuit board so as to obtain either the conventional emitter follower type current switch in accordance with the prior art as shown in FIG. 3 or the circuit of FIG. 1 embodying the present inventron, whereby both circuits may be tested and compared using the identical set of four transistors.
  • FIGS. 7 and 8 show the input and output traces obtamed with the circuit of FIG. 3, and FIGS. 11 and 12 show the input and output traces obtained with the circuit of FIG. 1.
  • the horizontal scale is one nanosecond per centimeter and the vertical scale is 200 millivolts per centimeter.
  • the ground reference is shown by the horizontal line identified by the ground symbol.
  • the generally employed figure of merit for switching speed is the propagation delay which is the time period from the instant of time when the input signal reaches its midpoint between its two quiescent levels and the instant of time when the output signal reaches its midpoint.
  • the propagation delay during the rise of the input potential is about 4.2 nanoseconds
  • the propagation delay of the in-phase output 01 is 2.2 nanoseconds
  • the out-of-phase output 02 has a propagation delay of 2.4 nanoseconds.
  • the propagation delay of output 03 is 2.0 nanoseconds for the prior art circuit
  • the propagation delay is 2.2 nanoseconds for the in-phase output 01 and 1.8 nanoseconds for the out-ofphase output 02 for the present invention of FIG. 1.
  • FIG. 13 shows the traces of the input and reference potentials for the circuit of FIG. 1.
  • FIG. 4 shows a modification of the prior art current switch of FIG. 3 in that the second stage constitutes a differential amplifier similar to the second stage of FIG. 1 rather than an emitter follower. More specifically, the first stage constitutes a current switch comprising transistors Q9, Q10 having their collectors 90, 100 connected to power supply E6 through respective load resistors R15, R16.
  • the emitters 9e, 10e of transistors Q9, Q10 are connected to a source of constant current comprising a resistor R14 and a power supply E5.
  • the base 912 of transistor Q9 is direct-coupled to the input 13 and the base 10b of transistor Q10 is connected to a fixed reference potential which may be the same power supply E6.
  • the differential amplifier stage comprises a pair of transistors Q11, Q12 comprising collectors 11c, 12c connected to ground through the respective load resistors R17, R18; emitters 111e, 12e connected to a source of constant current comprising power supply E and resistor R19; and bases 11b, 12b direct-coupled by leads 9x, x to the respective collectors 90, 100 of transistors Q9, Q10.
  • the in-phase output 05 is taken from the collector 110 of transistor Q11 and the out-of-phase output 06 is taken from collector 120 of transistor Q12. It will thus be seen that the circuit of FIG. 4 is identical to that of FIG. 1 except that the reference base 10b is provided with a fixed reference potential by the power supply E6 instead of with 10 the time-delayed in-phase reference potential provided at the base 2b by the feedback network in FIG. 1.
  • the input and output traces of the circuit of FIG. 4 are shown in the oscilloscope photographs of FIGS. 9 and 10.
  • the horizontal scale is one nanosecond per centimeter and the vertical scale is millivolts per centimeter.
  • the propagation delay for the in-phase output during the rise of the input potential is about 3.2 nanoseconds and that for the out-of-phase output is about 3.6 nanoseconds.
  • the in-phase output has a propagation delay of 3.1 nanoseconds whereas that for the out-of-phase output is 2.7 nanoseconds. It will thus be seen that the present invention achieves a substantially faster switching speed solely by virtue of the time-delayed in-phase reference potential.
  • FIG. 14 shows such a circuit connected so as to perform the usual closed-loop test whereby the output is connected to the input so that the circuit drives itself.
  • transistors Q13 and Q14 constitute a current switch and are provided with collectors 13c, 14c connected to power supply E8 through respective load resistors R22, R23.
  • the emitters 132, 142 of transistors Q13, Q14 are connected at a common node to a constant current source comprising a power supply E7 and a resistor R21.
  • Transistors Q15 and Q16 constitute the second current switch which performs the function of a differential amplifier.
  • the collectors 15c are connected to ground through respective load resistors R26, R27.
  • the bases 15b, 16b of transistors Q15, Q16 are direct-coupled to the respective collectors 13c,
  • the in-phase output 07 at the collector 15c of transistor Q15 is unloaded.
  • the out-of-phase output 08 at the collector 160 of transistor Q16 is provided with six connections 16a to 16z inclusive to the respective bases of six transistors (not shown) constituting an active load on the out-of-phase output 08.
  • a transmission line 16t having its other end terminated in a load R20 and connected by lead 16s to the base 13b of transistor Q13.
  • the circuit of FIG. 14 is further provided with the same feedback network described above with respect to the modification of FIG. 1 and comprising a resistor R24 extending from the collector of transistor Q15 and a resistor R25 extending from the collector of transistor Q16 and joined to a common node which is in turn connected by lead 14y to the base 14b of transistor Q14.
  • the potential traces at input 165 and output 08 of the closed-loop test of FIG. 14 are shown in FIG. 18. During the input potential rise the propagation delay was 0.5 nanosecond, and during the input potential fall the propagation delay was 0.9 nanosecond. It will thus be seen that by using relatively fast transistors the subject invention achieves a propagation delay in the subnanosecond range.
  • the transistors employed for the close-loop test of FIG. 14 were IBM Type Y and had the following specifications:
  • FIG. 15 there is shown a modified form of the invention wherein, in addition to the delay inherent in the forward transmission path as provided by the transistors, the reference potential is further delayed by the addition of a capacitor in the feedback network.
  • the overdrive continually increases as the input potential continues to move in a direction away from the reference potential. The longer the reference po tential is maintained at its quiescent level after the instant of traversal, the greater will be the overdrive. The latter in turn provides a faster switching action.
  • transistors Q17 and Q18 constitute the first stage current switch and are provided with collector load resistors R30, R31 extending from collectors 17c, 180 to ground.
  • the emitters 17c, 18a of transistors Q17, Q18 are connected to a common node which is in turn connected through register R29 to a power supply E9 so as to provide a source of constant current.
  • the input I4 of the circuit is connected to the base of transistor Q17.
  • the second stage operates as a differential amplifier and comprises transistors Q19, Q20 having respective collector load resistors R34, R35 connected from collectors 19c,
  • the emitters 19c, 20c of transistors Q19, Q20 are connected to one end of resistor R36 having its opposite end connected to power supply E9 so as to pr vide a source of constant current.
  • the collector 17c f transistor Q17 is direct-coupled by lead 17x to the base 19b of transistor Q19 and the collector 18c of transistor Q18 is similarly direct-coupled by lead 18x to the base 20b of transistor Q20.
  • the feedback network comprises resistors R32, R33 each having an end connected respectively to the outputs O9, 010 and another end joined to a common node 181 and connected to lead 18y to the base 18b of transistor Q18.
  • the circuit of FIG. 15 is identical to that of FIG. 1.
  • an additional delay of the reference potential swing is provided by a capacitor C1 connected between the common node 181 of feedback resistors R32, R33 and ground.
  • the potential at node 182 instead of varying instantaneously therewith, will be delayed to the extent required by the charging or discharging of capacitor C1.
  • the reference potential at the base of transistor Q18 tends to maintain its quiescent level after traversal by the input potential so as to provide a larger overdrive to improve the switching speed of the circuit.
  • FIG. 16 there is shown a circuit diagram of a comparison test which demonstrates that the present invention does not depend for its improved switching speed upon the existence of the second differential amplifier stage as at Q3, Q4 in FIG. 1.
  • the circuit of FIG. 16 enables the identical transistor specimens to be arranged in either a conventional current switch having a fixed reference potential in accordance with the prior art, or as a current switch stage wherein the reference potential is derived by a negative feedback network in accordance with the present invention.
  • transistor Q21 has its collector 210 connected through load resistor R37 to a power supply E10. Its base 21b is connected to input I5 and its emitter 21e is connected to a constant current source comprising power supply E11 and resistor R38. The output 011 is taken at the collector 21c.
  • a second transistor is connected in the position shown in dash-dot lines at Q22 when inserted into one of the two sockets (not shown) and is in the position shown at Q22 when inserted into the other of the sockets.
  • the emitter 22e of the second transistor is connected to the junction of emitter 21a of transistor Q21 and resistor R38.
  • both the collector 22c and base 22b of the second transistor are grounded as shown, thereby providing a conventional current switch stage.
  • the second transistor when the second transistor is in the position at Q22, its collector 22c and base 22b are connected by leads 22x and 22y to the node 221 of a feedback network comprising resistors R39 and R40 connected in series between a power supply E10 and ground.
  • a further delay in the reference potential swing is provided by a capacitor C2 extending from the base 22b of the second transistor to ground.
  • FIG. 20 shows the input and out-of-phase output traces for the conventional circuit with the second transistor at the position Q22.
  • the propagation delays were 1.0 nanosecond and 0.8 nanosecond for rising and falling input potentials respectively.
  • FIG. 21 shows Propagation delays of 0.5 nanosecond and 0.6 nanosecond for rising and falling input potentials with the second transistor at the position Q22.
  • FIG. 19 shows the input and reference potential swings for the latter position.
  • FIG. 17 there is shown a modified form of the invention wherein the varying time-delayed in-phase reference potential is derived from the input rather than from the output as in the previously described modifications.
  • a pair of transistors Q23 and Q24 are arranged as a current switch with their respective emitters 23c, 24c connected through resistor R41 to a power supply E11.
  • the collectors 23c, 240 are connected to ground through respective load resistors R42, R43.
  • Outof-phase and in-phase outputs O12, 013 are taken from collectors 23c, 24c respectively.
  • the input node 16 is connected by lead 23x to the base 23b of transistor Q23.
  • the reference potential at the base 24b of transistor Q24 is instead derived from the input 16 by a network comprising lead 23y extending from said input to a delay 17, the output of which is fed to an attenuator 18 which is in turn connected to said reference base 24b.
  • attenuator 18 will maintain the reference potential swing at base 24b at a predetermined proportion of the input potential swing.
  • delay 17, which may be realized as a delay line or by other suitable means, will maintain the reference potential at its quiescent level until after traversal by the input potential.
  • the circuit of FIG. 17 will thus provide the input and reference potential traces shown in idealized form in FIG. 6 so as to operate in a manner somewhat similar to that of the previously described modifications employing feedback from the output.
  • Transistors Q Q constitute a current switch having their respective collectors 25c, 260 connected by load resistors R45, R46 to a power supply E13.
  • the emitters 25c, 26c are connected to a constant current source comprising power supply E12 and resistor R44.
  • the base 25b of transistor Q25 is connected to the input node 17.
  • Transistors Q27, Q28 constitute a differential amplifier.
  • the collectors 27c, 28c of transistors Q27, Q28 are connected through load resistors R49, R50 to ground.
  • the bases 27b, 28b of transistors Q27, Q28 are connected by respective leads 25x, 26x to the collector 25c, 26c of transistors Q25, Q26.
  • the in-phase output 014 is taken from the collector 270 of transistor Q27 and the out-ofphase output 015 is taken from the collector 28c of transistor Q28.
  • the emitters 27c, 28c of transistors Q27, Q28 are connected to a constant current supply comprising resistor R51 and power supply E12.
  • the feedback network comprises resistors R47 and R48 each having one end connected at the node 26y.
  • the latter is direct-coupled by lead 26z to the base 26b of transistor Q26.
  • the other end of resistor R47 is connected to the in-phase output 014.
  • the embodiment of FIG. 22 is identical to that of FIG. 1.
  • the other end of the resistor corresponding to resistor R48 is connected to the out-of-phase output.
  • the other end of resistor R48 is connected to ground as shown.
  • the reference potential is therefore derived solely from the in-phase output.
  • the feedback network is passive.
  • the feedback network is active in that it comprises a transistor which provides both level setting and an additional delay for the reference potential swing. More specifically, transistors Q29, Q30 constitute a current switch and have their collector 29c, 30c connected through load resistors R53, R54 to a power supply E15 and their emitters 29c, 302 connected to a constant current source comprising power supply E14 and resistor R52.
  • the base 2% of transistor Q29 is direct-coupled to the input node 18.
  • Transistors Q31, Q32 constitute a differential amplifier and have their respective collectors 31c, 320 connected to ground through load resistors R56, R57, their bases 31b, 32b direct-coupled by leads 29x, 30x to collectors 29c, 30c of transistors Q29, Q30, and their emitters 31c, 32c connected to a constant current source comprising a power supply E14 and resistor R55.
  • the outputs O16, 017 are taken respectively from collectors 31c, 32c of transistors Q13, Q32.
  • the feedback network is taken from the out-of-phase output 017 and comprises a transistor Q33 having its base 33b direct-coupled to said output 017, its collector 330 connected through load resistor R58 to ground, and its emitter 33c connected through resistor R59 to power supply E15.
  • a resistor R60 is connected between collector 33c and emitter 33c to provide flexibility in design whereby the upper and lower limits of the reference potential swing may be adjusted to the desired magnitudes.
  • the feedback signal is derived from the collector 33c and is applied through lead 33x to the base 30b of transistor Q30 so as to provide the latter with a time-delayed in-phase reference potential as shown in FIG. 6.
  • the active feedback network of FIG. 23 may also be utilized in a current switch circuit having only a single stage as shown in FIG. 24 wherein transistors Q34, Q35 constitute the current switch and are provided with collectors 34c, 35c connected to power supply E16 through load resistors R61, R63 and emitters 34c, 35c connected to a constant current source comprising power supply E17 and resistor R62.
  • the base 34b of transistor Q34 is connected to the input node 19.
  • Theout-of-phase output 018 is taken from the collector 34c of transistor Q34 and the in-phase output 019 is taken from the collector 35c of transistor Q35.
  • the feedback network comprises transistor Q36 having its collector 36c connected through load resistor R64 to power supply E16, its base 36b direct-coupled by lead 34x to collector 34c of transistor Q34, and its emitter 362 connected to power supply E17 through resistor R65.
  • Resistor R66 extends between collector 36c and emitter 36c to provide flexibility in design as noted above with respect to resistor R60.
  • Transistor Q36 serves to invert the outof-phase signal at output 018, further delay said signal, and set the signal to the proper level. The resulting timedelayed in-phase signal is then applied as the reference potential by lead 36x to the base 35b of transistor Q35 so as to obtain the mode of operation illustrated in FIG. 6.
  • FIG. 25 shows another modification wherein the invention is embodied in the current switch of the emitter follower type.
  • the current switch function is provided by the first stage comprising transistors Q37 and Q38 having collectors 37c, 380 connected through load resistors R67, R68 to power supply E18 and emitters 37c, 38c connected to a constant current source comprising resistor R69 and power supply E19.
  • the base 37b of transister Q37 is connected to the input I10.
  • the second stage functions as an emitter follower and comprises transistors Q39, Q40 having collectors 39c, 4 0 c connected to power supply E18, bases 39b, 40b directcoupled by leads 37x, 38x to the respective collectors 37c, 38c of transistors Q37, Q38, and emitters 39c, 40c connected through respective emitter resistors R70, R71 to power supply E19.
  • the out-of-phase output 020 is taken from emitter 39e and the in-phase output 021 is taken from emitter 40e.
  • the reference potential is derived from the in-phase output 021 by a feedback network comprising resistors R72 and R73 each having one end joined at the node 38y.
  • the opposite end of resistor R72 is connected to the inphase output 021 and the opposite end of resistor R73 is grounded as shown.
  • a lead 382 extends from node 38y to the base 38b of transistor Q38 so as to apply thereto the time-delayed-in-phase reference potential related to the input potential in the manner disclosed in FIG. 6.
  • FIG. 26 shows still another modified form of the invention embodying the negative feedback network of FIG. 1 in combination with a positive feedback network to further increase the switching speed.
  • the first stage is a current switch comprising transistors Q41 and Q42 having respective collectors 41c, 42c connected to ground through load resistors R74, R76 and emitters 41c, 42e connected to a constant current supply comprising resistor R75 and power supply E16.
  • the base 41b of transistor Q41 is connected to the input Ill.
  • the second stage functions as a differential amplifier and comprises transistors Q43, Q44 having collectors 43c, 440 connected to ground through load resistor R79, R81 and emitters 43a, 44e connected to a constant current source comprising resistor R80 and power supply E16.
  • the in-phase output 018 is taken from collector 42c and the out-of-phase output 019 is taken from collector 440.
  • the negative feedback network comprises a pair of resistors R77, R78 each having one end connected to a node 42y.
  • the opposite end of resistor R77 is connected to the in-phase output 018 and the opposite end of resistor R78 is connected to the out-of-phase output 019.
  • Node 42y is connected through leads 42z and 42w to the base 42b of transistor Q42 so as to apply thereto the time-delayed in-phase reference potential.
  • FIG. 26 is identical to that of FIG. 1.
  • the positive feedback network added to the circuit of FIG. 26 is illustrated in the form of a capacitor C3 having one end connected to collector 410 of transistor Q41 through lead 41x and the other end connected to base 42b of transistor Q42 through lead 42w.
  • the effect of capacitor C3 may be best understood by reference to FIG. 28 showing idealized traces of the input and reference potentials during the switching operation. It will be seen that the reference potential, instead of remaining at its quiescent level until after traversal by the input potential as shown in FIG. 6 in connection with the circuit modification of FIG. 1, is urged by the positive feedback eifect of capacitor C3 in a direction opposite to the direction of swing of the input potential so as to cause a mutual traverse.
  • This mode of operation increases the switching speed because of two effects.
  • the circuit of FIG, 27 may be particularly advantageous in that is provides both negative and positive feedback networks similar to FIG. 26 but without requiring a capacitor.
  • the first stage of FIG. 27 functions as a current switch and comprises transistors Q45, Q46 having collectors 45c, 46c connected to ground through load resistors R82, R84, and emitters 45e, 46c connected to a constant current source comprising resistor R83 and power supply E17.
  • Base 45b of transistor Q45 is connected to input node I12.
  • the second stage constituting the differential amplifier comprises a pair of transistors Q47, Q48 having collectors 47c, 48c connected to ground through load resistors R87, R89 and emitters 47e, 48e connected to a constant current source comprising resistor R88 and power supply E17.
  • the base 47b of transistor Q47 is direct-coupled by lead 45x to the collector 45c of transistor Q45, and the base 48b of transistor Q48 is similarly direct-coupled'by lead 46x to the collector 46c of transistor Q46.
  • the inphase output 020 is taken from the collector 47c of transistor Q47 and the out-of-phase output 021 is taken from the collector 48c of transistor Q48.
  • the negative feedback network comprises a resistor R86 having one end connected to the in-phase output 020 and the other end connected to the reference base 46b of transistor Q46 through leads 46y and 46z.
  • the positive feedback network comprises a resistor R having one end connected to collector 450 of transistor Q45 through lead 45x and its other end connected to reference base 46b of transistor Q46 through lead 46z.
  • a switching circuit comprising an input node,
  • a logic circuit comprising an input node,
  • a switching circuit comprising .an input node for receiving an input signal having a v i a network to vary the reference potential with an amplitude less than that of the input signal and approximately in phase therewith but with a time delay with respect thereto.
  • a logic switching circuit comprising a reference node
  • an active element switchable from one state to another in response to the potential of the input node traversing the potential of the reference node
  • a feedback network to vary the potential of said reference node in time-delayed phase with any variation of the potential of the input node.
  • a logic switching circuit comprising a reference node
  • a feedback network extending from said output network to said reference node to vary the potential of the latter in time-delayed phase with any variation of the potential of the input node.
  • a logic switching circuit comprising a reference node
  • said active element including means for delaying the effect of said feedback network until said input node potential traverses said reference node potential.
  • a logic switching circuit comprising a reference node
  • an output network for connecting said binary element a feedback network extending from said binary element to said reference node to maintain the quiescent potential of the latter at a predetermined increment from the quiescent potential of the input node in both states of said binary element.
  • a logic circuit comprising an input node,
  • a logic switching circuit comprising a reference node
  • a logic switching circuit comprising a reference node, t I
  • a direct-current negative feedback network extending from said attenuator to said reference node to apply thereto said attenuated output signal.
  • a logic switching circuit comprising a reference node
  • a feedback network extending from said attenuator to said reference node to apply thereto said attenuated delayed signal.
  • a logic switching circuit comprising a reference node
  • a current switch actuable to switch a constant current from one path to another in response to the potential of the input node traversing the potential of the reference node
  • a feedback network extending from said attenuator to said reference node to apply thereto said delayed attenuated signal.
  • a transistor switching circuit having a source of constant current, a source of reference potential, a plurality of asymmetric impedance current paths connected in the forward direction between said current source and said reference potential, at all times at least one of which is carrying said constant current and at least one of which is the path from emitter to collector of a transistor, and an input node, the improvement comprising a network to maintain the quiescent condition of said circuit on the threshold of switching.
  • a logic switching circuit comprising:
  • an output network having an in-phase output node and an out-of-phase output node, said network being responsive to said active element, for providing two outputs,
  • a second attenuator having a value of resistance greater than that of the first attenuator, connected between the out-of-phase output node and the reference node, and
  • a logic switching circuit comprising:
  • an output network having an in-phase output node and an out-of-phase output node, said network being responsive to said active element, for providing two outputs,
  • a second attenuator having a value of resistance greater than that of the first attenuator, connected between the out-of-phase output node and the reference node,
  • a transistor switching circuit having a source of constant current, a source of reference potential, a plurality of assymetric impedance current paths connected in the forward direction between said current source and said reference potential, at all times at least one of which is carrying said constant current and at least one of which is the path from emitter to collector of a transistor, an input node, said constant current being switchable from one path to another in response to the potential of the input node traversing the reference potential, and an output network for connecting said circuit to a load, the improvement comprising a direct-current negative feedback network extending from said output network to said reference potential to maintain the quiescent value of the latter at a pre determined increment from the quiescent potential of the input node.
  • a transistor switching circuit having a source of constant current, a source of reference potential, a plurality of asymmetric impedance current paths connected in the forward direction between said current source and said reference potential, at all times at least one of which is carrying said constant current and at least One of which is the path from emitter to collector of a transistor, an input node, said constant current being switchable from one path to another in response to the potential of the input node traversing the reference potential, and an output network for connecting said circuit to a load, the improvement comprising a negative feedback network extending from said output network to said reference potential source to vary the potential of the latter in time-delayed phase with any variation of the potential of the input node, and
  • a transistor switching circuit having a common point, a source of constant current, means connecting said source of constant current to said common point, a reference potential, a plurality of asymmetric impedance current paths connected in the forward direction between said common point and said reference potential at least one of said paths being from emitter to collector of a transistor, means operable to cause said constant current to flow at all times through at least one of said paths, and
  • sensing means associated with at least one of said paths, an input node, said constant current being switchable from one path to another in response to the potential of the input node traversing the reference potential, and an output network for connecting said circuit to a load, the improvement comprising an attenuator for attenuating the signal at said output network, and a feedback network extending from said attenuator to provide said reference potential in the form of said attenuated signal.
  • a transistor switching circuit having a common point, a source of constant current, means connecting said source of constant current to said common point, a reference potential, a plurality of asymmetric impedance current paths connected in the forward direction between said common point and said reference potential, at least one of said paths being from emitter to collector of a transistor, means operable to cause said constant current to flow at all times through at least one of said paths, and sensing means associated with at least one of said paths, an input node, said constant current being switchable from one path to another in response to the potential of the input node traversing the reference potential and an output network for connecting said circuit to a load, the improvement comprising means for delaying the signal at said output network with respect to the signal at said input node,
  • a feedback network extending from said attenuator to provide said reference potential in the form of said delayed attenuated signal.
  • a logic switching circuit comprising:
  • an output network having an in-phase output node and an out-of-phase output node, said output network being responsive to said active element, for providing two outputs, and
  • a feedback network connected between the in-phase output node and the reference node for providing said reference node with a reference potential.
  • a switching circuit comprising an input node,
  • a direct-current negative feedback network to maintain the quiescent value of the reference potential within a predetermined incremental range about the quiescent potential of the input node
  • a network to urge the reference potential in a direction opposite to the swing of the input potential during the switching of said active element.

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  • Mathematical Physics (AREA)
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US495943A 1965-10-14 1965-10-14 Threshold logic switch with a feed-back current path Expired - Lifetime US3458719A (en)

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Cited By (14)

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US3509363A (en) * 1965-10-14 1970-04-28 Ibm Logic switch with active feedback network
US3562549A (en) * 1968-05-21 1971-02-09 Molekularelektronik Semiconductor logic circuit
US3787734A (en) * 1972-05-26 1974-01-22 Ibm Voltage regulator and constant current source for a current switch logic system
JPS49141742U (enExample) * 1973-04-10 1974-12-06
JPS513565A (ja) * 1974-06-26 1976-01-13 Yokogawa Electric Works Ltd Hansoshingonofukuchokairo
JPS522154A (en) * 1975-06-23 1977-01-08 Fuji Electric Co Ltd Waveform shaping circuit
US4112314A (en) * 1977-08-26 1978-09-05 International Business Machines Corporation Logical current switch
JPS56109028A (en) * 1980-02-01 1981-08-29 Matsushita Graphic Commun Syst Inc Binary value discriminating system and its device
US4287435A (en) * 1979-10-05 1981-09-01 International Business Machines Corp. Complementary transistor inverting emitter follower circuit
US4289978A (en) * 1979-10-05 1981-09-15 International Business Machines Corp. Complementary transistor inverting emitter follower circuit
US4311925A (en) * 1979-09-17 1982-01-19 International Business Machines Corporation Current switch emitter follower latch having output signals with reduced noise
US4363008A (en) * 1979-05-09 1982-12-07 Tellabs, Inc. Electronic transformer
US4709166A (en) * 1986-05-22 1987-11-24 International Business Machines Corporation Complementary cascoded logic circuit
US5043602A (en) * 1990-03-26 1991-08-27 Motorola, Inc. High speed logic circuit with reduced quiescent current

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Publication number Priority date Publication date Assignee Title
US4585952A (en) * 1982-03-04 1986-04-29 Sansui Electric Co., Ltd. Digital waveform shaping circuit

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US2964652A (en) * 1956-11-15 1960-12-13 Ibm Transistor switching circuits
US3181007A (en) * 1962-09-07 1965-04-27 Sperry Rand Corp Automatic contrast circuit employing two cascaded difference amplifiers for changing slope of information signal
US3198963A (en) * 1963-01-14 1965-08-03 Burroughs Corp Electronic circuit for generating linear time-base waveforms
US3239694A (en) * 1963-09-25 1966-03-08 North American Aviation Inc Bi-level threshold setting circuit
US3278770A (en) * 1962-08-02 1966-10-11 Branson Instr Extremal-centering method and system
US3302034A (en) * 1963-04-24 1967-01-31 Gen Electric Pulse processing circuits having automatic threshold level control
US3316404A (en) * 1964-06-01 1967-04-25 Santa Barbara Res Ct Infrared detecting system having a memory circuit utilizing a differential amplifier
US3329835A (en) * 1964-11-20 1967-07-04 Rca Corp Logic arrangement

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US2964652A (en) * 1956-11-15 1960-12-13 Ibm Transistor switching circuits
US3278770A (en) * 1962-08-02 1966-10-11 Branson Instr Extremal-centering method and system
US3181007A (en) * 1962-09-07 1965-04-27 Sperry Rand Corp Automatic contrast circuit employing two cascaded difference amplifiers for changing slope of information signal
US3198963A (en) * 1963-01-14 1965-08-03 Burroughs Corp Electronic circuit for generating linear time-base waveforms
US3302034A (en) * 1963-04-24 1967-01-31 Gen Electric Pulse processing circuits having automatic threshold level control
US3239694A (en) * 1963-09-25 1966-03-08 North American Aviation Inc Bi-level threshold setting circuit
US3316404A (en) * 1964-06-01 1967-04-25 Santa Barbara Res Ct Infrared detecting system having a memory circuit utilizing a differential amplifier
US3329835A (en) * 1964-11-20 1967-07-04 Rca Corp Logic arrangement

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3509363A (en) * 1965-10-14 1970-04-28 Ibm Logic switch with active feedback network
US3562549A (en) * 1968-05-21 1971-02-09 Molekularelektronik Semiconductor logic circuit
US3787734A (en) * 1972-05-26 1974-01-22 Ibm Voltage regulator and constant current source for a current switch logic system
JPS49141742U (enExample) * 1973-04-10 1974-12-06
JPS513565A (ja) * 1974-06-26 1976-01-13 Yokogawa Electric Works Ltd Hansoshingonofukuchokairo
JPS522154A (en) * 1975-06-23 1977-01-08 Fuji Electric Co Ltd Waveform shaping circuit
US4112314A (en) * 1977-08-26 1978-09-05 International Business Machines Corporation Logical current switch
US4363008A (en) * 1979-05-09 1982-12-07 Tellabs, Inc. Electronic transformer
US4311925A (en) * 1979-09-17 1982-01-19 International Business Machines Corporation Current switch emitter follower latch having output signals with reduced noise
US4287435A (en) * 1979-10-05 1981-09-01 International Business Machines Corp. Complementary transistor inverting emitter follower circuit
US4289978A (en) * 1979-10-05 1981-09-15 International Business Machines Corp. Complementary transistor inverting emitter follower circuit
JPS56109028A (en) * 1980-02-01 1981-08-29 Matsushita Graphic Commun Syst Inc Binary value discriminating system and its device
US4709166A (en) * 1986-05-22 1987-11-24 International Business Machines Corporation Complementary cascoded logic circuit
US5043602A (en) * 1990-03-26 1991-08-27 Motorola, Inc. High speed logic circuit with reduced quiescent current

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JPS4423362B1 (enExample) 1969-10-04
GB1164167A (en) 1969-09-17

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