US3408539A - Electric timing circuits - Google Patents

Electric timing circuits Download PDF

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Publication number
US3408539A
US3408539A US544583A US54458366A US3408539A US 3408539 A US3408539 A US 3408539A US 544583 A US544583 A US 544583A US 54458366 A US54458366 A US 54458366A US 3408539 A US3408539 A US 3408539A
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Prior art keywords
circuit
capacitor
transistor
input
voltage
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Expired - Lifetime
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US544583A
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English (en)
Inventor
Legg Malcolm
Patrickson John Brian
Wedepohl Leonhard Martin
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A Reyrolle and Co Ltd
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A Reyrolle and Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • G—PHYSICS
    • G04—HOROLOGY
    • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
    • G04C23/00—Clocks with attached or built-in means operating any device at preselected times or after preselected time-intervals
    • G04C23/02—Constructional details
    • G04C23/12—Electric circuitry
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/08—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current
    • H02H3/093—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to excess current with timing means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching

Definitions

  • Timing circuits are provided for producing a delay in the generation of a control signal in response to an initiating signal by means of integrating circuits.
  • An initiating circuit is included for providing a constant pre-charge to the integrating circuit and a discharging network is provided for discharging the integrating circuit to a voltage below that produced by the constant pre-charge to insure that the integrating circuit is always activated at a constant starting voltage.
  • An input signal shaping circuit may be included for providing an initiating signal proportional to a selected function of the input current and to provide a time lag in the generation of the control signal that is inversely proportional to the selected function of the input current.
  • This invention relates to electric timing circuits including an integrating capacitor, means for charging it progressively, from what may be termed an initiating moment, and means responsive to the capacitor voltage reaching a predetermined value.
  • the invention is applicable to a wide variety of systems requiring a consistent and repeatable time interval under different conditions.
  • it is applicable to protective systems, control systems or signalling or telemetry systems, and can be adapted for time intervals of a very Wide range of durations from fractions of a millisecond or less, to hundreds of seconds or more.
  • One application of the invention is to protective systems in which the timing circuit forms part of a delayed time lag relay for introducing delay before the tripping of circuit breakers after an initiating signal has been supplied to the timing circuit from an initiating circuit.
  • the initating circuit may of course respond to various different conditions or parameters.
  • the circuit is characterized by means for imparting to the capacitor an initial charge to a predetermined low voltage substantially instantaneously at the initiating moment.
  • the timing charge may be obtained from a timing supply in which case the initial charge may be obtained from a comparatively low voltage supply through a diode.
  • the low voltage supply may be afforded by a potential divider connected across the timing supply.
  • the potential divider includes at least one diode.
  • the means responsive to the capacitor voltage comprises a trigger circuit controlling an output circuit.
  • the discharge of the capacitor is effected by the cessation of the input signal.
  • the capacitor will be discharged to give a full delay period when the next input signal occurs.
  • the discharge path is of sutiiciently low resistance to discharge the capacitor comparatively rapidly (in relation to the delay time) down to. a voltage less than that of the low voltage supply.
  • the capacitor forms part of a resistor capacitor integrating network.
  • the capacitor forms the feedback capacitor of a Miller integrator.
  • FIGURE 1 is a circuit diagram of a definite time lag relay, employing an RC integrator, for a protective system;
  • FIGURE 2 is a similar circuit employing at Miller integrator and capable of being used either for a definite time lag or for an inverse time lag relay;
  • FIGURE 3 is a similar circuit of a further arrangement primarily intended for an inverse time lag relay.
  • the arrangement includes an initiating circuit which forms no part of the present invention and will not be described in detail.
  • the initiating circuit may be arranged to close contacts and keep them closed to connect a supply to the timing circuit from the initiating moment when the relevant condition subsists.
  • the initiating contacts may close only for part of each cycle or halfcycle of an alternating supply, from the time that the relevant condition subsists. 1
  • the initiating circuit responds to over current and its output includes a reed type relay 10 which is energised when the initiating circuit responds to over current and then closes its contacts 11 and keeps them closed, in order to initiate a timed period.
  • the timing circuit is energised from a timing supply represented by a pair of Zener diodes 12 connected to.a D.C. supply 14 (for example of 50 volts) in series with a resistor 15 and with the initiating contacts 11 of the reed relay of the initiating circuit.
  • a timing supply represented by a pair of Zener diodes 12 connected to.a D.C. supply 14 (for example of 50 volts) in series with a resistor 15 and with the initiating contacts 11 of the reed relay of the initiating circuit.
  • the purpose of the Zener diodes is to provide a reduced voltage.
  • the value of the voltage is not critical to the operation, and if a lower voltage supply is employed the Zener diodes 12 may be omitted.
  • a resistor capacitor network Connected across the timing supply represented by the Zener diodes is a resistor capacitor network comprising a resistor 19 in series with the timing capacitor 20. Accordingly when a signal is received from the initiating circuit, that is to say when the reed contacts 11 close, a timing supply is established and the timing capacitor 20 begins to charge up through the resistor 19.
  • a trigger circuit Connected to the junction 21 of the resistor capacitor network is a trigger circuit comprising a pair of transistors 22 and 23, one NPN and the other PNP, each having its base connected to the collector of the companion transistor.
  • the PNP transistor 22 has its emitter connected to the tapping of a potential divider 24, 25 connected across the supply, and its base (and the collector of the NPN transistor) connected to the junction 21 of the resistor capacitor network.
  • the emitter of the NPN transistor 23 is connected through a resistor 26 to the base of an output transistor 27 of N PN type having its emitter connected to the negative terminal of the timing supply and its collector connected through an output realy coil 30 to the positive terminal of the supply.
  • the output relay coil 30 is shunted by a diode 31 and controls contacts 32 connected across a suitable supply 33 in series with a holding relay coil 34 and a tripping coil 36.
  • the holding relay has contacts 37 in parallel with the output relay contacts 32.
  • the two trigger transistors operate with a snap action in known manner.
  • the base of the PNP transistor 22 is at substantially the same potential as the positive terminal of the supply whereas the emitter is more negative due to the drop in the resistor 25 of the potential divider 24, 25 connected across the supply.
  • the arrangement so far described has the disadvantage that if there is any initial charge on the timing capacitor the delay period will be correspondingly reduced. This may occur in various ways.
  • the normal low-impedance path for the discharge of the timing capacitor is through the base emitter path of the transistor 22. This offers an easy path for current until the voltage falls to a certain low value, generally referred to as the toe value, after which the impedance greatly increases. Hence the capacitor voltage will fall rapidly to a low value, possibly of the order of half a volt, after which further discharge will occur much more slowly through a comparatively high impedance path including the resistance 19 of the resistor capacitor network and the whole of the potential divider 24, 25.
  • the capacitor may also acquire an initial charge due to the phenomenon known as dielectric absorption.
  • means for imparting to the capacitor an initial charge to a predetermined low voltage substantially instantaneously at the initiating moment.
  • the term substantially instantaneously is used in this connection to mean in a period that is short in relation to the total time lag period.
  • a further potential divider is connected across the supply and its tapping is connected to the junction 21 of the resistor capacitor network through a precharging diode 41.
  • the potential divider may also include .a pair of diodes 44 and 45 at its positive end poled so as to permit flow of current through the potential divider from the supply.
  • the toe voltage of one of these diodes serves to compensate for that of the precharging diode 41, whilst that of the other compensates for that of the PNP trigger transistor 22.
  • the compensation can be maintained under conditions of varying temperature.
  • the capacitor when the supply is switched on by the initiating circuit the capacitor is rapidly charged to a comparatively low voltage through the diode 41 and potential divider 42 to 45. The time taken for this to occur is negligible in comparison with the delay period imposed by the timing circuit. As soon as the capacitor has been charged to a voltage corresponding to that of the potential divider 42 to 45 the latter plays no further part in the operation of the circuit and any discharge through the potential divider is prevented by the precharging diode 41.
  • the values of quantities involved may vary in accordance with requirements but by way of example if a charge of some 12 volts is required to actuate the .4 trigger circuit the initial charge might be of the order of a volt.
  • the timing capacitor forms part of a resistor capacitor integrating network.
  • it forms the feedback capacitor of a Miller integrator.
  • this comprisesan amplifier, conveniently consisting of these transistors 50, 51 and 52 in cascade, of which the output transistor 52 is connected across the supply in series with an emitter resistor 53 and a pair of collector resistors 54 and 55.
  • the base of the input transistor is connected to the positive supply terminal through one of a pair of timing resistors 56 and 57, selected by a switch 58, and through the timing capacitor 60 to the collector circuit of the output transistor 52.
  • the circuit When the supply is switched on, the circuit operates in the manner of a normal Miller integrator and the output voltage obtainable from the collector of the output transistor progressively rises. This is supplied to any suitable output trigger circuit so as to respond when the voltage reaches a predetermined value.
  • a pair of diodes 61 and 62 are included connecting the two terminals of the timing capacitor respectively to the terminals of the timing circuit.
  • one diode 62 is in parallel with the output resistor 55 and the other diode 61 is in parallel with the input resistor 56 or 57.
  • these diodes provide rapid discharge of the capacitor down to a voltage of approximately half a volt for each diode (known as the toe voltage of the diode) at which their impedance rapidly rises. Thereafter the capacitor will discharge much more slowly through the input and output resistors.
  • the capacitor is connected to the junction between the two collector resistors 54 and 55 of the output transistor rather than directly to the collector of that transistor.
  • the operation of the integrator differs somewhat from that of the normal Miller integrator.
  • it comprises an output stage comprising a transistor with its emitter connected to an earthed negative supply terminal
  • any flow of input current into the input of the amplifier will produce a change of output current suificient to ensure that a feedback current will flow back through the capacitor sufficient to nullify such input current.
  • the capacitor will accept substantially the whole of the input current and the input point of the amplifier will remain at constant potential, for example will be a virtual earth.
  • the capacitor charges up comparatively rapidly to a voltage dependent on the value of the resistor 54 quite independently of any input current.
  • This voltage is arranged to be in excess of the combined toe voltages of the three transistors.
  • the input current may be obtained in various ways depending on requirements.
  • the circuit of FIGURE 2 is intended for a fixed time lag and accordingly the input current is obtained by applying a constant voltage to the input resistor 56 or 57. For this purpose instead of being connected directly to the positive supply terminal a potential divider connected across the supply.
  • the base voltage of the input transistor 50 will be made up not only of the toe voltages of the three transistors but of those voltages plus the drop across the portion 53 of the potentiometer and hence will be less affected by variations of the toe voltages (due to temperature or changes of transistors).
  • the collector of the transistor 52 is connected through a potentiometer 64 to the positive supply terminal and the tapping is connected to the input of a combined amplifier and trigger circuit comprising four PNP transistors 65, 66, 67 and 68. The first three of these are connected in cascade, the emitter of each to the base of the next, the first two sharing a common collector resistor 69.
  • the third and fourth transitsors 67 and 68 share a common emitter resistor 70 connecting their emitters to the positive supply terminal, and the collector of the third transistor 67 is connected through a resistor 71 and a Zener diode 72 to the base of the fourth transistor 68 so as to form a trigger circuit of the known Schmidt type.
  • the collector circuits of the third and fourth transistors 67 and 68 are interchangeable.
  • One includes a resistor 73 while the other includes a resistor 74 in series with the coil of a relay 75, both being shunted by a diode 76.
  • the voltage across the potentiometer 64 gradually buids up until the transistors 65, 66 and 67 conduct and the transistor 68 cuts off. If delayed operation is required the relay will be placed in the collector circuit of the transistor 67, by suitable manipulation of links 77 or the like, whereas if delayed reset is required it will be placed in the collector circuit of the transistor 68 as shown.
  • the arrangement shown in FIGURE 2 is intended to give a constant delay time and accordingly the input resistor is connected direct to the positive supply terminal while the emitter of the output transistor 52 is connected to the tapping of the potentiometer 53, 63, so that a constant potential difference is applied to the input resistor. If it is required to give a time lag varying inversely as an input quantity, the base of the input transistor may be connected to the positive supply terminal through an input resistor in series with input terminals to which the said input signal is applied.
  • FIGURE 3 is intended for an inverse definite minimum time lag relay, and while it employs a Miller integrator as in FIGURE 2 the trigger circuit is virtually the same as that of FIGURE 1 and corresponding parts bear the same reference numerals.
  • the circuit is energised from the initiating circuit but a shaping circuit generally indicated by the reference numeral 80 is connected to an input 81 from a current transformer, and through a resistor 82 to the negative supply terminal and through a diode 83 to the positive supply terminal, while its output is connected to the base of a transistor 85 of PNP type forming the input to the Miller integrator.
  • the transistor 85 has its emitter connected to the positive supply terminal and its collector connected through a resistor 87 to the base of a second transistor 88, of NPN type, which in turn is connected through a capactior 89 to the negative supply terminal.
  • the emitter of the transistor 88 is connected to the negative supply terminal while its collector is connected through a resistor 90 to the base of a third transistor 91 of PNP type.
  • the emitter of the transistor 91 is connected to the positive supply terminal while its collector is connected through a pair of resistors 92 and 93 to the negative supply terminal.
  • the junction point 94 between the two collector resistors 92 and 93 is connected to the positive supply terminal through a potentiometer 95 and is also connected through a feedback capacitor 96 to the base of the first transistor 85.
  • junction point 94 and hence one terminal of the capacitor is connected through a diode 97 to the negative terminal of the supply while the other terminal of the capacitor, and hence the base of the first transistor 85, is connected through a diode 98 to the positive supply terminal.
  • the tapping of the potentiometer 95 is connected through a diode 99 t0 the input of a trigger circuit which is similar to that of FIGURE 1 and bears the same reference numerals.
  • the emitter of the input transistor is connected to the positive supply terminal so that the voltage of its base differs from that of this terminal by only a single toe voltage of perhaps half a volt, which can be balanced by the use of a resistor and a diode, and the potentiometer 53, 63 of FIGURE 2 is not required.
  • the emitter of the output transistor 91 is connected directly to the positive supply terminal. This means that a greater proportion of the supply voltage, determined by the Zener diodes 12, is available for timing since the available range is not reduced by dropping part of its across the portion 53 of the potential divider.
  • the circuit is energised by the input signal.
  • it may be continuously energised from a separate supply, the initiation of the time delay being etfected for example by a circuit including a switching device shunted across the capacitor.
  • a timing circuit for providing a delayed control signal in response to an initiating signal comprising:
  • a source for providing power to the timing circuit said source including first and second terminals,
  • a Miller integrator including a transitsor amplifier, in-
  • an input circuit for providing an initiating signal to the timing circuit, said input circuit being connected between said input terminal and said second terminal,
  • said output circuit connected across said source and to said output terminals, said output circuit including a pair of resistors connected in series between said first output terminal and said first terminal,
  • said integrator including a pair of diodes, said capacitor connected between said first and second terminals in series with and between said diodes, said diodes being poled to rapidly discharge said capacitor in response to the termination of the initiating signal, and
  • said output circuit further including means for interconnecting said input terminal with the junction of said pair of resistors to rapidly charge said capacitor to a pre-selected voltage prior to the application of the initiating signal.
  • a timing circuit as claimed in claim 1 further comprising current transformer means connected to the input circuit to provide an initiating signal proportional to a selected function of the current input to the input circuit and to provide a time lag in the generation of the control signal that is inversely proportional to the selected function of the current.
  • a timing circuit as claimed in claim 1 wherein said amplifier comprises first, second and third transistors connected in a cascade arrangement, .said first and third transistors including at least base and emitter electrodes, the emitter electrodes of said first and third transistors being connected to the same source termials so that the operating voltage difference between the base electrode of the first transistor and the emitter elecetrode of the third transistor is only a single toe voltage.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Relay Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Electronic Switches (AREA)
US544583A 1965-04-23 1966-04-22 Electric timing circuits Expired - Lifetime US3408539A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB17292/65A GB1124492A (en) 1965-04-23 1965-04-23 Improvements relating to electric timing circuits

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US3408539A true US3408539A (en) 1968-10-29

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US544583A Expired - Lifetime US3408539A (en) 1965-04-23 1966-04-22 Electric timing circuits

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US (1) US3408539A (es)
BE (1) BE679955A (es)
CH (1) CH480684A (es)
DE (1) DE1277915B (es)
DK (1) DK116297B (es)
FR (1) FR1477144A (es)
GB (1) GB1124492A (es)
NL (1) NL6605456A (es)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3466506A (en) * 1967-05-03 1969-09-09 Gen Time Corp Pulse generator for periodically energizing a timer solenoid
US3526812A (en) * 1967-04-06 1970-09-01 Gen Electric Power supply for circuit breaker tripping
US3534222A (en) * 1968-11-04 1970-10-13 Collins Radio Co Electronic timer circuit for delayed application of discharge potential
US3711761A (en) * 1970-08-13 1973-01-16 Westinghouse Electric Corp Off delay timer and internally generated auxiliary direct current voltage source for a controlled rectifier alternating current switch for use therein
FR2208173A1 (es) * 1972-11-23 1974-06-21 Matsushita Electric Works Ltd

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2219554B1 (es) * 1973-02-28 1978-03-03 Electricite De France
JPS50145840A (es) * 1974-05-11 1975-11-22
JPS54100248A (en) * 1978-01-25 1979-08-07 Sony Corp Timer circuit
DE3232240A1 (de) * 1982-08-30 1984-03-01 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordnung zum anschalten eines modems an eine fernsprechleitung
GB9222308D0 (en) * 1992-10-23 1992-12-09 Smiths Industries Plc Electrical systems

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3127542A (en) * 1959-06-08 1964-03-31 Mc Graw Edison Co Automatic reclosing breaker system including a repeating circuit interrupter and sectionalizer switches
US3262017A (en) * 1962-11-01 1966-07-19 Allis Chalmers Mfg Co Static overcurrent tripping device
US3317791A (en) * 1965-02-26 1967-05-02 Westinghouse Electric Corp Circuit-controlling systems
US3346797A (en) * 1963-01-21 1967-10-10 Allis Chalmers Mfg Co Static relay control circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2942123A (en) * 1956-01-31 1960-06-21 Westinghouse Electric Corp Time delay control device
DE1057173B (de) * 1956-03-27 1959-05-14 Westinghouse Electric Corp Selbstsperrender Transistorschaltkreis
DE1045456B (de) * 1957-02-01 1958-12-04 Siemens Ag Zeitschaltung zur Erzeugung eines Spannungssprunges, der nach einer definierten Zeitspanne auf einen Schaltvorgang folgt
DE1152145B (de) * 1961-01-04 1963-08-01 Elektro App Werke Berlin Trept Verzoegerungsschaltung, insbesondere fuer Relaisschaltungen
DE1185224B (de) * 1963-10-10 1965-01-14 Telefunken Patent Elektronische Verzoegerungsschaltung

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3127542A (en) * 1959-06-08 1964-03-31 Mc Graw Edison Co Automatic reclosing breaker system including a repeating circuit interrupter and sectionalizer switches
US3262017A (en) * 1962-11-01 1966-07-19 Allis Chalmers Mfg Co Static overcurrent tripping device
US3346797A (en) * 1963-01-21 1967-10-10 Allis Chalmers Mfg Co Static relay control circuit
US3317791A (en) * 1965-02-26 1967-05-02 Westinghouse Electric Corp Circuit-controlling systems

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3526812A (en) * 1967-04-06 1970-09-01 Gen Electric Power supply for circuit breaker tripping
US3466506A (en) * 1967-05-03 1969-09-09 Gen Time Corp Pulse generator for periodically energizing a timer solenoid
US3534222A (en) * 1968-11-04 1970-10-13 Collins Radio Co Electronic timer circuit for delayed application of discharge potential
US3711761A (en) * 1970-08-13 1973-01-16 Westinghouse Electric Corp Off delay timer and internally generated auxiliary direct current voltage source for a controlled rectifier alternating current switch for use therein
FR2208173A1 (es) * 1972-11-23 1974-06-21 Matsushita Electric Works Ltd

Also Published As

Publication number Publication date
DK116297B (da) 1969-12-29
GB1124492A (en) 1968-08-21
BE679955A (es) 1966-10-03
NL6605456A (es) 1966-10-24
CH585166A4 (es) 1969-07-15
DE1277915B (de) 1968-09-19
FR1477144A (fr) 1967-04-14
CH480684A (fr) 1969-12-15

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