US3343147A - Magnetic core switching and selecting circuits - Google Patents

Magnetic core switching and selecting circuits Download PDF

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Publication number
US3343147A
US3343147A US379622A US37962264A US3343147A US 3343147 A US3343147 A US 3343147A US 379622 A US379622 A US 379622A US 37962264 A US37962264 A US 37962264A US 3343147 A US3343147 A US 3343147A
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Prior art keywords
transistor
current
selector
primary
core
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US379622A
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English (en)
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Ashwell John
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Automatic Telephone and Electric Co Ltd
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Automatic Telephone and Electric Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/64—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors having inductive loads
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
    • G11C11/06007—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H03K17/62—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors
    • H03K17/6221—Switching arrangements with several input- output-terminals, e.g. multiplexers, distributors combined with selecting means

Definitions

  • Memories of the coincident current type comprise a matrix of crossing control lines having a magnetic core at each intersection or at a plurality of intersections.
  • Each magnetic core is controlled by a pulse applied to each of two control lines or to at least two of a plurality of control lines at the point of intersection at which the required core is situated, the arrangement being such that the core is energised when coincident pulses are applied to the required point of intersection.
  • the cores are driven between two states of saturation, one saturation state being arbitrarily taken as the 1 state and the other saturation state as the 0 condition.
  • coincident current memory matrices the uniformity of the coincident currents applied to obtain both conditions of saturation is essential. For example in a single plane matrix, should one of the coincident current pulses applied to accomplish saturation be less than the necessary half-switching value, the selected core will not be switched. On the other hand, when one of the coincident current pulses is too great, other than selected cores connected to receive that pulse may be switched.
  • switching circuits shall be available for providing the requisite read-out and Write currents for a magnetic core matrix store and these switching circuits, often called selectors, should moreover have a very short operating time in order that the speed of operation of the store shall not be impaired. It is usual to use transistor circuits for such selectors and in known systems it is usual to operate a current definer circuit and primary and secondary selector circuits for each row and column selection.
  • the use of primary and secondary selectors allows, for example, a total of thirtytwo (i.e. 16 primary and 16 secondary) selectors in a 64 x 64 bit matrix to be used together with sixteen current definer circuits instead of sixty-four selectors and sixty-four current definers for the same size matrix.
  • the first difiiculty encoun- 3,343,147 Patented Sept. 19, 1967 tered is due to the back generated across the core line when a half current pulse is connected to the drive wire. This back may be of the order of 20-25 volts in a large store and, as the emitter electrode of the secondary selector transistor is connected to the core line, non-selected selectors may be erroneously switched.
  • the second difiiculty is experienced with reference to power handling capacities for the transistors employed. In constant current switching systems, the primary selector transistor must remain unsaturated to allow the core line to be driven from a high source impedance. However, transistors having such power handling capabilities are relatively slow acting devices.
  • the third and final difficulty, again with reference to power handling capacity transistors is the fact that substantially large drive requirements must be satisfied for the power transistors making unsuitable the normal logic levels employed in the store control circuitry.
  • the selecting circuits each including a current defining circuit, a primary selector stage connected between the output of the current defining circuit and one end of the drive wire and a secondary selector stage connected to the other end of the drive wire, the transistor in each of said current defining circuits is permanently conductive to a defined state and is operatively associated with a first source of operating potential connected to said transistor when the drive wire is not being selected and is operatively associated with an alternative source of operating potential on the operation of a third selector stage, the alternative source of potential being connected to the current defining circuit over the primary selector stage, the drive wire, the secondary selector stage and the third selector stage and the operation of the selecting circuit is such that when the primary and secondary selector stages are conditioned for operation, the third selector stage upon activation controls the passage of a defined current pulse through the
  • FIG. 1 shows diagrammatically a 64 x 64 magnetic core matrix store and FIG. 2 shows in more detail the selector stages and current defining circiut for one core line CL.
  • each core line is used for reading and writing by reversal of the direction of current flow over the line.
  • a timing select-or stage such as TSl for column core line 1
  • a secondary selector such as WYSI
  • a primary selector such as WYPl
  • a current defining circuit such as TXDI.
  • the writing and reading circuits are separated electrically by the diodes D10, D11, D12 and the circuit shown within the dotted lines in FIG. 2 and referenced TS and the blocks representing the primary and secondary selectors consist of the same circuit with some slight differences which will be explained when describing FIG. 2 in detail.
  • the blocks in FIG. 1 representing the current defining circuits TXD1 to TXD8 all consist of the circiut contained within the dotted rectangle, of the transistor TXD of FIG. 2.
  • the input leads corresponding to lead I]? in FIG. 2 are referenced 1P1, 1P2 and 1P3 for timing selector TSl, secondary selector WYS1 and primary selector WYPl respectively, the other input leads in FIG. 1 being given the general reference IP.
  • the core lines are divided into groups of eight and the method of selecting a core line is such that the primary selectors are each connectedto all the core lines of a particular group while the secondary selectors are each connected to corresponding core lines in all the groups.
  • the write primary selector WYPl as indicated in FIG. 1 is connected to core lines 1 to 8 i.e. to all the core lines of the first group whereas the write secondary selector WYS1 is connected to core lines 1, 9, 17, 25, 33, 41, 49 and 57 i.e. the first core line in each of the eight groups.
  • the read primary selector RYPl is connected to core lines 1 to 8 whereas the read secondary selector RYSl is connectedto core lines 1, 9, 17, 25,,
  • the write and read primary and secondary selectors WYP2, WYS2, RYPZ and RYS2 are similarly connected and so are the write and read primary and secondary selectors WXPl, WXPZ, WXSI, WXSZ, RXPl, RXPZ, RXSl and RXS2 for the row core lines.
  • the references in brackets attached to various leads in FIG.,1 indicate the core lines to which such leads are connected.
  • timing selector stage TS using transitsor TXT
  • the primary and secondary selector stages using transistors TXP and TXS respectively, being the same as the timing selector stage except that resistors R2 and R3 and their associated wander leads L1 and WLZ are omitted.
  • the circuit arrangement employing transistor TXA is a typical output stage for a pulse amplifier which is used to drive the timing selector stage while transistor TXD is employed in the current pulse definer circuit.
  • transistors TXD In the quiescent state of the circuits, i.e. when no magnetic core lines are being selected, all the current defining transistors TXD (TXDl to TXD8, FIG. 1) conduct. These transistors are arranged to pass a standard current defined by the value of emitter resistor RD (FIG. 2) and the stabilised base voltage +VST which is positive with respect to earth. Diode D1 is included to provide a source of current for transistor TXD while the other selector stage transistors are cut off, voltages V3 being more negative than voltage -V1 and both these voltages being negative with respect to earth.
  • the primary and secondary selector stages WYPl and WYS1 are actuated by the leading edge of an input drive pulse on input leads 1P2 and IP3.
  • the transistors TXP and TXS in these selector stages do not conduct sufiiciently to ,provide enough collector current at this time to have any appreciable effect on the magnetic cores threaded by core line CL.
  • the duration of the input drive pulse to the primary and secondary selector stages is defined by the characteristics of the input transformers corresponding to T1 and is arranged to be of greater duration than that which will be generated by transformer T1 of the timing selector.
  • the timing selector stage TS using transistor TXT, is operated by a negative-going edge, which may typically be from volt to 6 volts, applied to the base of transistor TXA, the selector stage drive amplifier output transistor.
  • the input drive edge causes transistorTXA to conduct providing a sharp change in current in the primary winding of transformer T1. The voltage ratio of this trans-.
  • Resistor R7 in the collector of transistor TXA is provided to limit thecollector current to a value within the power rating I of the transistor used in the event of transistor TXA being left conducting due to fault conditions.
  • the current pulse produced in the secondary winding of transformer T1 is passedby resistors R5 and R6 to cause transistor TXT to conduct.
  • Capacitor C2 is provided to decrease the rise time of the leading edge of the current pulse.
  • Two secondary windings are shown the second being connected to another timing selector (not shown) which may be used to drive half the stack of a large capacity magnetic core matrix. The second secondary winding would, of course, not be provided in any of the selector stages.
  • transistors TXS and TXP both pass collector current andin fact, these,,transistors pass the total collector current of the current definer transistor TXD.
  • this current is the closely defined half-current pulse required for coincident current core selection. It will be appreciated at this point that it is desirable that the maxi mum voltage available is used to drive the core line CL. For this reason it is important that the selector stage transistors have as small voltage drop across them as is practical and ideally these transistors should saturate. However, saturation causes a delay in switching off and,
  • an anti-saturation diode such as D4 in the timing selector stage, is included to prevent saturation but limit the voltage drop across the transistors.
  • transistor TXT When the current pulse from the secondary winding of transformer T1 is complete, transistor TXT is cut off thus terminating the current pulse in core line CL. Diode D1 will again provide collector current for transistor TXD. The back built up across the core line CL will cause the collector of transistor TXS ,to become positive with respect to earth. The back E.M.F. is prevented from reaching a value which would damage transistor TXD by means of diode D2. This diode prevents the collector of transistor TXD from becoming more positive than +V2 which is arranged to be within the maximum. in-- verse collector/omitter voltage rating for this transistor.
  • timing selector stage transistor TXT when the timing selector stage transistor TXT is switched on and olf,the momentarily large and rapid voltage changes at the collector of the current definer transistor TXD coupled via bothsecondary windings of the primary input transformer to the undriven primary winding, on a primary selector stage served by the same current definer but not required for the.
  • This unwanted primary selector stage is also associated with the secondary selector stage required, so that two core lines will be selected which obviously cannot be tolerated.
  • resistor R4 shown in the timing selector stage, is provided in both primary and secondary selector stages. This resistor successfully damps out these voltage surges.
  • - Resistor R4 may, in the primary selector stage, he re- From the above description it will be seen that the cur rent definer transistor TXD is permanently conductive and therefore a slow relatively inexpensive transistor may be employed.
  • the selector stages are transformer fed n elaborate voltage changing circuits are required to provide suflicient drive to these stages and therefore they may be incorporated in the logic switching control arrangements provided for a large capacity fact access store employing normal logic voltage levels.
  • Resistors R2 and R3 are provided with their associated shorting wander leads WL1 and WL2 to even-up the differences in rise times experienced with high and low gain transistors. This may alternatively be achieved by the use of a tapped drive transformer. Resistor R1 and capacitor C1, which have been omitted from FIG. 1 in order not to over-complicate the drawings, are provided as a compensation network to reduce overshoot in the current pulse. The actual values will be affected by the amount of stray capacitance experienced in a built-up store.
  • the invention is not limited to the precise method of core line selection described with reference to FIG. 1 but is applicable to any method which employs a primary selector connected to one end of the core line and a secondary selector connected to other end of the core line.
  • n-p-n transistors for the current definer and selector stage transistors and this is intended to be in no way limiting to the invention. It will be obvious to those skilled in the art that p-n-p transistors may be employed with suitable adjustments in voltage levels.
  • a magnetic core storage matrix arranged to operate on the coincident current principle and comprising a plurality of column drive wires, a plurality of row drive wires, a plurality of magnetic cores, one at each of the intersections of the column drive Wires with the row drive wires selecting circuits for selecting one of said column drive wires and one of said row drive wires, each selecting circuit including a transistor current defining circuit, a primary transistor selector stage connected between the output of said current defining circuit and one end of the drive wire associated therewith, a secondary transistor selector stage connected to the other end of said drive wire, a first source of operating potential for maintaining the transistor in said current defining circuit conductive to a defined state when said drive wire is not being selected, means for conditioning said primary transistor and secondary transistor selector stages for operation, a third selector stage, an alternative source of operating potential for the transistor in said current defining circuit, means for operating said third selector stage to connect said alternative source of operating potential to the transistor in said current defining circuit whereby the defined conductive state of the transistor in said

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  • Computer Hardware Design (AREA)
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US379622A 1963-07-27 1964-07-01 Magnetic core switching and selecting circuits Expired - Lifetime US3343147A (en)

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GB29879/63A GB1085955A (en) 1963-07-27 1963-07-27 Improvements in or relating to magnetic core storage matrices

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US3343147A true US3343147A (en) 1967-09-19

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3432835A (en) * 1965-04-30 1969-03-11 Ibm Current summing arrangement for a magnetic core memory
US3440624A (en) * 1964-10-26 1969-04-22 Automatic Telephone & Elect Magnetic core matrix data storage devices
US3445831A (en) * 1965-10-05 1969-05-20 Ibm Drive system for a magnetic core array
US3451048A (en) * 1965-10-05 1969-06-17 Ibm Drive system for a magnetic core array
US3487383A (en) * 1966-02-14 1969-12-30 Burroughs Corp Coincident current destructive read-out magnetic memory system
US3568152A (en) * 1967-11-08 1971-03-02 Control Data Corp Method and apparatus for preconditioning a memory system
US3582911A (en) * 1968-12-04 1971-06-01 Ferroxcube Corp Core memory selection matrix
US3707705A (en) * 1967-12-20 1972-12-26 Jones V Howell Jr Memory module
US3930171A (en) * 1974-07-15 1975-12-30 Ampex Low power, fast rise time current driver for inductive load

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3054905A (en) * 1960-11-21 1962-09-18 Ampex Load-driving circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3054905A (en) * 1960-11-21 1962-09-18 Ampex Load-driving circuit

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3440624A (en) * 1964-10-26 1969-04-22 Automatic Telephone & Elect Magnetic core matrix data storage devices
US3432835A (en) * 1965-04-30 1969-03-11 Ibm Current summing arrangement for a magnetic core memory
US3445831A (en) * 1965-10-05 1969-05-20 Ibm Drive system for a magnetic core array
US3451048A (en) * 1965-10-05 1969-06-17 Ibm Drive system for a magnetic core array
US3487383A (en) * 1966-02-14 1969-12-30 Burroughs Corp Coincident current destructive read-out magnetic memory system
US3568152A (en) * 1967-11-08 1971-03-02 Control Data Corp Method and apparatus for preconditioning a memory system
US3707705A (en) * 1967-12-20 1972-12-26 Jones V Howell Jr Memory module
US3582911A (en) * 1968-12-04 1971-06-01 Ferroxcube Corp Core memory selection matrix
US3930171A (en) * 1974-07-15 1975-12-30 Ampex Low power, fast rise time current driver for inductive load

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Publication number Publication date
NL6408319A (fr) 1964-10-26
DE1449705B2 (de) 1972-12-28
DE1449705A1 (de) 1968-12-19
GB1085955A (en) 1967-10-04
FR1420400A (fr) 1965-12-10

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