US3305411A - Method of making a transistor using semiconductive wafer with core portion of different conductivity - Google Patents

Method of making a transistor using semiconductive wafer with core portion of different conductivity Download PDF

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US3305411A
US3305411A US239310A US23931062A US3305411A US 3305411 A US3305411 A US 3305411A US 239310 A US239310 A US 239310A US 23931062 A US23931062 A US 23931062A US 3305411 A US3305411 A US 3305411A
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opposite
shaped
conductivity type
rod
layer
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Jochems Pieter Johan Wilhelmus
Tummers Leonard Johan
Werdt Reinier De
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US Philips Corp
North American Philips Co Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/228—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a liquid phase, e.g. alloy diffusion processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors

Definitions

  • the invention relates to a transistor comprising a wafershaped semi-conductor body having opposite emitter and collector regions of one conductivity type and a base reg on of the opposite conductivity type consisting of an act1ve layer interposed between the emitter region and the collector region and produced by a local activating treatment, for example a diffusion treatment, of the emitter side of the wafer-shaped semi-conductor body, and of a portion surrounding and radially adjoining this layer for contact purposes, and to a method of manufacturing such a transistor.
  • a local activating treatment for example a diffusion treatment
  • active layer of the base region is used herein to signify in the usual manner the part of the base region substantially interposed between the emitter and collector regions and traversed by charge carriers which are emitted by the emitter region and collected by the collector region.
  • a layer obtained by activating treatment of a surface of the semi-conductor body is used herein to signify a layer obtained by epitaxial growing to this surface or, as mentioned hereinbefore, a layer obtained by diffusion into the said surface.
  • an epitaxially grown layer is used herein to signify in the usual manner a layer obtained by deposition of semi-conductor material from the vapour phase of this material or by decomposition from a compound in the vapour state containing the semi-conductor material, impurities being also deposited or diffused into the previously obtained layer.
  • One of the advantages of a diffused active base layer and of an epitaxial grown active base layer is that during manufacturing the thickness of such layers may be controlled easily. Especially when the thickness of the active layer must be small, for instance, a few microns for high frequency purposes, the said control of the thickness is important, which control improves the devices characteristics and its reproduction.
  • An important method of making a diffused active base layer is the alloy-diffusion method, which is described in detail in the copending ap plication, Serial No. 676,563, filed August 6, 1957.
  • the known transistors including an active layer of the base region of the said kind have a portion of the base region intended for the provision of contacts and having a thickness which, although it frequently exceeds the thickness of the active layer, still is of the same order of magnitude as that of the active layer, while in view of the use of the transistor at high frequencies this active layer is particularly thin (the thickness being, for example, a few microns).
  • the base connection contact is provided on the still thin part of the base region intended for contacting purposes.
  • Such transistors cannot readily be manufactured because the provision of the base connecting contact on so thin a layer provides difliculty. Furthermore such transistors still have a considerable base resistance due to the slight thickness of the part of the base region intended for contacting purposes.
  • the base resistance may be restricted by providing the base connecting con-tact near the active layer of the base region and hence near the emitter region.
  • provision of the base con-, tact and the emitter contact (emitter region) in close proximity to one another provides technological difficulty and in addition during their-provision they are liable to influence one another.
  • a transistor of the kind mentioned in the preamble is characterized in that the part of the base region intended for contacting purposes extends over the entire thickness of the wafer-shaped semi-conductor body from the edge of the wafer-shaped semiconductor body substantially up to the active layer of the base region, a distance preferably exceeding the thickness of the wafer-shaped semiconductor body, a base connecting contact being provided on the said part.
  • An important embodiment of the transistor in accordance with the invention is characterized in that between the diffused active layer of the base region and the collector region a further layer is provided having the same conductivity type as the base zone and a specific resistivity at least equal to that of the part of the diffused active layer adjoining the said further layer and at most equal to the intrinsic specific resistivity, whereas the part of the base region intended for contacting purposes has a specific resistivity lower than that of the said further layer.
  • the transistor in accordance with the invention has a low collector capacitance so that in operation in a circuit arrangement less trouble is encountered resulting from feedback.
  • a .layer of the same conductivity type as a previously mentioned layer and having a larger specific resistivity includes an intrinsic layer.
  • the invention further provides a surprisingly simple method of manufacturing a transistor in accordance with the invention.
  • this method is characterized in that it starts from a wafer-shaped semiconductor body including a rod'shaped portion extending transversely through the body and a portion surrounding the said rod-shaped portion, the concentration of charge carriers of the type which in the surrounding portion form the majority charge carriers being smaller in the rodsha-ped portion than in the surrounding portion, after which the active layer of the base region, which layer adjoins the surrounding portion and is of the same conductivity type as this portion, is obtained by an activating treatment, for example a diffusion treatment, of an end face of the rod-shaped portion, the emitter zone being provided on the active layer.
  • an activating treatment for example a diffusion treatment
  • An important embodiment of the method in accordance with the invention is characterized in that one starts from a wafer-shaped semi-conductor body in which the said rod-shaped portion and the surrounding portion are of opposite conductivity types while at the end-face of the rod-shaped portion situated opposite the end face at which the active layer is formed a collector connecting contact is provided.
  • another particularly important embodiment of the method of manufacturing a transistor in accordance with the invention of the kind mentioned hereinbefore having a further layer interposed between the active base layer and the collector region is characterized in that one starts from a wafer-shaped semiconductor body in which the said rod-shaped portion and the surrounding portion are of the same conductivity type, the specific resistivity of the rod-shaped portion exceeding that of the surrounding portion and at most being equal to the intrinsic specific resistivity, while at the end face of the rod-shaped portion situated opposite the end face at which the active layer of the base region is formed a collector region is provided.
  • This collector region may be obtained by a known alloying process.
  • the manufacture of such a complicated transistor structure is particularly simplified by starting in accordance with the invention from a wafer-shaped semi-conductor body including a rod-shaped portion having the same specific resistivity as is desired for the further layer.
  • the wafer-shaped semiconductor body including a rod-shaped portion and a surrounding portion is manufactured by manufacturing a wafer-shaped semi-conductor body provided with masking layers on opposed major surfaces thereof, after which impurities of a particular conductivity type are diffused into the body throughout its entire surface area until only a rod-shaped portion of this body situated between the masking layers still has the initial concentration of impurities, after which the masking layers and, as the case may be, surrounding surface layers of the semi-conductor body are removed so that the portion having the initial concentration is exposed at the surface on both sides of the body.
  • the masking layers may simply be opposite raised parts of the semi-conductor body.
  • the said raised parts are recrystallized semiconductor layers.
  • Rod-shaped portions having proportions determined with a higher degree of accuracy and a greater reproducibility are obtained by using masking layers of silica.
  • FIGURES 1 and 2 are cross-sectional views of two different embodiments of transistors in accordance with the invention.
  • FIGURES 3, 4, 5 and 6 are cross-sectional views of successive intermediate stages of a method in accordance with the invention of manufacturing a transistor in accordance with the invention; while FIGURE 7 shows an intermediate stage of a semiconductor body during another embodiment of the method in accordance with the invention.
  • FIGURE 1 is a diagrammatic cross-sectional view of an embodiment of a transistor in accordance with the invention including a diffused active layer of the base region.
  • the transistor comprises a wafer-shaped semiconductor body 8 having an emitter region 1 of, for example, p-type conducitvity provided with an emitter contact 5 and a connecting lead 12, and a collective region 2 of the same conductivity type provided with a collector contact 6 and a connecting lead 14.
  • the base region which has a conductivity type opposite to that of the emitter and collector regions, that is to say, n-type conductivity in this example, comprises a thin diffused active layer 3 and a portion 4 for contacting purposes which surrounds this active layer and radially adjoins it.
  • the portion 4 intended for contacting purposes extends over the entire thickness (see the arrow 21) of the wafershaped semi-conductor body 8 from the edge of the wafer-shaped semi-conductor body 8 substantially up to the active layer 3 (see the arrow Consequently, the base resistance is low.
  • the distance indicated by the arrow 20 preferably exceeds the thickness indicated by the arrow 21.
  • a base connecting contact 9, which may be an annular contact soldered to the wafer-shaped semiconductor body 8, is spaced by a comparatively large distance from the emitter contact 5 and the emitter region 1 while retaining a low base resistance.
  • the base and emitter connecting contacts are substantially prevented from influencing one another during their provision while the large thickness of the portion 4 intended for contacting purposes facilitates the provision of a base connecting contact.
  • the portion intended for contacting purposes is too thin and frequently its area is too small to be connected to a contact which also serves as a support for the semiconductor body.
  • the collector contact also serves as support for the semi-conductor body.
  • the-portion 4 of the base region intended for contacting purposes is very suitable for connection to a contact which also serves as support.
  • This contact may be a metal plate 29 which is provided with an aperture 36 (FIGURE 2) and along this aperture is connected to the semi-conductor body 8, for example, by soldering in a manner as shown in FIGURE 2.
  • a transistor in accordance with the invention as shown in FIGURE 2 includes a further layer 7 interposed between the diffused active layer 3 and the collector region 11.
  • This layer 7 is of the same conductivity type as the layer 3 and has a specific resistivity at least equal to that of the portion of the layer 3 adjoining the layer 7 and at most equal to the intrinsic specific resistivity.
  • the term intrinsic specific resistivity is used herein to signify in the usual manner the specific resistivity in a semi-conduct-or in which the concentrations of both types of charge carriers are equal. Due to this layer 7 the collector capacitance is small so that when the transistor is used in an electric circuit arrangement less trouble is encountered from feedback.
  • a wafer-shaped semi-conductor body provided with masking layers on opposite surfaces is manufactured.
  • this body By subjecting this body to a diffusion treatment throughout its surface area the concentration of impurities in the body with the exception of a rod-shaped part situated between the masking layers is altered.
  • the masking layers are then removed so that the said rod-shaped part is exposed at the surface on both sides.
  • a transistor as shown in FIGURE 1 one may start from a wafer-shaped semi-conductor body, for example, of p-type germanium having a thickness of 220 microns and a specific resistivity of about 1 ohm-cm. From both sides of the water a surface layer 31 of thick-- ness about 60 microns is removed except at two areas: situated opposite one another on either side of the wafer (FIGURE 3). This may be effected by grinding, selective etching or ultrasonic boring. The wafer then has a crosssectional area as shown by shading in FIGURE 3 with opposite raised parts 32. These raised parts 32 serve as masking layers.
  • the diameter of the plate may be about 1 mm, its thickness 100 microns, the height of the opposed raised parts 60 microns and the diameter of these raised parts 180 microns.
  • the raised parts 32 may be masking recrystallized semiconductor layers. These layers may be obtained by alloying a material consisting of germanium and at least one metal to the wafer-shaped germanium body and subsequently cooling. The proportion of germanium in the alloy material must be such that substantially no material of the semi-conductor body is dissolved in the alloyed material while on cooling a sufficiently thick recrystallized germanium layer is obtained. On this recrystallized layer is disposed the metal of the alloy which subsequently is removed. A slight amount of the metal of the alloy is also crystallized out in the recrystallized layer.
  • the said alloy preferably contains no rapidly diffusing active impurities.
  • the alloy may contain one or several of the metals indium, aluminum, gallium, lead and tin.
  • a pellet having a diameter of 18 microns and consisting of indium containing 60 atomic percent of germanium may be alloyed to the semi-conductor body in a hydrogen atmos phere at a temperature of 820 C.
  • Cooling to room temperature is then effected in about half an hour.
  • a recrystallized germanium layer (in the form of a raised part 32) having a thickness of about 60 microns and a diameter of about 180 microns is then produced.
  • a small amount of indium is disposed on this layer. This indium is removed by etching with a solution of HCl in water.
  • n-Type impurities for example antimony are then diffused into the entire surface area of the water provided with raised parts 32, for example, to a depth of about 55 microns.
  • the resulting configuration is shown in FIG- URE 4.
  • the broken lines indicate the diffusion boundaries. Only a rod-shaped portion 41 of the plate situated between the raised parts 32 still is of p-type conductivity while the remainder 4.2 of the wafer has become n-type.
  • the diffusion of antimony may be effected in a furnace which may consist of quartz and in which a hydrogen atmosphere is maintained containing antimony vapour.
  • the diffusion is performed at 820 C. for about 18 hours.
  • the surface concentration of antimony atoms is from about 10 -10 atoms per cc.
  • the raised parts 32 and if necessary surrounding surface layers are then removed so that the configuration shown in FIGURE 5 is obtained.
  • the raised parts may simply be removed by grinding.
  • the resulting configuration comprises a rodshaped portion 51 of p-type conductivity and a portion 52 of n-type conductivity surrounding the rod-shaped portion.
  • the wafer is etched electrolytically, for example, in an aqueous 40% solution of KOH.
  • a conductor is secured at one side of the wafer to an end face of the rod-shaped portion 51 with the aid of silver paste after which this side of the wafer and the conductor are coated with an insulating lacquer.
  • the other side of the wafer is etched in the etching bat-h.
  • a voltage is applied between the said conductor and a platinum electrode arranged in the bath a voltage causing a current of, for example, a few ma. Etching is performed for about 10 seconds.
  • the p-type rodshaped portion 51 is etched at a higher rate than the surrounding n-type portion 52 so that at the area of the rodshaped portion 51 a recess is produced in the surface of the wafer.
  • the other side of the wafer is etched in the same manner.
  • the lacquer and the silver paste may be removed by dissolving in acetone.
  • the resulting configuration is shown in FIGURE 6, the recesses 53 marking the position of the rod-shaped portion 51. After the etching process the wafer is washed in deionized Water and then dried.
  • a wafer-shaped semi-conductor body for example, of germanium, is not pro-vided with the above-described raised parts but with masking layers of silica.
  • a masking silica layer may be readily obtained by deposition from the vapour phase, for example, with the use of a separate masking plate provided with at least one aperture.
  • the masking plate may be a molybdenum plate of thickness about microns having a circular aperture made, for example, by drilling and having a diameter of about microns.
  • the masking plate is arranged on the semi-conductor body and the assembly is arranged in a device for deposition from the vapour phase in which a vacuum is maintained.
  • the device also contains an amount of solid silica which is heated to a temperature of about 1000 C. While the temperature of the semi-conductor body is raised to about 300 C. The spacing between the solid silica and the semi-conductor body is about 10 cms. The silica vaporizes and is deposited on the molybdenum plate and, through the aperture, on the semi-conductor body. The process is continued until a silica layer having a thickness of approximately from /2 to 1 micron is produced on the semi-conductor body.
  • the body is subjected to a diffusion treatment throughout its entire surface area in the manner described in the preceding example and subsequently the silica layers are removed by etching with hydrofluoric acid.
  • the resulting configuration is shown in FIGURE 5.
  • etching in a manner as described in the preceding example a configuration as shown in FIGURE 6 is obtained.
  • masking silica layers are provided on a wafer-shaped semi-conductor body with a high degree of accuracy by a photographic process.
  • the semi-conductor body may be entirely coated with a layer of silica and subsequently the layer may locally be removed with the aid of a photographic process.
  • the semi-conductor body is preferably first coated with a photo-hardening lacquer.
  • photo-hardening lacquer is used herein to signify in the usual manner a lacquer which is also referred to as photo-resist and is soluble in a suitable developing liquid before irradiation but not after irradiation. (The irradiation need not necessarily be effected with visible light.) Such lacquers together with associated developing liquid are commercially available.
  • the lacquer After the lacquer has been deposited on the semi-conductor body it is exposed with the exception of the areas at which the masking layers are to be provided and subsequently the unexposed portions of the lacquer are removed with the aid of a developing liquid. Subsequently a silica layer is deposited from the vapour phase in the manner described hereinbefore. This layer adheres satisfactorily to the semi-conductor body at the areas from which the photo-hardening lacquer has been removed, but is readily removed by brushing from the other areas together with the residual photo-hardening lacquer. As has been described hereinbefore, the configuration shown in FIGURE 6 may then be obtained by subjecting the assembly to diffusion throughout its surface area, removing the masking oxide layer and etching. However, to obtain accurately defined recesses 53 the latter are preferably produced by electrolytic etching after the development of the photo-hardening lacquer and before the provision of the oxide layer.
  • the electrolytic etching process may be performed by cementing a glass tube, for example, with nitrocellulose lacquer to a surface of the semi-conductor body so that the tube is closed at one end by the semi-conductor body.
  • the tube is filled, for example, with mercury into whlch an electric connecting lead is inserted.
  • the mercury is in contact with the semi-conductor body at the areas at which the photo-hardening lacquer has been removed.
  • the semiconductor body is immersed in an etching bath so that the tube projects above the etching liquid.
  • the etching liquid may be an aqueous 40% solution of KOH.
  • Between the said connecting lead and a further electrode arranged in the etching bath a voltage is applied so that a current of atfew ma. starts to flow.
  • the surface of the semi-conductor body opposite the tube is etched at the areas from which the photo-hardening lacquer has been removed so that recesses are produced. Etching is performed for about 10 seconds.
  • recesses 53 are not essential to the invention but by providing these recesse 53 one has an easy method to indicate the location of the rodshaped region 51.
  • the body is subjected to a diffusion treatment throughout its surface area and the oxide layers are again removed so that the configuration shown in FIG- URE 6 is obtained.
  • the body having a configuration as shown in FIGURE 6 is then provided with the active layer of the base region.
  • This layer, the emitter region and the emitter contact may simply be obtained by alloying a pellet having a diameter of about 60 microns consisting, for example, of lead containing 2% by weight of antimony and 0.5% by weight of gallium to an end face 54 of the rod-shaped part 51 in a recess 53 (FIGURE 6) at a temperature of about 780 C. in a hydrogen atmosphere for about 10 minutes.
  • an active n-type layer 3 (FIGURE 1) of thickness a few microns is produced and by predominant segregation of the gallium a p-type recrystallized emitter region 1 is produced on which a solidified amount of electrode material 5 is disposed.
  • a collector contact 6 is provided on the side opposite the emitter region 1 and the active layer 3, for example, by alloying a pellet having a diametter of 60 and consisting of indium containing /2% by weight of gallium to the semi-conductor body at a temperature of about 550 C. in a hydrogen atmosphere for about 5 minutes.
  • the resulting assembly may be etched in a usual manner and this may be repeated after the provision of the collector contact 6.
  • connection leads 12 and 14 which may be nickel wires, may be provided in a usual manner while the base connecting contact, which may consist of a nickel wire 9 or of an apertured nickel plate 29 (FIGURE 3), may be joined to the portion 4 intended for contacting purposes by soldering, for example, with a lead tin solder to which antimony has been added.
  • the transistor described with reference to FIGURE 2 in which the layer 7 is of the same conductivity type as the base region comprising the portions 3 and 4 or, as the case may be, is intrinsic, may be manufactured substantially in the same manner as described herein'befo-re with respect to a transistor of the kind shown in FIGURE 1.
  • the whole difference consists in that one does not start from a wafer-shaped body of p-type conductivity but from a body of n-type conductivity having a specific resistivity exceeding, for example, 10 ohm cm. or even from an intrinsic body.
  • the collector contact 6 (FIGURE 1) may be provided after a large part of the layer 2 has been removed by etching so that the spacing between the collector contact 6 and the layer 3 is decreased and the collector series resistance is reduced.
  • the active layer 3 of the base region (FIGURES l and 2) may be separately obtained by diffusion or epitaxial growth from the vapour phase and subsequently the emitter contact may be alloyed to the diffused layer in a separate operation.
  • the semi-conductor body which is subjected to diffusion throughout its entire surface area may be shaped in the form shown in cross-section by FIGURE 7.
  • the semi-conductor body is wafer-shaped and provided with annular opposite grooves 65 and with raised parts 32.
  • the grooves are readily obtainable by ultrasonic boring. After diffusion and removal of the marginal parts A a body is obtained as shown in FIGURE 4.
  • This method is highly suitable for mass manufacture because in a large sheet of semi-conductor material many pairs of opposite annular grooves may be provided and subsequently by subdivision of the sheet and diffusion many bodies of the kind shown in FIGURE 4 may be obtained.
  • a sheet of semi-conductor material may be provided with a number of pairs of opposite masking layers consisting of silica, enabling a plurality of transistors to be made from a sheet of semiconductor material.
  • wafer-shaped semiconductor bodies including a rod shaped portion and a surrounding portion may be obtained by subjecting a rod of semi-conductor material to diffusion throughout its entire surface area until only the core of the rod still has the initial concentration of impurities, after which the rod is cut into wafers, or by subjecting a rod of semi-conductor material to a floating zone treatment in which by the use of annular molten zones only the core of the rod retains the initial composition, after which the rod is cut into wafers.
  • Semi-conductor materials other than germanium, for example, silicon and A B compounds, may be used, as may impurities and electrode materials other than the above mentioned ones.
  • a method of making a transistor comprising the steps of providing a wafer-shaped semiconductive body of one conductivity type with opposed major surfaces, proy1d1ng opposite one another on the major surfaces maskmg layers capable of inhibiting the diffusion of active impurities into a body portion located between the masking layers, thereafter diffusing into the entire body except for the body portion protected by the masking layers active impurities forming the opposite conductivity type seml-conductor to convert the entire wafer except for a generally rod-shaped interior portion surrounded thereby to the opposite conductivity type material having a conductivity value substantially greater than that of the rodshaped interior portion, the concentration of charge carriers 1n the surrounding body portions of opposite conductivity type of the type which form therein the majority charge carriers being greater than the concentration of said charge carriers in the interior rod-shaped portion, epitaxially depositing a layer on the rod-shaped portion and providing therewithin active impurities forming the said opposite conductivity type semiconductor to convert a surface portion thereof to the said opposite type conductivity connected to the surrounding body portions to produce a base
  • a method of making a transistor comprising the steps of providing a wafer-shaped semiconductive body of one conductivity type with opposed major surfaces, providing opposite one another on the major surfaces masking layers capable of inhibiting the diffusion of active impurities into a body portion located between the masking layers, thereafter diffusing into the entire body except for the body portion protected by the masking layers active impurities forming the opposite conductivity type semiconductor to convert the entire Wafer except for a generally rod-shaped interior portion surrounded thereby to the opposite conductivity type material having a conductivity value substantially greater than that of the rodshaped interior portion, the concentration of charge carriers in the surrounding body portions of opposite conductivity type of the type which form therein the majority charge carriers being greater than the concentration of said charge carriers in the interior rod-shaped portion, thereafter exposing opposite surface portions of the rodshaped interior portion by removing intervening materials, diffusing into an exposed surface portion of the rod-shaped portion active impurities forming the said opposite conductivity type semiconductor to convert a surface portion thereof to the opposite type conductivity connected to the converted surrounding body portions to produce a base region
  • masking layers comprise raised portions of the semiconductive body integral with the remainder of the body, said raised portions being removed to expose the rod-shaped interior portion.
  • the raised portions are formed by alloying an alloy mass containing at least one metal and the material of the semiconductive body to opposed portions of the semiconductive body to form recrystallized regions underneath the mass, and then removing the mass leaving the recrystallized regions.

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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US239310A 1961-11-30 1962-11-21 Method of making a transistor using semiconductive wafer with core portion of different conductivity Expired - Lifetime US3305411A (en)

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AT (1) AT238258B (de)
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NL (1) NL272046A (de)

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB765190A (en) * 1954-06-11 1957-01-02 Standard Telephones Cables Ltd Improvements in or relating to the treatment of electric semi-conducting materials
US2796562A (en) * 1952-06-02 1957-06-18 Rca Corp Semiconductive device and method of fabricating same
US2802760A (en) * 1955-12-02 1957-08-13 Bell Telephone Labor Inc Oxidation of semiconductive surfaces for controlled diffusion
US2840497A (en) * 1954-10-29 1958-06-24 Westinghouse Electric Corp Junction transistors and processes for producing them
US2840494A (en) * 1952-12-31 1958-06-24 Henry W Parker Manufacture of transistors
US2940023A (en) * 1957-03-22 1960-06-07 Int Standard Electric Corp Transistor
US2941131A (en) * 1955-05-13 1960-06-14 Philco Corp Semiconductive apparatus
US2947923A (en) * 1955-11-03 1960-08-02 Motorola Inc Transistor process and product
US2952824A (en) * 1958-06-18 1960-09-13 Bell Telephone Labor Inc Silicon alloy diode
US2975342A (en) * 1957-08-16 1961-03-14 Research Corp Narrow base planar junction punch-thru diode
US2975080A (en) * 1958-12-24 1961-03-14 Rca Corp Production of controlled p-n junctions
US3089793A (en) * 1959-04-15 1963-05-14 Rca Corp Semiconductor devices and methods of making them
US3108914A (en) * 1959-06-30 1963-10-29 Fairchild Camera Instr Co Transistor manufacturing process
US3164498A (en) * 1961-04-10 1965-01-05 Philips Corp Method of manufacturing transistors
US3164500A (en) * 1960-05-10 1965-01-05 Siemens Ag Method of producing an electronic semiconductor device

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2796562A (en) * 1952-06-02 1957-06-18 Rca Corp Semiconductive device and method of fabricating same
US2840494A (en) * 1952-12-31 1958-06-24 Henry W Parker Manufacture of transistors
GB765190A (en) * 1954-06-11 1957-01-02 Standard Telephones Cables Ltd Improvements in or relating to the treatment of electric semi-conducting materials
US2840497A (en) * 1954-10-29 1958-06-24 Westinghouse Electric Corp Junction transistors and processes for producing them
US2941131A (en) * 1955-05-13 1960-06-14 Philco Corp Semiconductive apparatus
US2947923A (en) * 1955-11-03 1960-08-02 Motorola Inc Transistor process and product
US2802760A (en) * 1955-12-02 1957-08-13 Bell Telephone Labor Inc Oxidation of semiconductive surfaces for controlled diffusion
US2940023A (en) * 1957-03-22 1960-06-07 Int Standard Electric Corp Transistor
US2975342A (en) * 1957-08-16 1961-03-14 Research Corp Narrow base planar junction punch-thru diode
US2952824A (en) * 1958-06-18 1960-09-13 Bell Telephone Labor Inc Silicon alloy diode
US2975080A (en) * 1958-12-24 1961-03-14 Rca Corp Production of controlled p-n junctions
US3089793A (en) * 1959-04-15 1963-05-14 Rca Corp Semiconductor devices and methods of making them
US3108914A (en) * 1959-06-30 1963-10-29 Fairchild Camera Instr Co Transistor manufacturing process
US3164500A (en) * 1960-05-10 1965-01-05 Siemens Ag Method of producing an electronic semiconductor device
US3164498A (en) * 1961-04-10 1965-01-05 Philips Corp Method of manufacturing transistors

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BE625431A (de)
ES282889A1 (es) 1963-05-01
NL272046A (de)
GB1031157A (en) 1966-05-25
AT238258B (de) 1965-02-10

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