US3293634A - Binary-to-decimal decoding matrix using static switches - Google Patents

Binary-to-decimal decoding matrix using static switches Download PDF

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Publication number
US3293634A
US3293634A US264472A US26447263A US3293634A US 3293634 A US3293634 A US 3293634A US 264472 A US264472 A US 264472A US 26447263 A US26447263 A US 26447263A US 3293634 A US3293634 A US 3293634A
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matrix
binary
magnetic
cores
terminal
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US264472A
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English (en)
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Teitel Teodor
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INSTITUTE OF ATOMIC PHYSICS
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INSTITUTE OF ATOMIC PHYSICS
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/80—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using non-linear magnetic devices; using non-linear dielectric devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/08—Output circuits

Definitions

  • the invention relates to a matrix composed of saturable reactors of a special design as static switching elements, enabling conversion from the one out of ten binary to the one out of ten counting system, the said matrix being adaptable to transistorized decimal-coded binary scaling circuits, enabling the direct driving of incandescent lamp projection read-out elements or of in-line display tubes (Nixie).
  • Decoding circuits using electromechanical relays are known, the said relays being driven by the collector current of transistors in the flip-flop stages, the display tubes being selectively switched through the combination of the changeover contacts of said relays.
  • This system has the disadvantage of possessing moving elements, and, due to the existence of mechanical contacts, its reliability is low.
  • circuits comprising a plurality of groups of magnetic modulators, having an alternating-current winding and a direct current winding for controlling the saturation of the core, the alternating-current winding of said modulators in each subgroup of magnetic modulators being series connected and having the center and outside ends of said series connection connected to receive a current from a subgroup of a previous group of the cascade connection.
  • the disadvantage of this matrix consists in the fact that, for reason of avoiding the coupling between the alternating-current winding and the directcurrent winding, two modulators of the same subgroup are series-opposing connected. Due to the fact that the ratio of the number of turns of the direct-current winding 3,293,634 Patented Dec.
  • the binary-to-decimal decoding matrix using static switches has none of these disadvantages, due to the fact that, in order to avoid inductive couplings between the alternating current circuit and the direct current windings, its switching elements consist of two toroidal-shaped magnetic cores, the two said magnetic cores being laid tangentially in the same plane, each core having a load winding with few turns, the said load windings being series-opposing connected, and a common direct-current winding for controlling the saturation of said cores, all switching elements being identical and being connected in said matrix to provide a low impedance path for the alternating current between an input terminal and one the ten output terminals corresponding to the decimal figure indicated by the collector currents of the transistors in the flip-flop stages of the scaling unit.
  • the binary-to-decimal decoding matrix using static switches consists of eighteen identical switching elements, each of said switching elements having two toroidal magnetic cores, each core being made out of ferrite, thus allowing the use of a high frequency supply voltage.
  • the two said'cores of each switching element are situated tangentially, in the same plane, each having a few turns load winding a, the said windings being series opposing connected and charged by the load current.
  • Through the holes of the two, toroidal-shaped, cores is a common winding b with many turns, allowing the two said cores of each switching element to be saturated when a direct current circulates through this winding.
  • the switching element may act as a relay closing the circuit for an alternating current if the cores are saturated, or exhibiting a high impedance in the alternating-current circuit, when the cores are not brought into saturation.
  • the load windings of these magnetic switching elements are cascade-connected in the matrix, according to the wiring diagram, enabling a connection to be established between the high-frequency generator terminal, and one of the ten read-out lamps 0 used to display the figures 0 9.
  • the direct-current windings of the eighteen magnetic switching elements are series-connected in the collector circuits of the transistors in the scaling unit, thus enabling the different steady-states of the flip-flop stages in said scaling unit to determine the saturation of cores of said switching elements which are connected in the collectors of the current-conducting transistors.
  • connection of the magnetic switching elements in the matrix according to the invention enables the display for a l2-4-8 as well as for a l24-2 scaling unit.
  • the binary number 0000 makes an alternating current flow through display unit 0, since all transistors on ways T, E, 1, g are condcting, thus providing a low impedance path between high-frequency generator G and display lamp 0, while binary number 1110 provides a load current on way 7, since only on this way have all switching elements their cores saturated (conducting are in this case transistors 1, 2, 4, 8).
  • the invention Compared to existing methods for displaying the indication of transistorized. scaling units, the invention has following advantageous features:
  • the low electric power required to bring the magnetic cores into saturation enables the decoding matrix to be driven directly by the transistorized scaling unit, without the use of intermediate amplifier elements;
  • toroidal-shaped magnetic cores and a common direct-current winding for controlling the saturation of a pair of cores, leads to a satisfactory switching characteristic, even if ferrite cores are used;
  • ferrite magnetic cores permits the use of a high frequency supply for the load circuit, enabling a considerable reduction in size for the whole matrix
  • the eighteen magnetic switching elements composing the matrix are identical and can easily be standardized as independent components that can be wired on a single printed board.
  • a magnetic matrix decoder for connecting an input terminal selectively to one of ten output terminals to provide an output decimal system numerical indication of a multiple bit binary input, said matrix comprising, in combination, a plurality of magnetic switching elements arranged electrically at selected intersections of columns and rows, with the columns corresponding to respective binary input bits and the rows corresponding to respective numerical digits in the decimal system; each element comprising a pair of annular cores of magnetic material arranged in substantially coplanar juxtaposed relation; a load winding on each core, the load windings on the cores of each pair having the same number of turns and being connected in series opposite; a source of AC.
  • a matrix input terminal connected to one terminal of said source; a plurality of matrix output terminals each corresponding to a receptive one of said rows; a plurality of digit indicators each connected between a respective output terminal and the other terminal of said source, each digit indicator corresponding to a respective binary code input; said load windings being connected in cascade between said input terminal and said output terminals; the number and column position of the said elements connected to a respective output terminal corresponding to the binary code representation of the digit of the associated indicators; a plurality of control windings equal in number to said elements, each control winding being common to both cores of a respective element and those control windings arranged along a respective column being connected in series; and means for selectively applying a DC.
  • a magnetic switching element comprising a pair of annular cores of magnetic material arranged in substantially coplanar juxtaposed relation; a load winding on each core, the load windings having the same number of turns and being connected in series opposition; means operable to impress an AC. potential across said series connected load windings; a control winding common to both of said cores; and means operable to selectively apply a DC. potential across said control winding to saturate said cores to provide a low impedance A.C, path through said load windings.
  • a magnetic matrix decoder as claimed in claim 1, in which said source of AC. potential is a high frequency source.
  • a magnetic matrix decoder as claimed in claim 1, in which said columns are arranged in pairs; said means for selectively applying said DC. potential comprising flip-flop transistor stages each controlling a pair of columns.
  • a magnetic matrix decoder as claimed in claim 4, in which there are eighteen of said elements and four pairs of columns, a first pair of columns having the binary representations 1 and I, a second pair of columns having the binary representations 2 and 1 a third pair of columns having the binary representations 4 and I and a fourth pair of columns having the binary representations 8 and each of said digit indicators being associated with a respective row, and said digit indicators having indications from 0 to References Cited by the Examiner UNITED STATES PATENTS 3,086,198 4/1963 Tate 340347 MAYNARD R. WILBUR, Primary Examiner.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Baking, Grill, Roasting (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Electrotherapy Devices (AREA)
  • Control Of El Displays (AREA)
  • Ignition Installations For Internal Combustion Engines (AREA)
US264472A 1962-03-05 1963-03-04 Binary-to-decimal decoding matrix using static switches Expired - Lifetime US3293634A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
RO4520162 1962-03-05
RO4592162 1962-12-20

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US3293634A true US3293634A (en) 1966-12-20

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US (1) US3293634A (US07714131-20100511-C00024.png)
BE (2) BE641605A (US07714131-20100511-C00024.png)
CH (1) CH406304A (US07714131-20100511-C00024.png)
DE (2) DE1210914B (US07714131-20100511-C00024.png)
GB (2) GB955329A (US07714131-20100511-C00024.png)
NL (2) NL302354A (US07714131-20100511-C00024.png)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3766372A (en) * 1970-05-18 1973-10-16 Agency Ind Science Techn Method of controlling high electric field domain in bulk semiconductor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3086198A (en) * 1958-07-24 1963-04-16 Ibm Core code translator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3086198A (en) * 1958-07-24 1963-04-16 Ibm Core code translator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3766372A (en) * 1970-05-18 1973-10-16 Agency Ind Science Techn Method of controlling high electric field domain in bulk semiconductor

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Publication number Publication date
BE641605A (US07714131-20100511-C00024.png) 1964-06-22
GB992784A (en) 1965-05-19
BE629020A (US07714131-20100511-C00024.png)
DE1221279B (de) 1966-07-21
CH406304A (de) 1966-01-31
NL302354A (US07714131-20100511-C00024.png)
NL289718A (US07714131-20100511-C00024.png)
DE1210914B (de) 1966-02-17
GB955329A (en) 1964-04-15

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