US3293634A - Binary-to-decimal decoding matrix using static switches - Google Patents

Description

T. TEITEL Dec. 20, 1966 BlNARY-TO-DECIMAL DECODING MATRIX USING STATIC SWITCHES Filed March 4, 1963 INVENTOR TEODOR BERNARDEMANUEL BY 1' ITEL z/fm 0. m

15 Affor-ne United States Patent 3,293,634 BINARY-TO-DEQIMAL DECODING MATRIX USING STATIC SWITCHES Teodor Teitel, Bucharest, Rumania, assignor to Institute of Atomic Physics, Bucharest, Rumania Filed Mar. 4, 1963, Ser. No. 264,472 Claims priority, application Rumania, Mar. 5, 1962,

Claims. (cl. 340 347 The invention relates to a matrix composed of saturable reactors of a special design as static switching elements, enabling conversion from the one out of ten binary to the one out of ten counting system, the said matrix being adaptable to transistorized decimal-coded binary scaling circuits, enabling the direct driving of incandescent lamp projection read-out elements or of in-line display tubes (Nixie).

Decoding circuits using electromechanical relays are known, the said relays being driven by the collector current of transistors in the flip-flop stages, the display tubes being selectively switched through the combination of the changeover contacts of said relays. This system has the disadvantage of possessing moving elements, and, due to the existence of mechanical contacts, its reliability is low.

Known are also binary-to-decimal decoding circuits using static elements, such as solid-state diodes or resistors or a combination of diodes and resistors, adaptable to transistorized scaling units. Such circuits have the disadvantage of not being able to provide a voltage sufiicient to drive the in-line display tubes, or to provide currents suificiently large to drive the filamentary lamps of the inline projection display systems, intermediate amplifier stages being in that case required.

Known are also binary-to-decirnal decoding circuits using photoresistors illuminated by neon discharge tubes, the said neon tubes being driven by transistors, the said decoding circuits being able to drive the in-line display tubes. The disadvantage of these circuits is the fact that the decoding matrix is not directly driven by the scaling unit, an intermediate circuit for the neon discharge tubes being necessary, thus making the construction more complicated.

Known are also circuits containing magnetic amplifiers acting as relays, the collector direct current of the flipflop stages in the scaling unit being used to saturate some magnetic cores of the matrix. In this way an alternating current delivered by an auxiliary generator is switched, enabling a selective connection of the cathodes of the readout tubes or of the incandescent lamps, thus displaying the corresponding decimal figure. This system has the disadvantage of not being able to avoid the parasite couplings between the flip-flop stages through the direct current windings, due to the fact that each magnetic core has more than one direct current winding for controlling the saturation of said core; in this way reading-out the scaled figure can be done only when a counting period has elapsed.

Known are also circuits comprising a plurality of groups of magnetic modulators, having an alternating-current winding and a direct current winding for controlling the saturation of the core, the alternating-current winding of said modulators in each subgroup of magnetic modulators being series connected and having the center and outside ends of said series connection connected to receive a current from a subgroup of a previous group of the cascade connection. The disadvantage of this matrix consists in the fact that, for reason of avoiding the coupling between the alternating-current winding and the directcurrent winding, two modulators of the same subgroup are series-opposing connected. Due to the fact that the ratio of the number of turns of the direct-current winding 3,293,634 Patented Dec. 20, 1966 and that of the load winding is great, the induced voltages in the direct current windings become very large, thus implying special insulation problems. Apart from that, in order to obtain a satisfactory switching characteristic, a special magnetic material has to be used (cold rolled magnetic lamination) thus limiting, due to the magnetic losses, the supply frequency to a low value, which is consequently accompanied by an increase in dimensions,

The binary-to-decimal decoding matrix using static switches according to the invention has none of these disadvantages, due to the fact that, in order to avoid inductive couplings between the alternating current circuit and the direct current windings, its switching elements consist of two toroidal-shaped magnetic cores, the two said magnetic cores being laid tangentially in the same plane, each core having a load winding with few turns, the said load windings being series-opposing connected, and a common direct-current winding for controlling the saturation of said cores, all switching elements being identical and being connected in said matrix to provide a low impedance path for the alternating current between an input terminal and one the ten output terminals corresponding to the decimal figure indicated by the collector currents of the transistors in the flip-flop stages of the scaling unit.

In order to illustrate this, an example is given for decoding and displaying the indication of a transistorized scaling unit working according to the l248 counting diagram, referring to the wiring diagram in the figure.

According to the invention, the binary-to-decimal decoding matrix using static switches consists of eighteen identical switching elements, each of said switching elements having two toroidal magnetic cores, each core being made out of ferrite, thus allowing the use of a high frequency supply voltage.

The two said'cores of each switching element are situated tangentially, in the same plane, each having a few turns load winding a, the said windings being series opposing connected and charged by the load current. Through the holes of the two, toroidal-shaped, cores is a common winding b with many turns, allowing the two said cores of each switching element to be saturated when a direct current circulates through this winding. In this way the switching element may act as a relay closing the circuit for an alternating current if the cores are saturated, or exhibiting a high impedance in the alternating-current circuit, when the cores are not brought into saturation.

The series-opposing connection of the load windings, and the use of two magnetic cores having similar magnetic characteristics lead to no alternating voltage appearing in the direct current winding.

The load windings of these magnetic switching elements are cascade-connected in the matrix, according to the wiring diagram, enabling a connection to be established between the high-frequency generator terminal, and one of the ten read-out lamps 0 used to display the figures 0 9.

The direct-current windings of the eighteen magnetic switching elements are series-connected in the collector circuits of the transistors in the scaling unit, thus enabling the different steady-states of the flip-flop stages in said scaling unit to determine the saturation of cores of said switching elements which are connected in the collectors of the current-conducting transistors.

The connection of the magnetic switching elements in the matrix according to the invention enables the display for a l2-4-8 as well as for a l24-2 scaling unit. For instance, the binary number 0000 makes an alternating current flow through display unit 0, since all transistors on ways T, E, 1, g are condcting, thus providing a low impedance path between high-frequency generator G and display lamp 0, while binary number 1110 provides a load current on way 7, since only on this way have all switching elements their cores saturated (conducting are in this case transistors 1, 2, 4, 8).

The binary and decimal figures correspondence being unique, for each situation of the flip-flop stages in normal working condition of the scaling unit, there will be a load current flowing on a single way only, making the display unit indicate the decimal figure corresponding to the situation of the set flip-flop stages.

It is possible to connect on the ten output ways in the load circuit either filamentary lamps, in the case of in-line projection display units, or, after a subsequent impedancernatching, in-line display tubes (Nixie).

Compared to existing methods for displaying the indication of transistorized. scaling units, the invention has following advantageous features:

A great reliability is achieved, since the decoding matrix uses as active elements only saturable reactors;

The low electric power required to bring the magnetic cores into saturation enables the decoding matrix to be driven directly by the transistorized scaling unit, without the use of intermediate amplifier elements;

Using toroidal-shaped magnetic cores, and a common direct-current winding for controlling the saturation of a pair of cores, leads to a satisfactory switching characteristic, even if ferrite cores are used;

The use of ferrite magnetic cores permits the use of a high frequency supply for the load circuit, enabling a considerable reduction in size for the whole matrix;

The absence of parasite couplings between load and direct-current windings, as well as between the collector circuits of transistors in the flip-flop stages, enables the decoding matrix to work simultaneously with the scaling circuit;

The eighteen magnetic switching elements composing the matrix are identical and can easily be standardized as independent components that can be wired on a single printed board.

I claim:

1. A magnetic matrix decoder for connecting an input terminal selectively to one of ten output terminals to provide an output decimal system numerical indication of a multiple bit binary input, said matrix comprising, in combination, a plurality of magnetic switching elements arranged electrically at selected intersections of columns and rows, with the columns corresponding to respective binary input bits and the rows corresponding to respective numerical digits in the decimal system; each element comprising a pair of annular cores of magnetic material arranged in substantially coplanar juxtaposed relation; a load winding on each core, the load windings on the cores of each pair having the same number of turns and being connected in series opposite; a source of AC. potential; a matrix input terminal connected to one terminal of said source; a plurality of matrix output terminals each corresponding to a receptive one of said rows; a plurality of digit indicators each connected between a respective output terminal and the other terminal of said source, each digit indicator corresponding to a respective binary code input; said load windings being connected in cascade between said input terminal and said output terminals; the number and column position of the said elements connected to a respective output terminal corresponding to the binary code representation of the digit of the associated indicators; a plurality of control windings equal in number to said elements, each control winding being common to both cores of a respective element and those control windings arranged along a respective column being connected in series; and means for selectively applying a DC. potential to all of the control windings along selected columns in accordance with a respective binary code input to saturate those cores arranged along said columns to provide a low impedance A.C. path between said input terminal and the respective output terminal corresponding to said binary code input.

2. In a magnetic matrix decoder, a magnetic switching element comprising a pair of annular cores of magnetic material arranged in substantially coplanar juxtaposed relation; a load winding on each core, the load windings having the same number of turns and being connected in series opposition; means operable to impress an AC. potential across said series connected load windings; a control winding common to both of said cores; and means operable to selectively apply a DC. potential across said control winding to saturate said cores to provide a low impedance A.C, path through said load windings.

3. A magnetic matrix decoder, as claimed in claim 1, in which said source of AC. potential is a high frequency source.

4. A magnetic matrix decoder, as claimed in claim 1, in which said columns are arranged in pairs; said means for selectively applying said DC. potential comprising flip-flop transistor stages each controlling a pair of columns.

5. A magnetic matrix decoder, as claimed in claim 4, in which there are eighteen of said elements and four pairs of columns, a first pair of columns having the binary representations 1 and I, a second pair of columns having the binary representations 2 and 1 a third pair of columns having the binary representations 4 and I and a fourth pair of columns having the binary representations 8 and each of said digit indicators being associated with a respective row, and said digit indicators having indications from 0 to References Cited by the Examiner UNITED STATES PATENTS 3,086,198 4/1963 Tate 340347 MAYNARD R. WILBUR, Primary Examiner.

DARYL W. COOK, MALCOLM A. MORRISON,

Examiners. K. R. STEVENS, Assistant Examiner.

Claims (1)

1. A MAGNETIC MATRIX DECODER FOR CONNECTING AN INPUT TERMINAL SELECTIVELY TO ONE OF TEN OUTPUT TERMINALS TO PROVIDE AN OUTPUT CHEMICAL SYSTEM NUMERICAL INDICATION OF A MULTIPLE BIT BINARY INPUT, SAID MATRIX COMPRISING, IN COMBINATION, A PLURALITY OF MAGNETIC SWITCHING ELEMENTS ARRANGED ELECTRICALLY AT SELECTED INTERSECTIONS OF COLUMNS AND ROWS, WITH THE COLUMNS CORRESPONDING TO RESPECTIVE BINARY INPUTS BITS AND THE ROWS CORRESPONDING TO RESPECTIVE NUMERICAL DIGITS IN THE DECIMAL SYSTEM; EACH ELEMENT COMPRISING A PAIR OF ANNULAR CORES OF MAGNETIC MATERIAL ARRANGED IN SUBSTANTIALLY COPLANAR JUXTAPOSED RELATION; A LOAD WINDING ON EACH CORE, THE LOAD WINDINGS ON THE CORES OF EACH PAIR HAVING THE SAME NUMBER TURNS AND BEING CONNECTED IN SERIES OPPOSITE; A SOURCE OF A.C. POTENTIAL; A MATRIX INPUT TERMINAL CONNECTION TO ONE TERMINAL OF SAID SOURCE; A PLURALITY OF MATRIX OUTPUT TERMINALS EACH CORRESPONDING TO A RECEPTIVE ONE OF SAID ROWS; A PLURALITY OF DIGIT INDICATORS EACH CONNECTED BETWEEN A RESPECTIVE OUTPUT TERMINAL AND THE OTHER TERMINAL OF SAID SOURCE, EACH DIGIT INDICATOR CORRESPONDING TO A RESPECTIVE BINARY CODE INPUT; SAID LOAD WINDINGS BEING CONNECTED IN CASCADE BETWEEN SAID INPUT TERMINAL AND SAID OUTPUT TERMINALS; THE NUMBER AND COLUMN POSITION OF THE SAID ELEMENTS CONNECTED TO A RESPECTIVE OUTPUT TERMINAL CORRESPONDING TO THE BINARY CODE REPRESENTATION OF THE DIGIT OF THE ASSOCIATED INDI-

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