US3237172A - Impulse storage matrix comprising magnet cores having rectangular hysteresis loops - Google Patents

Impulse storage matrix comprising magnet cores having rectangular hysteresis loops Download PDF

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Publication number
US3237172A
US3237172A US715314A US71531458A US3237172A US 3237172 A US3237172 A US 3237172A US 715314 A US715314 A US 715314A US 71531458 A US71531458 A US 71531458A US 3237172 A US3237172 A US 3237172A
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Prior art keywords
cores
winding
sensing
extending
rows
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Expired - Lifetime
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US715314A
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English (en)
Inventor
Gosslau Karlheinz
Harloff Hans Joachim
Ohmann Friedrich
Schneider Gerd
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Siemens and Halske AG
Siemens Corp
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Individual
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
    • G11C11/06007—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit
    • G11C11/06014—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit using one such element per bit

Definitions

  • each individual magnet core a sensing winding which is linked with a plurality of cores, for example, with all cores disposed in one plane.
  • the sensing winding or conductor must for this reason be arranged so that the individual interference pulses, in a sensing winding linked with a plurality of cores, are not added, but are compensated, because it would -otherwise be impossible to recognize atrthe output of a sensing winding, especially if such winding should be linked with many or, for example, with all cores of a matrix, whether the impulse occurring responsive to a sensing operation comes from the demagnetizing of an individual core or is due to the addition or summation of interference pulses of several cores which had not been demagnetized. It has for this reason become customary to conduct or to extend the sensing winding diagonally through the individual cores of a plane, so as to satisfy the compensation requirement.
  • the diagonal winding can be provided only lby manual operations, because the relatively thin sensing wire cannot be carried through the very small cores by machine operation.
  • the sensing loop is in the diagonal arrangement rendered very long.
  • the invention is concerned with an arrangement of a sensing winding or conductor, in such storage matrices, proposing an entirely new way of effecting the compensation for the interference pulses.
  • the sensing conductor is disposed parallel to one of the control lines or conductors and the interference pulses induced by the partially energized cores are compensated by means of compensation cores arranged within the matrix of the sensing con- 3,2371?? Patented F eb. 22, 1966 ICC ductor, incident to sensing and storage operations, by proper triggering of the compensation cores.
  • the compensation cores as storage cores, that is, to construct the storage matrix, taking care, either by proper choice of the triggering of the individual cores or by proper arrangement of the sensing conductor parallel to one of the control lines, so that one matrix can be utilized for storage functions, as until now, but at the same time fulfilling the above explained compensation conditions.
  • FIG. l shows a storage matrix comprising 24 cores
  • FIG. 2 indicates the triggering along the Y-line or conductor
  • FIG. 3 illustrates the conditions along row 3 of FIG. 1;
  • FIG. 4 shows an example of arranging the cores within a plane so that a meandering blocking winding or conductor extends in preferred direction
  • FIG. 5 illustrates an example of the arrangement of a single row of cores
  • FIG. 6 shows an arrangement in which the sensing winding extends in meandering manner alternately between two respective rows so that it is linked in each direction with the same number of cores.
  • the cores M are arranged in four columns each having six cores or in six rows each having four cores.
  • the control lines or conductors I to IV linked with the cores in the coordinate direction of the columns may be referred to as Y-lines and the control lines 1 to 6 linked with the cores in the coordinate direction of the rows may be referred to as Xlines.
  • each individual core is linked with a sensing line extending between the terminals a-a.
  • the sensing winding meanders in parallel with the X-lines, the individual meander loops being crossed in such a manner that a portion of the loop appears as a feed and return conductor in each individual row.
  • the individual cores of the matrix are referred to according to their column and row number, respectively.
  • a triggering impulse flowing along control line II from the top downwardly will induce at the core M111 as well as at all further cores of the corresponding column II, a current impulse in the sensing Winding which is directed to the right.
  • the magnitude of this interference pulse is at all cores approximately the same. It will at once be realized from FIG. 2, that these interference pulses are compensated in pairs and that no voltage can occur Iat the terminals a-a in the absence of corresponding triggering in the third row, resulting in opposite magnetization of the core.
  • a Z-conductor a meandering conductor extending generally in parallel to one of the control conductors, such Z-conductor permeating all cores in a plane or, in case of special structures of magnetic storage apparatus, portions of a plane.
  • Interference pulses induced by the impulses over the Z- conductor and occurring in a non-energized plane are not as a rule as troublesome as interference pulses induced by the impulses conducted to the control lines; however, suppression of the corresponding interference pulses may be of great interest whenever there is danger, due to high operating speed, that these interference pulses might adversely affect a subsequent sensing pulse.
  • Another danger resides in the possibility that interference pulses of great magnitude, induced in the sensing winding of a non-energized plane, may falsify stored information, or that such interference pulses might by induction, similar to the cross-talk effect, produce an impulse in a neighboring plane that should not occur therein.
  • the invention makes this possible by arranging the cores within a plane in herringbone-like manner, that is, disposing the magnet cores so as to slant about 45 to the right in the coordinate while slanting in the adjacent coordinate, row or column, about 45 to the left, the meandering blocking winding extending in this manner in preferred direction of the pattern.
  • FIG. 4 shows an example of such an embodiment, wherein the cores of any two adjacent columns slant angularly in opposite directions.
  • the Z-winding extends in individual sections parallel to the Y-conductors, meandering throughout the entire matrix.
  • the compensation of the control pulses conducted over the X- and Y-conductors is effected in the manner already explained in connection with FIGS.
  • an interference impulse will be induced to the left, in the sensing winding at all cores.
  • the individual interference impulses are compensated within the loop of the sensing winding which extends with respect to the X-conductor in the form of a crossing meandering loop.
  • the invention is not inherently limited to the illustrated and described matrix embodiments. As will be readily realized, it is entirely feasible to allot the cores at the left of the crossing points of the sensing winding (FIG. l) to an individual matrix while allotting the cores at the right of these points to another matrix, and to dispose the sensing winding for both planes in common, in such a manner, that the described compensation conditions are satisfied. Such an arrangement is shown in FIG. 6. Parts corresponding to those also shown in FIG. 1 are identically referenced in FIG. 6. The purpose and object of the invention will be obtained in such a case.
  • a signal storage device constructed of a plurality of magnet cores with at least approximately rectangular hysteresis loop, said cores arranged in a plurality of lines in two coordinate directions forming rows and columns, said cores being interlinked with at least two control windings and further interlinked with a sensing winding that is common to at least a plurality of said cores and having portions extending in parallel with said rows and columns, said sensing winding being disposed in meandering manner with each successive parallel portion thereof, extending in one of said coordinate directions, being disposed in an adjacent line extending in such coordinate direction, with a crossover to an adjacent line taking place midway between the total number of cores interlinked by said winding in the line involved, following each successive odd numbered of such successive parallel portions, with such winding extending in interlinking relationship with equal numbers of cores in each of the rows and columns in either direction of its meandering course whereby interference pulses induced into said sensing winding are compensated therein.
  • a signal storage device constructed of a plurality of magnet cores with at least approximately rectangular hysteresis loop, said cores arranged in a plurality of lines in two coordinate directions forming rows and columns, said cores being interlinked with at least :two lcontrol windings and further interlinked ⁇ with a sensing winding that is common to at least a plurality of said cores and having portions extending in parallel with said rows and columns, said sensing winding being disposed in meandering manner with portions thereof alternately disposed in sucessive pairs of lines in one of said coordinate directions, with such winding extending in interlinking relationship with equal numbers of cores in each of the rows and columns in either direction of its meandering course whereby interference pulses induced into said sensing winding are compensated therein, and an inhibit winding extending in meandering manner Within a storage plane, the cores in any tWo adjacent lines extending in coordinate direction being in said plane angularly oppositely inclined such that the turns of said inhibit winding extend in direction of
  • a signal storage device comprising two storage planes, each having a plurality of magnet cores with at least approximately rectangular hysteresis loop, said cores arranged in a plurality of lines in two coordinate directions forming rows and columns, said cores being interlinked with at least two control windings and further interlinked with a sensing winding that is common to at least a plurality of -said cores and having portions extending in parallel with said rows and columns, said sensing winding being disposed in meandering manner with each successive parallel portion thereof, extending in one of said coordinate directions, being disposed in an adjacent line extending in such coordinate direction, with a crossover to an adjacent line taking place midway between the total numer of cores interlinked by said winding in the line involved, following each lsuccessive odd numbered of such successive parallel portions, with such winding extending in interlinking relationship with equal numbers of cores in each of the rows and columns in either direction ⁇ of its meandering course whereby interference pulses induced into said sensing winding are

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Transmission And Conversion Of Sensor Element Output (AREA)
  • Magnetic Resonance Imaging Apparatus (AREA)
US715314A 1957-02-22 1958-02-14 Impulse storage matrix comprising magnet cores having rectangular hysteresis loops Expired - Lifetime US3237172A (en)

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DES0052459 1957-02-22

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US (1) US3237172A (enrdf_load_stackoverflow)
DE (1) DE1069681B (enrdf_load_stackoverflow)
FR (1) FR1202201A (enrdf_load_stackoverflow)
GB (1) GB885495A (enrdf_load_stackoverflow)
NL (2) NL224994A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3478333A (en) * 1964-02-24 1969-11-11 Gen Motors Corp Magnetic memory system
US3478338A (en) * 1963-03-26 1969-11-11 Ncr Co Sensing means for a magnetic memory system
US5060189A (en) * 1986-06-13 1991-10-22 Sharp Kabushiki Kaisha Semiconductor device with reduced crosstalk between lines

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1295015B (de) * 1964-11-09 1969-05-14 Siemens Ag Magnetischer Koinzidenzspeicher
NL249296A (enrdf_load_stackoverflow) * 1959-03-11
NL277856A (enrdf_load_stackoverflow) * 1961-05-15
FR1351083A (fr) * 1962-03-15 1964-05-04 Siemens Ag Matrice de mémoire à couches de stockage magnétiques minces
US3325791A (en) * 1963-02-27 1967-06-13 Itt Sense line capacitive balancing in word-organized memory arrays
DE1295016B (de) * 1964-09-30 1969-05-14 Siemens Ag Magnetischer Speicher

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2732542A (en) * 1954-09-13 1956-01-24 minnick
GB769384A (en) * 1954-05-20 1957-03-06 Ibm Transformer matrix system
US2802203A (en) * 1955-03-08 1957-08-06 Telemeter Magnetics And Electr Magnetic memory system
US2880406A (en) * 1955-05-25 1959-03-31 Ferranti Ltd Magnetic-core storage devices for digital computers
US2929050A (en) * 1955-05-27 1960-03-15 Ibm Double ended drive for selection lines of a core memory
US3008130A (en) * 1957-08-19 1961-11-07 Burroughs Corp Memory construction
US3102328A (en) * 1957-12-31 1963-09-03 Ibm Method of packaging and interconnecting circuit components
US3134163A (en) * 1955-11-21 1964-05-26 Ibm Method for winding and assembling magnetic cores

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL263626A (enrdf_load_stackoverflow) * 1954-03-16

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB769384A (en) * 1954-05-20 1957-03-06 Ibm Transformer matrix system
US2732542A (en) * 1954-09-13 1956-01-24 minnick
US2802203A (en) * 1955-03-08 1957-08-06 Telemeter Magnetics And Electr Magnetic memory system
US2880406A (en) * 1955-05-25 1959-03-31 Ferranti Ltd Magnetic-core storage devices for digital computers
US2929050A (en) * 1955-05-27 1960-03-15 Ibm Double ended drive for selection lines of a core memory
US3134163A (en) * 1955-11-21 1964-05-26 Ibm Method for winding and assembling magnetic cores
US3008130A (en) * 1957-08-19 1961-11-07 Burroughs Corp Memory construction
US3102328A (en) * 1957-12-31 1963-09-03 Ibm Method of packaging and interconnecting circuit components

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3478338A (en) * 1963-03-26 1969-11-11 Ncr Co Sensing means for a magnetic memory system
US3478333A (en) * 1964-02-24 1969-11-11 Gen Motors Corp Magnetic memory system
US5060189A (en) * 1986-06-13 1991-10-22 Sharp Kabushiki Kaisha Semiconductor device with reduced crosstalk between lines

Also Published As

Publication number Publication date
NL113656C (enrdf_load_stackoverflow)
NL224994A (enrdf_load_stackoverflow)
GB885495A (en) 1961-12-28
DE1069681B (enrdf_load_stackoverflow) 1959-11-26
FR1202201A (fr) 1960-01-08

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