US2979701A - Matrix memory system - Google Patents

Matrix memory system Download PDF

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Publication number
US2979701A
US2979701A US766311A US76631158A US2979701A US 2979701 A US2979701 A US 2979701A US 766311 A US766311 A US 766311A US 76631158 A US76631158 A US 76631158A US 2979701 A US2979701 A US 2979701A
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United States
Prior art keywords
conductors
conductor
core
cores
pulse
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Expired - Lifetime
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US766311A
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English (en)
Inventor
Marchand Jean Francois
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US Philips Corp
North American Philips Co Inc
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US Philips Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
    • G11C11/06007—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit
    • G11C11/06014—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit using one such element per bit

Definitions

  • This invention relates to a matrix memory system comprising a plurality of memory elements each of which is made of magnetic material having a high remaneuce.
  • the memory elements areeachmagnetically coupled to one of a first group of conductors and to one of a second group of conductors, means being provided 'for changing the magnetic state of a certain memory element by variation of the electrical state of the group conductors coupled to this memory core.
  • Fig. 2 shows an example of a hysteresis loop a, b, c, d, e, f, g, h, i, a, of a" magnetic material which can be used in the cores K11, K12, and so on.
  • Each core can be either in a state of positive magnetic remanence P or in a state of negative remanence N, these states corresponding, for example, to the binary digits 1 and 0.
  • a certain core for example K22
  • a certain remanencejstate for example the state P
  • the double pulse 2] ' is applied to the core K22. If this core was in the state N, the branch a, b, c, d, e, f, of the hysteresis loop is traversed so that the core is set to the state P.
  • the cores K21, K23, K12 and K32 have only the single pulse I applied to them in order that their magnetic states are not changed under the control of the single pulse J.
  • Fig. 1 shows a system in accordancewith theinvention
  • I Fig. 2 shows a hysteresis loop of a magneticmaterial which can be used in this system
  • p Fig.3 shows a modified embodiment of a system in accordance with the invention.
  • e i i Fig. 1 shows diagrammatically a' number of memory elements K11, K12, K13 K32, K33 made of a mag netic material having a rectangularhysteresis loop and arranged according to a matrix. All cores of one horizontal row are coupled to one horizontal conductorHl, H2 and H3 respectively, and all cores of one vertical column are coupled to one vertical conductorjVl, V2
  • the ends of the conductors are for example, be transformers the primary windings of which are constituted bythe conductors H1, H2 and, so on,,a secondary winding of each transformer .Ibeing short-circuited, forexample, through a transistor so that the internal impedances of-the transistors are stepped down towards the conductors
  • the short-circuit can 'be
  • the hysteresis loop shOWn in Fig. 2 does not satisfy this requirement, for in this loop the pulse strength .I exceedsthe'current IK corresponding to the knee b in the hysteresis loop. It should be noted that in practice the knees b' and g generally are lesssharply bent than is shown in the drawing.
  • Thecores K21, K23, K12 and K32, to which only the single pulse Iis applied, will be. driven only under the control of this pulse and with the shape shown of the hysteresis curve along the branch ab-cj; consequently, on termination of the pulse, these cores do not return to the zero state N but will be set to the state j. In other words, the zero state is disturbed and thisis undesirable. 2
  • the switch contacts CHZ'and CV2 are switched over to the work position so that the conductors H2 and V2 are connected to the pulse source JB.
  • the core K22 similarly to what has been described hereinbefore, under the control of the double pulse.2J traverses the branch a- -b cde-fof the hysteresis loop and passes to state P.
  • the cores K21, K23, K12fand K32 likewise have a current pulse] applied to them through the conductors H2 and V2. In the system shown in Fig. 1, however, the
  • the number of cores associated with one conductor can be high without any difficulty, for example may be 100 or more, provided that the spacings between the cores are not too large, for example /2 cm. or less.
  • An advantage of the system described as compared with the known systems consists in that with the use of the same magnetic material the strength of the applied pulses can be greater so that the speed at which the system can be operated can be higher than in the known systems.
  • the abrupt changes of the magnetization states in a core have a cer' tain inertia, the speed of these changes being proportional not to the strength of the pulse but to the pulse strength less a constant value corresponding to the coercive force. This means that the rate of change increases with the pulse strength not proportionally but at a higher rate.
  • Reading-out of the information from a certain core, for example K22 can take place similarly.
  • the conductors H2 and V2 are connected to a source the polarity of which is opposite to that of the source used in storing.
  • this core will pass to the state so that a reaction pulse can be taken from an auxiliary conductor coupled to all cores (not shown in the drawing).
  • a change of the magnetic state of the cores K21, K23, K12 and K32 is in this event prevented by the occurrence of reaction currents in the remaining short-circuited conductors similarly to what occurs in the process of storing information.
  • the information is stored or read out by simultaneously applying a pulse to both conductors coupled to a certain core.
  • a cer: tain core for example K22
  • the remanence state of a cer: tain core can be changed to the opposite state by applying a pulse to only one of the conductors H2 and V2, for example to the conductor H2, and eliminating the short-circuit of the other conductor V2. Consequently the conductor V2 is not connected to a pulse source and the pulse source to be connected to the conductor H2 must have a strength which is double that used in the preceding case.
  • Fig. 3 shows a modified embodiment .of the system in accordance with the invention, in which control pulses no longer have to be applied to individual control conductors, as in the case in the known systems, but only to a single control point SB common to all cores.
  • the cores of one horizontal row are coupled to one horizontal conductor H1 H4 respectively and the cores of one vertical column are coupled to one vertical conductor V1 .V4 respectively.
  • Switching contacts in the form of transformers CH1 CH4 and CV1 CV4 respectively, the primary windings of which are constituted by the conductors H1 H4 and V1 V4 respectively, are connected in series with the conductors.
  • the ends of the secondary windings are connected to the emitters and collectors of transistors, for example TH3 and TV4, as is shown for the transformers CH3 and CV4.
  • a tapping on each secondary winding is earthed while the bases of the transistors are connected to a negative voltage supply through resistances, for example RH3 and RV4.
  • the two blocking layers of the transistors are conductive, a current flowing from the emitter to the base and from the collector to the base.
  • the internal impedance of the transistors when conducting is comparatively low and of the order of magnitude of a few ohms.
  • the conductor SH extends in parts parallel to all horizontal conductors H1, H2, H3 and H4 and is arranged in closest proximity to these conductors so that there is strong magnetic coupling with those conductors; hence, when an alternating current fiows in the conductors SH, there is induced in a short-circuited conductor H1 H4 a current the direction of which is opposite to that of the current in the conductor SH, the current amplitudes being substantially equal.
  • the conductor SV is arranged similarly so as to extend parallel to the vertical conductors V1 V4 and tightly coupled therewith magnetically so that an alternating current in the conductor SV produces an opposite reaction current in each vertical conductor V1 .V4.
  • this eltect can be further enhanced by coupling the control conductor to the short-circuit conductors by means of a separate transformer auxiliary coupling, for example by means of an auxiliary core of high-frequency magnetic material, such as the core HK shown in broken lines.
  • the conductors SV and SH can be connected in series.
  • Storing of information in a certain core is effected by applying a positive potential to terminals BH3 and BV4 so that the transistors TH3 and TV4 are cut off, the short-circuit of the conductors H3 and V4 thus being eliminated,
  • a current pulse of suitable polarity which is applied through the control terminal SB to the conductors SV and SH, causes the core K34 to pass to the desired remanence state.
  • the other cores are not influenced by this pulse since each of these cores remains coupled to at least one short-circuited conductor so that any change in the state of magnetization is counteracted by the reaction current in these shortcircuited conductors.
  • Reading-out the information from a certain core can be effected similarly by applying in the manner described a pulse of opposite polarity to this core so that a reaction pulse can be taken from a readout conductor coupled to all cores (not shown).
  • This method has a disadvantage in that, in the process of reading-out, the information is destroyed and, if required, must be stored again.
  • the information can alternatively be read out by means of an alternating current the amplitude of which is so small that the remanence state of the core concerned is not changed.
  • the short-circuit of the conductors H3 and V4 is eliminated by cutting-off the transistors TH3 and TV4 while at the same time an alternating current is supplied to the control conductors SH and SV through the terminal SB.
  • the positive phase of this reaction current for example, exceeds the negative phase while conversely, if the core K34 should be in the state P, the positive phase of the reaction current would be smaller than the negative phase.
  • the amplitude of the read-out alternating current at the terminal SB can advantageously be made much greater than the value IK provided that the frequency of this alternating current is made sufficiently high, for example higher than 1 mc./s., in which event the process remains reversible, the value of the reaction current, however, being greater than with a comparatively small value of the read-out alternating current.
  • a matrix memory system comprising a plurality of memory elements composed of magnetic material having a substantially rectangular hysteresis loop, first and second groups of conductors, each element being magnetically coupled to one conductor of the first group and one conductor of the second group, means for varying the electric state of the conductor of each group coupled to a desiredelement, and means for short-circuiting each of the remainder of the conductors of the matrix, whereby undesirable remanences in the remaining elements of the matrix are eliminated.
  • each element is an annular magnetic core.
  • a memory system as claimed in claim 1, wherein said short-circuiting means comprises a highly conductive frame surrounding said matrix, both ends of each conductor being connected to said frame.
  • said varying means comprises at least one control conductor magnetically coupled to each memory element and also arranged in close magnetic coupling proximity to all conductors of each group, whereby the current in the control conductor produces a reaction current in each short-circuited conductor thus cancelling the elfect of the control current therein.
  • a matrix memory system comprising a plurality of annular magnetic memory cores composed of magnetic material having a substantially rectangular hysteresis loop, first and second groups of conductors, each core being magnetically coupled to one conductor of the first group and one conductor of the second group, means for applying a writing pulse to the conductor of each group coupled to a desired element, each pulse having a magnitude one-halfof that'necessary to change-over a core from one saturation condition to another, and means for short-circuiting each of the remainder of the conductors of the matrix, whereby undesirable remanences in the remaining cores of the matrix areeliminated.
  • a matrix memory system comprising a plurality of annular magnetic memory cores composed of magnetic material having a substantially rectangular hysteresis loop, first and second groups of conductors, each core being magnetically coupled to one conductor of the first group and one conductor of the second group, means for short-circuiting each of the conductors of the matrix, means for applying a writing pulse to a selected conductor of one group, means for eliminating the short-circuit of a selected conductor of the other group, the magnitude of said writing pulse being suflicient to change-over a core from one saturation condition to another, whereby undesirable remanences in all cores other than the core coupled to said selected conductors are eliminated.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Manufacturing Cores, Coils, And Magnets (AREA)
  • Soft Magnetic Materials (AREA)
US766311A 1957-10-17 1958-10-09 Matrix memory system Expired - Lifetime US2979701A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL221692 1957-10-17

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US2979701A true US2979701A (en) 1961-04-11

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US766311A Expired - Lifetime US2979701A (en) 1957-10-17 1958-10-09 Matrix memory system

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US (1) US2979701A (en(2012))
BE (1) BE572063A (en(2012))
CH (1) CH368526A (en(2012))
DE (1) DE1074297B (en(2012))
FR (1) FR1212422A (en(2012))
GB (1) GB852397A (en(2012))
NL (2) NL97500C (en(2012))

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3130391A (en) * 1959-08-29 1964-04-21 Int Standard Electric Corp Circuit arrangement for ferrite-core storage devices
US3146428A (en) * 1960-09-02 1964-08-25 Ncr Co Data storage system
US3177473A (en) * 1959-02-26 1965-04-06 Philips Corp Magnetic memory device
US3191161A (en) * 1958-10-29 1965-06-22 Ncr Co Means for driving magnetic storage elements
US3196413A (en) * 1960-12-19 1965-07-20 Ibm Non-destructive magnetic memory
US3215993A (en) * 1961-05-31 1965-11-02 Bell Telephone Labor Inc Magnetic core switching circuits
US3222656A (en) * 1959-09-16 1965-12-07 Ericsson Telefon Ab L M Magnetic memory arrangement
US3248714A (en) * 1961-12-19 1966-04-26 Ibm Parametron selection system
US3307161A (en) * 1962-01-08 1967-02-28 Raytheon Co Multiaperture core memory system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2691154A (en) * 1952-03-08 1954-10-05 Rca Corp Magnetic information handling system
US2734187A (en) * 1951-12-29 1956-02-07 rajchman

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2734187A (en) * 1951-12-29 1956-02-07 rajchman
US2691154A (en) * 1952-03-08 1954-10-05 Rca Corp Magnetic information handling system

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3191161A (en) * 1958-10-29 1965-06-22 Ncr Co Means for driving magnetic storage elements
US3177473A (en) * 1959-02-26 1965-04-06 Philips Corp Magnetic memory device
US3130391A (en) * 1959-08-29 1964-04-21 Int Standard Electric Corp Circuit arrangement for ferrite-core storage devices
US3222656A (en) * 1959-09-16 1965-12-07 Ericsson Telefon Ab L M Magnetic memory arrangement
US3146428A (en) * 1960-09-02 1964-08-25 Ncr Co Data storage system
US3196413A (en) * 1960-12-19 1965-07-20 Ibm Non-destructive magnetic memory
US3215993A (en) * 1961-05-31 1965-11-02 Bell Telephone Labor Inc Magnetic core switching circuits
US3248714A (en) * 1961-12-19 1966-04-26 Ibm Parametron selection system
US3307161A (en) * 1962-01-08 1967-02-28 Raytheon Co Multiaperture core memory system

Also Published As

Publication number Publication date
BE572063A (en(2012))
NL97500C (en(2012))
GB852397A (en) 1960-10-26
CH368526A (de) 1963-04-15
DE1074297B (de) 1960-01-28
NL221692A (en(2012))
FR1212422A (fr) 1960-03-23

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