US2691155A - Memory system - Google Patents

Memory system Download PDF

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US2691155A
US2691155A US346162A US34616253A US2691155A US 2691155 A US2691155 A US 2691155A US 346162 A US346162 A US 346162A US 34616253 A US34616253 A US 34616253A US 2691155 A US2691155 A US 2691155A
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Prior art keywords
pulse
switch
core
cores
memory
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Rosenberg Milton
Stuart-Williams Raymond
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RCA Corp
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RCA Corp
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Priority to US346162A priority Critical patent/US2691155A/en
Priority to US33790253 priority patent/US2734184A/en
Priority to CH331049D priority patent/CH331049A/de
Priority to GB3497/54A priority patent/GB753025A/en
Priority to FR1095967D priority patent/FR1095967A/fr
Priority to CH323365D priority patent/CH323365A/de
Priority to BE526599D priority patent/BE526599A/xx
Priority to NL185257A priority patent/NL93839C/xx
Priority to JP318854A priority patent/JPS307759B1/ja
Application granted granted Critical
Publication of US2691155A publication Critical patent/US2691155A/en
Priority to DER13623A priority patent/DE1051034B/de
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
    • G11C11/06007—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit
    • G11C11/06014—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit using one such element per bit
    • G11C11/06021—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit using one such element per bit with destructive read-out
    • G11C11/06028—Matrixes
    • G11C11/06035—Bit core selection for writing or reading, by at least two coincident partial currents, e.g. "bit"- organised, 2L/2D, or 3D
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/80—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using non-linear magnetic devices; using non-linear dielectric devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/80—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using non-linear magnetic devices; using non-linear dielectric devices
    • H03K17/81—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors

Definitions

  • This invention relates to magnetic switching matrices such as are used, for example, in controlling the writing of information into and the reading of information out of memory matrices.
  • the array of magnetic cores is described in these articles as a memory device able to store binary coded information as a P or N saturation condition of the cores. It will be appreciated that if a different coil is coupled to each core in a matrix, as a core in the matrix is driven from one saturation polarity to the other a voltage is induced in the coil. This voltage may be applied to any utilization devices.
  • the matrix thus can be used for random switching operations including that of driv ing a magnetic matrix memory.
  • a system wherein two magnetic matrix switches of this type are used to control a magnetic matrix memory may be found described and claimed in an application Ser. No. 264,217, by Jan A. Rajchman, filed December 29, 1951, and assigned to this assignee.
  • two or more switches of this improved type are utilized to control a magnetic memory matrix in the manner described in the above indicated RCA Review article and application, and pulses which control these switches may be terminated either concurrently or in succession, selectively to determine whether a selected core of the memory matrix is left in a desired state of N-saturation or in a desired state of P-saturation.
  • the pulses for operation of the switches are produced in a program control network including a master pulse former which ates all common drivers of the switches and a second pulse former which provides an inhibiting or driving pulse for the drivers of one of the switches and which may be applied or withheld, depending upon the information to be stored or restored in the memory matrix.
  • a master pulse former which ates all common drivers of the switches
  • a second pulse former which provides an inhibiting or driving pulse for the drivers of one of the switches and which may be applied or withheld, depending upon the information to be stored or restored in the memory matrix.
  • the master pulse may be applied to a switch common to one side of all memory matrices and to switches individual to the other side of each of the matrices.
  • the output of the second pulse former may be applied or withheld from each of the latter switches depending upon the information to be stored or restored in the associated memory matrix.
  • the invention further resides in features of construction, combination and arrangement hereinafter described and claimed.
  • Figure 1 schematically illustrates an element of a magnetic switching matrix shown to assist in explanation of the present invention
  • Figure 2 is an explanatory figure referred to in discussion of Figure 1;
  • Figure 3 is a simplified block diagram of a switching arrangement for a memory matrix
  • Figures 4A, 4B and 4C are explanatory wave shape figures referred to in discussion of Figures 1, 3 and other figures;
  • Figure 5 schematically illustrates a switching matrix embodying the switching elements of Figure 1 and a program control network which is an embodiment of the invention
  • Figure 5A is a schematic illustration of a switch program control network which is an alternative to the one shown in Figure 5;
  • Figure 5B illustrates a gate and driver circuit suitable for use in driving the magnetic switch cores responsive to address
  • Figure 6 schematically illustrates a parallel memory matrix system controlled by programmed switches embodying the present invention
  • Figures TA, '73 and 7C illustrate modifications of Figure 1;
  • FIG. 8 schematically illustrates another parallel memory matrix arrangement controlled by programmed switches embodying the present invention.
  • Figure 9 represents circuit diagrams of gates which are employed in the embodiment of the invention.
  • the simplest possible switch element E which is utilized in the switching matrices later described is shown in Figure 1.
  • the core in is preferably toroidal in form and is made of magnetic material which may have a hysteresis characteristic such as is shown in Figure 2.
  • the switching coils or conductors I! and I2 are wound in the same direction or suitably poled so that they are cumulative in their efiect upon the core.
  • the winding [3 is oppositely poled or wound and is continuously energized by direct current.
  • the direct current traversing winding I3 is of such magnitude that it biases the core material to a point NI on its B/H curve ( Figure 2).
  • the core I0 is continuously biased by the direct-current in winding I3 to a point of N-saturation well beyond the lower knee of the hysteresis loop. If a current pulse, such as pulse Pl or P2 ( Figures 4A, 4B, 4C) is applied to only one of the windings II, I 2, the core material shifts from point NI to N2 at the beginning of the pulse and back from point N2 to point NI at the termination of the pulse.
  • a current pulse such as pulse Pl or P2 ( Figures 4A, 4B, 4C)
  • each of the rectangles I5 and 15 represents a switching matrix comprising a plurality of switching elements of the type shown in Figure 1. All of the biasing windings of the cores in each switching matrix are connected together as a common winding for energization from a suitable source of direct current, not shown.
  • the cores of each matrix may be arranged in columns and rows with the switching windings II of all cores in each column interconnected, as in series, to provide a separate X input coil and with the switching windings l2 of the cores in each row interconnected, as in series, to form a separate Y input coil.
  • the output windings MX, NW of the selected switch cores IIIX, IDY are both inductively coupled to a selected core IOM of a magnetic memory matrix I! which may be of any of the types disclosed in the aforesaid articles or application.
  • These memory cores store binary digital information as saturation at P or N, thus the material of the memory cores such as M require qualities such as high remanence and a substantially rectangular hysteresis loop.
  • the combined output of the excited coils MX, NW of the selected switching cores IBX, IOY is suflicient to drive the core IBM of the memory matrix from P-saturation to N-saturation. If, however, the pulses to the switches I5 and it are not so terminated, none of the non-coincident outputs of the coils I4X, MY of the switching cores IOX, IDY is suificient to turn over the memory core IBM which therefore remains in a state of P-saturation.
  • the writing operation requires two intervals.
  • the first interval is the one in which the switch cores are selected and driven to P.
  • the driving currents in the switches are then allowed to subside.
  • the second interval is the one wherein the selected cores in the switches are either simultaneously or separately returned to N In the present invention no second interval as a separate entity is required.
  • any of the IOXa: addresses of the switch I5A may be combined with any of its IllXy addresses to select, in accordance with the X address of a bit of information, that one of its 100 switch cores which is to be shifted from point NI to point P of its magnetization curve. Either the X address or the Y address, or both, of a particular bit of information may be set prior to a cycle of the control or switching pulses.
  • the program control network PC which supplies the paired pulses to the switch matrices is shown in the left side of Figure 5.
  • the instruction to write is in the form of a pulse applied from a source (not shown) through line H! to the master pulse former l9 whose output may be represented by a short pulse MP.
  • the pulse former [9 may be a one-shot multlvibrator, followed by a shapin stage, or
  • the master pulse may be applied to the grids of the cathode follower tubes 20 and 22 or equivalent by lines 3IX, 3lY.
  • the output oftube 20 is applied through lines Zlw, '2Iy to the X switch I5A: specifically, the master pulse output of tube 20 is applied to the combined driver and gate tubes VCI-VC I 0 for the column input coils Cl-Clfl of switch
  • the output pulse of control tube 22 is concurrently applied by line 23 to the combined driver and gate tubes of the Y switch (not shown but similar to X switch I5A) to enable the addressed ones of these tubes to conduct.
  • each of the column coils Cl-Cl0 of switch 15A includes the serially-connected windings II on all the cores in that column and each of the row coils Rl-Rlll includes the serially-connected windings IE on all of the cores of that row.
  • the direct-current B winding common to all cores of switch I5A includes the coils or conductors [3 of all of the cores.
  • each element of switch I5A is similar to the element shown in Figure 1 with its coil [I in a particular column, with its coil l2 in a particular row and with its coil is continuously energized by direct current.
  • a particular core of the switch I5A is selected in accordance with the X address of the information, which has previously been applied as a signal to the control grid of a particular one of the column tubes VCi-VCIG and a particular one of the row tubes VRl-VRlil This will move the magnetic position of the switch core coupled to the two coils excited by application of a signal to their associated row and column tubes from the point NI to point P, Figure 2, as above described. Because of the change in flux of the selected core of switch.
  • a P-driving impulse RP will appear across the output coil M of the selected core of X switch ltA and serves, as noted in Figure 3, as a driving pulse for the corresponding column coil of a memory matrix.
  • a P driving impulse from the selected core of that switch is supplied to the corresponding row coil of the memory matrix.
  • one core of the memory matrix is subjected to both output pulses RP of the switching matrices and it alone is driven to P-saturation.
  • the to-Write instruction pulse is applied not only to the master pulse former [9 but also to the write P pulse former which provides an output pulse PP which continues after the master pulse MP terminates.
  • the pulse former 24 may be the same type of circuit as pulse former I9.,with
  • the write P" pulse PP can pass to the control grid of tube 30 by means of an and gate 25.
  • the plate and cathode of tube 30 are in parallel with those of tube 22.
  • the and gate 25 is merely a coincidence-switch of the type requiring two coincident inputs to provide one output.
  • a suitable and gate circuit may be found described and shown on page 378 of a book entitled Waveforms by Chance et al. and published by the McGraw-I-Iill Book Company, Inc., in 1949.
  • the pulse PP is not applied to tube 30 and the pulses PX, PY, respectively applied to the X switch matrix ISA and the Y switch matrix (not shown) terminate at the same instant. Consequently, the selected cores. of both switching matrices simultaneously shift back to N-saturation due to the biasing current in their coils B (windings l3 in series) to produce coincident output pulses FP for the selected core of the memory matrix. As above explained in discussion of Fi ure 3, these coincident pulses drive the selected memory core from P-saturation to N-saturation. Thus, if the gate 25 is not opened during the program cycle, the bit of information retained by the selected memory core is N.
  • the gate 25 is opened during the program cycle.
  • the pulse PP is transmitted to tube 30 and the pulse PY transmitted to the Y switch does not terminate until after termination of the pulse PX for the switch.
  • the output pulses FP of the two switching matrices are not coincident and, since they individually are incapable of driving the memory core from P to N, the memory core remains in the P-state.
  • the switch matrices do not require application of any N restoring pulse, the selected core of the switch being returned to NI by a direct-current bias in the common bias winding upon termination of the control pulse PX or PY, as the case may be. It is also to be noted that before termination of the shorter pulse MP, it has been determined whether the information to be retained by the selected memory core is N or P. Accordingly, when a reading operation occurs a memory core will or will not provide an output indicative of its condition on the front edge of pulses PX and PY so that before termination of pulse MP the stored information can be read out and the pulse PP used, if necessary, to restore that information in the selected memory core.
  • the write P register 26 which may also be a oneshot multivibrator and which receives a restore P instruction or a write P instruction in the form of a tripping pulse from either of the sources 21, 28. If it is desired to write P, then a pulse from the write P instruction source 28 is applied to the register 26. The register primes the and gate 25 so that pulse PP may be passed through. It will be recalled that the reading of the information stored in a core in a magnetic memory is performed by driving that core in a direction N. If a voltage is induced in the reading winding of the memory coupled to that core then it is known that the core was in condition P.
  • the core must be restored to P or else the act of reading has erased the information.
  • This restoration is eiiectuated here by applying the voltage pulse detected in the readin winding to the restore P instruction 2i (amplifying and shaping stages) which applies the tripping pulse to the write P" register to hold open the and gate 25.
  • the short pulse MP need be only of slightly longer duration than the natural turnover time of the memory core material. This single pulse prevents the drives to point P of the selected cores of both switch matrices and upon its termination cores are permitted to concurrently return to point N! by action of the biasing current, when N is to be written into the memory core, This greatly simplifies timing problems since the longer pulse PP need not have accurately timed edges. Its only function is to obtain non-coincidence of the output pulses of the switching matrices when P is to be written into the memory core. The only requirement for pulse PP is that it should terminate at least one natural turnover time of the memory core material after the termination of pulse MP.
  • the master pulse former l9 the only element requiring accurate timing and shaping is the master pulse former l9.
  • This circumstance allows great flexibility of control because control of the magnitude of the master pulse MP together with that of pulse PP may be employed to control the output of all current amplifiers of both switching matrices and because the edges of master pulse MP may be shaped in any desired manner to compensate for non-linearity of such amplifiers and for other effects which tend to make the N and P output pulses of the switches differ in shape.
  • circuits represented by block diagrams and generally described herein are well known in the prior art and have many suitable alternative forms. Suitable multivibrator circuits, wave shaping circuits, delay circuits and gate circuits are all described at length in Waveforms by Chance and others in the Radiation Laboratory Series, volume 19, published by the McGraw- Hill Publishing Company.
  • the one-shot multivibrators are described on page 166 et seq. and are described as monostable multivibrators.
  • Other suitable and gate circuitry, otherwise known as switch or multicoincidence circuits, are described on page 377 et. seq. of the same book.
  • the master pulse is not necessary that the master pulse be the shorter one of the pair.
  • the portion PC of Figure 5 may be replaced with the system shown in Figure 5A.
  • the master pulse former 19 here produces in response to a pulse applied to terminal l8 a pulse MP which has a duration of at least two natural turn over times of the magnetic core storage material.
  • the power amplifier 20 distributes this pulse to all the X and Y amplifiers VCl-VCIQ, VRl-VRIO.
  • a delay circuit 24A is operated.
  • This circuit may be a monostable multivibrator, delay line or any circuit capable of producing a delay of the order of one natural turnover time of the storage material.
  • the write P pulse former 24B is operated.
  • the pulse (PP) should start about half way through MP and should terminate a little after MP has terminated. If it is desired to write P this pulse is allowed to pass through and" gate 3 (25) and then via line 29 to the power amplifier (30). If it is desired to write P this amplifier produces a negative going pulse PY which is fed to all Y amplifiers on line 23A.
  • a typical gate and amplifier used to drive a row or column coil in the Y switch is shown in Figure 5B.
  • the master pulse MP is applied by means of line 23 to the grid of tube 43 via a resistor 4
  • the function of the condenser is to carry the fast leading and trailing edges of pulse MP.
  • the grid of tube 43 will rise when MP is applied and hence cause current to flow in the switch coils, provided that neither diode 44 nor diode 45 is conducting.
  • Diode 45 is employed as the address switching element.
  • all terminals 46 are held negative, except for the two selected tubes associated with the desired cores which are made positive.
  • Line 23A is always positive during the first half of MP and hence if terminal 46 is positive tube 43 will con- 9 duct. If it is desired to write 1? line 23A goes negative during the last half of MP and hence tube 43 ceases to conduct due to the signal to the grid being shunted by diode 44. Thus by terminating the action of the Y amplifiers early a P is stored in the matrix.
  • control of MP only controls all amplifiers.
  • the amplifier shown in Figure B may also be used for the driving amplifiers for the X switch if desired. In that case, however, line 23A and terminal 46 may be omitted.
  • Magnetic memory matrices are particularly suited to parallel. operation, the storage or memory unit consisting of as many matrices as there are binary digits X in the word. The same position is selected in every matrix and the reading windings provide the parallel output.
  • the length of the second control pulse is determined by a write P pulse former 24.
  • the duration of the master pulse need be only slightly greater than twice the time require-:1 for the memory cores to change their magnetic state, and the duration of the control pulse need be only about half that of the master pulse.
  • the switch S-MX of Figures 6 and 8 need not be, but is preferably, of the type shown in Figure 5 and discussed above: the switches MSYi-MSYS of Figures 6 and 8 may also be of the type shown in Figure 5.
  • a plurality of paralleloperated memory matrices are provided with a single X-switch SMX, each of Whose cores is provided with an output coil which is also a column coil in all the memory matrices.
  • separate X switches may be used for each matrix driven by one common set of X drivin tubes.
  • an individual Y-switch specifically, each of the cores of switch MSYI is provided with an output coil which is also a row coil for a different row of cores in the associated memory matrix MM! and similarly each of the cores of the switches MSY2, MSY3 provides for energization of a corresponding row coil of the associated memory matrices MM2, MM3, respectively.
  • the common driver VR of the Y-switches I ⁇ ISYi-MSY3 and the driver VC of the X-switch SMX are both controlled by the master puls as applied through output lines 2
  • Each of the Y-switches MSYI- MSYt has common to all of its cores a pulsed winding in addition to or common with its D. C. bias winding ( Figures 7A-7C).
  • the pu1sed winding I3P is distinct from the bias winding I 3D although it may be the same winding l3, as in Figures 7B, 70.
  • Each core of each Y-switch is arranged to operate upon the occurrence of a triple coincidence which arises when the corresponding address or information lines are set up and the common pulsed winding is operated.
  • the driver tubes in V0 have been addressed for selection of core IUX of switch SMX and the driver tubes in VB have been addressed for selection of cores IBYI, W2 and 1Y3 of switches MSYE-MSY3Q
  • the driver tubes in VC are gated by the masterpulse, the selected switch core [BX is driven to point P ( Figure 2) to produce a first output pulse energizing the common column coil C of all memory matrices.
  • This column coil includes the X windings of the memory matrix cores lllMl, IDMZ, IOM3.-
  • the pairs of input coils respectively including coils II and coils 12 of cores lflYl, IOYZ and W3 are energized.
  • the master pulse is applied through line 3
  • These tubes energize the common core winding i3P of each Y switch and therefore triple coincidence occurs at cores IUYI, "1Y2, IOY3.
  • the gate is of the type which has a normal input and an inhibiting input.
  • the normal input is passed thru the gate except in the presence of the inhibiting input. Accordingly, the switch cores IOYI, IOY2, and W3 of the Y switches MSYI-MSY3 each shift to point P of their hysteresis characteristic. The resulting change or flux in each of these cores induces current in its output winding to effect energization of the corresponding row coil RI, R2, R3 of the associated memory matrix MMI, MM2, MM3.
  • each of the cores IBMI, IBMZ, IOM3 f the memory matrices is switched from the N- state to the P-state by the master pulse at or near he beginning of the program cycle.
  • the energization of the common core winding I3P of the corresponding Y-switch is materially reduced or cut off early in the program cycle by an inhibiting pulse which commences at the end of the pulse generated by the write P pulse 24.
  • an inhibiting pulse which commences at the end of the pulse generated by the write P pulse 24.
  • an inhibiting pulse output of the and gate I or and gate 2 closes gate 25Y2, thus shortening the master pulse as applied to the common core winding B of switch MSYZ.
  • the core W2 is shifted back to NI or N2 of its characteristic well before the core IOX is returned to its N-state, upon termination of the master pulse, by the common D. C. winding B of switch SMX. Because of the non-coincidence of the second output pulses of cores W2 and IIJX, the core IOMZ is left in the P-state to which it was driven near the beginning of the program cycle by coincidence of the output pulses of cores IDX, IDYZ.
  • the gates 25YI, 25Y3 are so controlled during the program cycle so that the shortened control pulse is not efiectively applied to switches MSYI and MSY3. Consequently upon termination of the master pulse, the output pulses of each of switch cores IBYI and IOY3 are each coincident with the output pulse of switch core IIIX and the cores IIIMI, IIJM3 of the memory matrices MMI, MM3 are consequently driven back to N-saturation.
  • the No. 3 and gates for the individual Y-switch channels are of the type which remain open for transmission of the whole master pulse unless closed by a writeP pulse resulting either from an instruction to write-P or from a write-P instruction from the reading amplifier, if, upon an instruction to read that amplifier, the selected core of the corresponding memory matrix is in the P- state.
  • the No. I and gates and the No. 2 "and gates are also of a similar type.
  • the write-P pulse former produces a pulse which commences at the same time as the master pulse but has one half the duration. This pulse inhibits the and No. I and the No. 2 gates. These gates when operated inhibit and No. 3 gate. Therefore during the first half of the pulse from the write-P pulse former all and No. 3 gates are always open. Thus the first half of the master pulse is always fed to all switches. If an instruction to write-P has been given on a particular line, and gate No. 2 will operate when the pulse from the 12 Write-P pulse former has finished. This in turn will inhibit and gate No. 3 and hence shorten the pulse applied to the winding I3P.
  • gate I is primed by the instruction to read line.
  • This gate cannot operate during the existence of the pulse from the write-P pulse former but can operate after it terminates if a suitable signal is transmitted from the reading circuit 27 to and gate I.
  • This circuit is so arranged that if the information read out from the matrix indicates a P-state then the signal from the circuit will be such as to maintain a level which will prime and No. I. Hence if P-state is detected in the matrix then and No. I is operated which inhibits and No. 3 which shortens the pulse in coil I3P and hence the matrix core is left in the P-stage.
  • the reading circuit 2! can for example consist of a suitable amplifier coupled to the output of the reading coil of a magnetic memory matrix.
  • the amplifier drives a monostable multivibrator of the type previously referred to herein.
  • the output of the multivibrator is used to prime and gate I.
  • a suitable reading circuit of this general type may be found described in an application by L. B. Person, filed March 28, 1952, Serial No. 279,113, entitled Magnetic Memory Matrix Writing System and assigned to this assignee.
  • a pulse from the master pulse former is applied to the X and Y switch driver tubes and through and gate 3 to the winding I3P.
  • the and gate 3 remains open as long as no inhibit pulse is received from either and gate I or and gate 2.
  • gate I has two normal inputs and one inhibit input.
  • gate 2 has one normal input and one inhibit input.
  • the inhibit inputs to and gates I and 2 are provided by the output of the P pulse which generates a pulse simultaneously with the master pulse former but half its duration.
  • the and gate I requires an input from both the reading circuit and an instruction to read line to provide an output.
  • And gate 2 provides an output from the instruction to write P line.
  • the restoring action may be delayed more than in some other magnetic types of commutators due both to the smaller magnitude of the restoring force and to distortion of the restoring pulse by inductive lag in the inhibiting winding. Such delay, however, is of no consequence as the restoring pulse is not utilized for resetting.
  • the resetting of this system occurs when all switching cores are returned to their N point by the biasing windings at termination of the master pulse.
  • the circuit may be modified as by inclusion of a delay line in the input to the master pulse former, or in its output circuit, so that the biasing pulse for switch MSYI-MSY3 is applied in advance of gating of the drivers.
  • control pulse input from pulse former 24 may be arran ed to control the restoration of the cores of switches MSYI-MSY3 in another manner.
  • the currents in the Y-switch drives are increased so that a double coincidence of pulses in a row and a column coil is required to shift one core of each switch MSYi-MSY3 from the N state.
  • the E coil or bias coil of any switch MSYI-MSY3 is energized by a pulse which provides a magnetomotive force in a direction N only if it is desired to leave the information core of the assomemory, each word containing 10 bits.
  • biasing coils of the cores may also serve as the N restore winding by injection of additional current during the N restore operation.
  • injection may be accomplished by a direct tube drive as in Figure 7B or by a pulse transformer 33 as in Figure 7C. In the latter case, it is permissible to allow the transformer 33 to swing positive for D. C. restoration purposes provided that the output pulse of the transformer 33 terminates after the master pulse.
  • the modification shown in Figure 8 is similar to that shown in Figure 6 except that the address for the Y-switches is divided, certain of the address inputs being supplied to all of the Y-switches and other of them being supplied to the individual Y-switches of the several memory matrices.
  • the driver group VR controls the column windings of all of the Y-switches MSYI- MSY3 and the driver groups VRRI-VRR3 respectively control the row windings of switches MSYI- MSY3.
  • the master pulse from the program control network MC gates the driver group V for the X-switch SMX and also gates the driver group VRC, common to the Y-switches MSYI-MSY3.
  • the remainder of the driver groups VRRI-VRR3 set the same address in each of the Y-switches MSYI-MSY3.
  • the operation of the driver groups VRRI-VRR3 may be individually terminated earlier in the program cycle under control of the write-P pulse former 24 and the individual gates 25YI-25Y3. Consequently, these driver groups combine in each of the Y-switches together with the action of the address drives and the common core winding B to provide a very flexible control mechanism.
  • This type of parallel operation is useful when the storage capacity of the memory matrices is small.
  • the arrangement of Figure is also useful when it is desired to store either in parallel or in serial manner.
  • gate I consists of three tubes I00, IIO. and I each having its anode connected to a common anode load I02, and its cathode connected to ground.
  • the grid I04 of the first tube I 00 is coupled to the write P pulse former 24 and to a negative bias source so that, in the absence of apulse, the tube I 00 is normally non-conducting.
  • the grid I I4 of the second tube H0 is coupled to the instruction to read line and to ground through a gridleak resistor so that, in the absence of a pulse, the tube H4 is normally conducting.
  • the grid I24 of the third tube I20 is coupled to the reading circuit 21 and to ground through a grid leak resistor so that, in the absence of a pulse, the tube is normally conducting. Therefore, the voltage at the junction I06 of the anodes of the three tubes is low and remains low until all three tubes are not conducting. This happens only in the absence of a pulse from the write P pulse former 24 and in the presence of pulses from the instruction to read line and from the reading circuit 21.
  • And gate 2 consists of two tubes I 30, I40 having a common anode load I32 and their cathodes connected to ground.
  • the grid I34 of the first tube I30 is coupled to the write P pulse former 24 and to a source of negative bias so that, in the absence of a pulse, the tube I30 is normally non-conducting.
  • the grid I44 of the second tube I40 is coupled to the instruction to the write P line and to ground through a grid leak resistor so that, in the absence of a pulse, the tube I40 is normally conducting. Therefore, the voltage at the junction I36 of the anodes of the tubes is low and remains low until both the tubes cease conduction. This happens in the absence of a pulse from the write P pulse former 24 and in the presence of a pulse from the instruction to write P line.
  • a first diode I50 has its anode connected to the anode Junction I06 of and gate I and a second diode I52 has its anode connected to the anode junction I36 of and gate 2.
  • the cathodes of the diodes are connected together and, through a voltage divider resistor I 54, to a negative bias source.
  • the diodes I50, I52 conduct in a limited manner.
  • An inverter tube I60 has its grid I62 coupled to a point H on the voltage divider I54.
  • And gate 3 consists of two tubes I10, I 80, the first I10 being a multigrid tube having its control grid I12 coupled to point H.
  • the suppressor grid I14 of the tube is connected to line 3IY.
  • the cathode is connected to ground and the anode is connected to B+ through a plate load resistor I16. Therefore, the tube I10 is in condition to conduct whenever it receives a pulse from line SIY, but only as long as point H is high, which condition prevails as long as either and gate i or and gate 2 remains closed. As soon as point H goes positive, point H goes negative and holds the tube I10 non-conductive in spite of any signals applied through line 3IY to the suppressor grid.
  • the second inverter tube I has its control grid I82 connected to a voltage divider I18 in which. the anode load I10 of the tube I10 is connected.
  • This second tube I80 is accordingly rendered conducting when a first tube I10 is cut-off and is out 01? when the tube I10 is conducting.
  • the anode of this second inverter I80 has its load resistor I86 connected into a voltage divider I88 from a lower point of which connection is made to the grid of tube 30Y1. It is to be understood that there is one set of this and gate circuitry for each memory. The next set of and gates is connected to 30Y2. The third set is connected to 38Y3 and so forth.
  • the circuitry shown in Figure 9 may be readily used.
  • the inverter tube I68 is omitted as well as divider I64 and points H and H are connected together.
  • gate 3 will only provide an output when either and gate l or "and gate 2 is opened (point I06 or 136 made high) and a pulse is applied from the master pulse former l9.
  • the arrangement of gates comprises apparatus for the selective termination of the operation of the drives applied to the magnetic switches by the drivers VC and VB or VRRI and VRC.
  • These drivers may be termed selective driving and holding means for the cores in the magnetic switches since they serve the purpose of selectively driving and holding the cores in the magnetic switches at a P polarity of magnetization.
  • the auxiliary coil having windings I3P may be included since although not selective in its action it is still ineifective without the aid of the drivers.
  • the memory and switching matrices have been represented by blocks.
  • the memory matrices each comprise a multiplicity of cores with windings arranged in a manner, as more fully disclosed in copending application filed September 30, 1950, for Magnetic Matrix Memory by J. A. Rajchman, bearing Serial Number 187,733, and assigned to this assignee, or in an article in the Preview of Scientific Instruments, September 1951, by Jay Forrester, and that the switching matrices comprise a plurality of cores with coils having the inductive relations shown in Figure 1 or Figures 7A-7C with the switching coils connected to form row and column windings and with the D. C.
  • the address pulse or the 1/ address pulse may be applied to more than one core of the switch, but both pulses are simultaneously applied to only one core and consequently only that core, as above explained, is driven from Ni to P ( Figure 2), the others, if excited at all, remaining in the region of N-saturation because of the D. C. bias.
  • the memory storage unit of Figures 6 and 8 is for three-digit words, but obviously such unit may be expanded for longer words by correspondingly increasing the number of memory matrices. In such expanded unit, all of the memory matrices and under control of the network MC by circuitry similar to that shown for matrices MMi-MM3 of these figures.
  • the operation of the switches from paired pulses simplifies and reduces the required control equipment.
  • the master pulse controls the timing of all critical operations, the problem of proper timing is greatly simplified and there is a minimum waste of time as it is not necessary to insert delay elements to allow for the turnover time of flip-flop circuits such as used in other program control systems.
  • the master pulse also provides an overall amplitude control of the driver current and shaping of it compensates for non-linearity of the amplifiers.
  • a most significant advantage of the invention is that it allows use of direct current inhibiting windings in the switches with the consequent advantages that:
  • a magnetic matrix arrangement comprising a plurality of magnetic cores each having a pair of switching windings, a biasing winding and an output winding, means for supplying direct current to said biasing windings to saturate all of said cores, means for initiating a pair of current pulses, means for respectively applying said pair of pulses to the pair of switching windings of a selected core of said plurality to effect a flux change despite energization of said biasing winding and so induce an output pulse of one polarity in said output winding upon initiation of coincidence of said pulses, and means for selectively terminating said pair of current pulses either at the same or different times, said biasing winding returning the selected core substantially to its original saturation upon a coincidence in the termination of said pair of pulses.
  • a switching arrangement for a magnetic memory matrix of the type including a plurality of magnetic cores and two sets of selecting coils, and wherein the addressing of a core in said memory requires coincident excitation of one coil in each set which is coupled to said core, said switching arrangement comprising a first and a second magnetic switch each comprising a plurality of magnetic cores, each core having a biasing winding, means for supplying direct current to said biasing winding of each core to saturate all of said switch cores at one magnetic polarity, each of the cores of said first magnetic switch being inductively coupled to a different one of said first set of coils, each of the cores of said second magnetic switch being inductively coupled to a difierent one of said second set of coils, means to initiate a master pulse, a means for each of said switches to selectively drive and hold a desired one of the cores in each switch toward saturation at the opposite magnetic polarity responsive to the application of said master pulse, whereby a core in said magnetic memory matrix which is inductive
  • a switching arrangement as recited in claim 2 wherein said means to render inoperative the hold of each or said means to selectively drive and hold a desired one of the cores at different times includes means to generate a pulse simultaneously with and of longer duration than said master pulse, a closed gate, means to apply said longer duration pulse to the input of said closed gate, means to apply said signal to said gate to open said gate, and means to apply the output from said gate to said means to selectively drive and hold a desired one of the cores of said second switch to thereby maintain it operative beyond the duration of said master pulse.
  • a switching arrangement as recited in claim 2 wherein said means to render inoperative the hold of each said means to selectively drive and hold a desired one of the cores at different times includes means to generate a pulse at least equal to and during the latter half of said master pulse, a closed gate means to apply said half pulse to the input of said closed gate, means to apply said signal to said gate to open said gate, and means to apply the output of said gate in opposition to said master pulse to said means to selectively drive and hold a desired one of the cores in said second switch.
  • said means responsive to a signal to nullify the hold of one of said means to selectively drive and hold a desired one of the cores before the termination of operation of the other includes a closed gating means, means to apply said master pulse to said closed gating means, means coupling the output of said gating means to said biasing windings of the cores of said first switch, means to apply said signal to said gating means to render it open to thereby apply said master pulse to said biasing windings in a direction to nullify the hold of one of said means to selectively drive and hold a desired one of said cores toward saturation at the opposite magnetic polarity.
  • a magnetic switching arrangement for a magnetic memory matrix of the type including a plurality of magnetic cores and two sets of selecting coils, addressing any core in said memory requiring coincident excitation of one coil in each set which coupled to said core, said switching arrangement comprising a first and a second magnetic switch each comprising a plurality of magnetic cores, each core having a pair of switching windings and a biasing winding, means for supplying direct current to said biasing windings to saturate all of said cores, each of the cores of said first magnetic switch being respectively coupled to a different one of said first set of coils, each of the cores of said second magnetic switch being respectively coupled to a different one of said second set of coils, means for initiating two pairs of current pulses, means for initiating a master pulse, means responsive to said master pulse for applying one pair of said current pulses to the pair of switching windings of a desired core in said first magnetic switch, means responsive to said master pulse for applying the other pair of said current pulses to the pair of switching winding
  • a magnetic switching arrangement for a plurality of parallel-operated magnetic memory matrices comprising an X switch common to said memory matrices, a driver for said X switch set in accordance with the X address of information for said memory matrices, a plurality of Y switches, one for each of said memory matrices, a common driver for said Y switches set in accordance with the Y address of information for said memory matrices, each of said Y switches comp-rising magnetic cores having windings selectively energized from the common Y driver and having a common D.
  • a program con-' trol network including a master pulse former and a second pulse former, circuitry for applying the output of said master pulse former to gate both of said drivers, a plurality of gates each efiectively interposed between one of said Y switches and said second pulse former, and means individually to control said gates selectively to effect in each memory matrix either coincidence or non-coincidence of termination of pulses respectively from the common X switch and from the Y switch individual to that matrix.
  • each 1 the gates is in circuit between said second pulse former and a common winding of the cores of the corresponding Y switch.
  • the common driver for the Y switches is set by some of the Y address information, which additionally includes drivers, one for each of the Y switches, set by the remainder of the Y address information, and in which each of the gates is interposed between the second pulse former and and a common winding of the cores of the associated Y switch to permit or to preclude passage of a driving pulse.
  • a system including a magnetic memory matrix and two magnetic switching matrices characterized in that each of said switching matrices includes a plurali y of magnetic cores each having a pair of switching windings, a biasing winding and an output winding; means for supplying direct current to the biasing windings of all cores of both switching matrices normally to saturate them, means for initiating a switching pulse simultaneously applied to the switching windings of a selected core of each of said switching matrices and for concurrently initiating a second switching pulse, the concurrent energization of both switching windings of each selected core producing an output pulse despite the biasing winding, the two output pulses of the selected cores of the switches effecting reversal of the direction of saturation of a selected core of the memory matrix, and means for applying said second switching pulse to, or withholding it from, one of said selected cores whereby the output pu ses of the selected switching cores are either coincident to return the selected core of the memory matrix to its original direction of saturation or
  • a magnetic switching arrangement for a plurality of parallel-operated magnetimmemory matrices comprising an X magnetic switch common to all of said matrices and a plurality of Y magnetic switches, one for each of said matrices, all of said magnetic switches each comprising a plurality of magnetic cores each having at least a pair of pulse windings, a biasing winding and an output winding, the biasing windings of the cores of each switch being connected to form a biasing coil for the switch, gated drive means for said common magnetic switch, gated drive means for said plurality of magnetic switches, and a program control network comprising two pulse formers connected to a to write or read instruction line, connections for applying the output of one of said pulse formers to both of said gated drive means, and connections for applying the output of the other of said pulse formers respectively to modify the eiiect of the biasing coil of each of said plurality of Y switches, each of said last-named connections including a gating device selectively permitting or pre
  • a program control network having the characteristic that information to be stored in the memory matrix is available for read-out during the write-in period of the program cycle comprising a master pulse former and a second pulse former, both simultaneously responsive to an instruction to write or read, circuitry for applying the output of said master pulse former to both of said switching matrices to turn over a selected core of said memory matrix, said circuitry including a gate in the pulse path to one of said switches, and circuitry including a second gate for control of said first gate selectively to efiect either coincidence or noncoincidence of return of said switching matrices to their original state so to leave said memory core turned over or to return it to its original state, said second gate having applied thereto the output of said second pulse former, the output of said read-out circuit which is of zero or finite value depending upon the state of said selected core, and an instruction to read.
  • a program control network comprising a master pulse former and a second pulse former, both simultaneously responsive to an instruction to write or read, circuitry for applying the output of said master pulse former to both of said switching matrices to turn over a selected core of said memory matrix, said circuitry including a gate in the pulse path to one of said switches, and circuitry including a second gate for control of said first gate selectively to effect either coincidence or non-coincidence of return of said switching matrices to their original state so as to leave said memory core turned over or to return it to its original state, said second gate having applied thereto the output of said second pulse former, and an instruction to write.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Electronic Switches (AREA)
  • Magnetic Resonance Imaging Apparatus (AREA)
  • Digital Magnetic Recording (AREA)
  • Electromagnets (AREA)
US346162A 1952-10-29 1953-02-20 Memory system Expired - Lifetime US2691155A (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
US346162A US2691155A (en) 1953-02-20 1953-02-20 Memory system
US33790253 US2734184A (en) 1953-02-20 1953-02-20 Magnetic switching devices
CH331049D CH331049A (de) 1952-10-29 1953-10-29 Verfahren zur Herstellung eines Penicillinsalzes
GB3497/54A GB753025A (en) 1953-02-20 1954-02-05 Magnetic switching devices
FR1095967D FR1095967A (fr) 1953-02-20 1954-02-12 Commutateur magnétique
CH323365D CH323365A (de) 1953-02-20 1954-02-16 Magnetische Schaltanordnung für magnetische Gedächtnisvorrichtungen.
BE526599D BE526599A (xx) 1953-02-20 1954-02-18
NL185257A NL93839C (xx) 1953-02-20 1954-02-19
JP318854A JPS307759B1 (xx) 1953-02-20 1954-02-20
DER13623A DE1051034B (de) 1953-02-20 1955-09-24 Magnetischer Schalter

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Also Published As

Publication number Publication date
JPS307759B1 (xx) 1955-10-26
FR1095967A (fr) 1955-06-08
DE1051034B (de) 1959-02-05
BE526599A (xx) 1956-08-17
CH323365A (de) 1957-07-31
GB753025A (en) 1956-07-18
US2734184A (en) 1956-02-07
NL93839C (xx) 1960-04-19

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